Redundant latching decoding circuit and memory

Abstract

The application discloses a redundancy latch circuit and a memory. The redundancy latch circuit comprises: a redundancy latch circuit comprising a plurality of redundancy latch regions, each redundancy latch region comprising at least one normal redundancy latch unit, and at least part of the plurality of redundancy latch regions being configured into at least one redundancy latch shared group, each redundancy latch shared group corresponding to at least two redundancy latch regions comprising at least one shared redundancy latch unit, and the at least two redundancy latch regions sharing the at least one shared redundancy latch unit; and a redundancy decoding circuit coupled to the redundancy latch circuit, and enabling a corresponding redundancy signal line to address a redundancy storage resource in the memory in response to an address matching a replacement address. In this way, the shared redundancy latch unit in the redundancy latch circuit can be shared by at least two redundancy latch regions, and can be shared and utilized by at least two storage regions, thereby improving the utilization rate of the replacement resource, saving the replacement resource and circuit area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a redundancy latch decoding circuit and a memory. BACKGROUND

[0002] In the manufacturing process of random memories, especially dynamic random memories (DRAM) or pseudo static random memories (PSRAM), there may be defects in the memory cells (MC) in the row direction, which cannot normally perform storage operations; or there may be defects in the memory cells in the column direction, which cannot normally perform storage operations. Therefore, in order to improve the yield of random memories, some spare circuits and spare memory cells are needed to replace the damaged word lines, bit lines and memory cells. These spare circuits and spare memory cells are collectively referred to as replacement (RDN) resources. Specifically, when there are defects in the memory cells in the row direction, row replacement is needed, which is called row redundancy; when there are defects in the memory cells in the column direction, column replacement is needed, which is called column redundancy.

[0003] Taking column redundancy as an example, the replacement of a damaged bit line is generally achieved by replacing an abnormal column selection communication signal line. The random memory includes a memory array and a redundancy latch circuit (RDN latch). The memory array includes a plurality of storage sections. The redundancy latch circuit includes a plurality of redundancy latch sections corresponding to the plurality of storage sections. Each redundancy latch section is used to latch the address of the abnormal column selection communication signal line in the corresponding storage section. However, the unused latch resources in the redundancy latch section cause a waste of replacement resources and circuit area. SUMMARY

[0004] In order to solve the above problems, the present application provides a redundancy latch decoding circuit and a memory, which can share part of the latch resources, thereby improving the utilization efficiency of the replacement resources, saving the replacement resources and circuit area.

[0005] To solve the above technical problems, one technical solution adopted by the present application is: a redundant latch circuit, comprising a plurality of redundant latch areas corresponding to a plurality of storage areas of the memory, wherein each of the redundant latch areas comprises at least one normal redundant latch unit, and at least part of the plurality of redundant latch areas is configured into at least one redundant latch sharing group, each of the redundant latch sharing groups comprises at least one shared redundant latch unit, each of the redundant latch sharing groups corresponds to at least two redundant latch areas, and the at least two redundant latch areas share the at least one shared redundant latch unit; and a redundant decoding circuit coupled to the redundant latch circuit to receive a replacement address, wherein in response to the matching of the addressing address and the replacement address, the redundant decoding circuit enables a corresponding redundant signal line to address a redundant storage resource in the memory.

[0006] Wherein the at least one shared redundant latch unit is arranged in one of the at least two redundant latch areas, and the other of the at least two redundant latch areas corresponding to the redundant latch sharing group shares the at least one shared redundant latch unit; or the at least one shared redundant latch unit is arranged in the at least two redundant latch areas, and the at least two redundant latch areas corresponding to the redundant latch sharing group share the at least one shared redundant latch unit.

[0007] Wherein each of the redundant latch sharing groups corresponds to two adjacent redundant latch areas, each of the redundant latch areas comprises n normal redundant latch units, any of the redundant latch sharing groups comprises m shared redundant latch units, and the m shared redundant latch units are arranged in one of the two redundant latch areas, and the other of the two redundant latch areas can share the m shared redundant latch units, and the redundant latch area corresponding to any of the storage areas is configured to comprise (n+m) redundant latch units; or each of the redundant latch sharing groups corresponds to three adjacent redundant latch areas, each of the redundant latch areas comprises n normal redundant latch units, any of the redundant latch sharing groups comprises m shared redundant latch units, and the m shared redundant latch units are arranged in one of the three redundant latch areas, and the other of the three redundant latch areas can share the m shared redundant latch units, and the redundant latch area corresponding to any of the storage areas is configured to comprise (n+m) redundant latch units.

[0008] The redundant latch circuit includes a redundant latch array including the plurality of redundant latch regions and receiving a bad block address, storage region indication information and a reset signal to latch the bad block address to the corresponding redundant latch region bit by bit; a selection circuit coupled to the redundant latch array to receive an address bit; the selection circuit also receives a first group of selection signals and a second group of selection signals, wherein the selection circuit determines a current redundant latch region corresponding to a current operation storage region based on the first group of selection signals, and determines a current redundant latch sharing group corresponding to the current redundant latch region based on the second group of selection signals, to selectively output a first replacement address composed of the address bit latched by the normal redundant latch unit in the current redundant latch region and a second replacement address composed of the address bit latched by the shared redundant latch unit corresponding to the current redundant latch sharing group.

[0009] The first group of selection signals includes a plurality of first selection signals cooperating to select the current redundant latch region from the plurality of redundant latch regions; and the second group of selection signals includes a plurality of second selection signals cooperating to select the current redundant latch sharing group corresponding to the current redundant latch region from the at least one redundant latch sharing group.

[0010] The redundant decoding circuit is coupled to the selection circuit, wherein, when performing an addressing operation, the redundant decoding circuit compares the first replacement address and the second replacement address with an addressing address respectively; in response to the addressing address matching any one of the first replacement address and the second replacement address, the redundant decoding circuit enables the corresponding redundant signal line to address the redundant storage resource in the memory.

[0011] The redundant decoding circuit includes a first redundant decoding unit coupled to the selection circuit and receiving an addressing address; wherein, when performing the addressing operation, the first redundant decoding unit compares the first replacement address and the second replacement address with the addressing address respectively, and based on the addressing address matching any one of the first replacement address and the second replacement address, generates a corresponding redundant enable signal; a second redundant decoding unit coupled to the first redundant decoding unit and receiving the addressing address, wherein, when performing the addressing operation, in response to the first redundant decoding unit generating the corresponding redundant enable signal, the second redundant decoding unit masks the addressing address and enables the corresponding redundant signal line based on the redundant enable signal to address the corresponding redundant storage resource in the memory; in response to the first redundant decoding unit not generating the corresponding redundant enable signal, the second redundant decoding unit enables the corresponding normal signal line based on the addressing address to normally address the corresponding normal storage resource in the memory.

[0012] The redundancy latch circuit includes a column redundancy latch circuit, the redundancy decoding circuit includes a column redundancy decoding circuit, the redundancy signal line includes a redundancy column selection signal line, the normal signal line includes a normal column selection signal line, and the memory includes k memory areas in the row direction.

[0013] The number of normal signal lines is x, and the number of redundancy signal lines is y. In response to one of the y redundancy enable signals being set, the second redundancy decoding unit enables one of the corresponding y redundancy signal lines. In response to none of the y redundancy enable signals being set, the second redundancy decoding unit enables one of the corresponding x normal signal lines based on the addressing address.

[0014] The first redundancy decoding unit includes a plurality of logic gate circuits, each of which receives one of the first replacement address and the second replacement address and the addressing address to compare one of the first replacement address and the second replacement address with the addressing address. The logic gate circuit includes a logic exclusive OR gate circuit.

[0015] To solve the above technical problems, another technical solution adopted by the present application is to provide a memory including the redundancy latch decoding circuit described above.

[0016] The beneficial effects of the embodiments of the present application are that, unlike the prior art, the redundancy latch decoding circuit provided by the present application is applied to a memory and includes a redundancy latch circuit including a plurality of redundancy latch areas corresponding to a plurality of memory areas of the memory. Each redundancy latch area includes at least one normal redundancy latch unit, and at least part of the plurality of redundancy latch areas is configured into at least one redundancy latch sharing group. Each redundancy latch sharing group includes at least one shared redundancy latch unit, and each redundancy latch sharing group corresponds to at least two redundancy latch areas sharing the at least one shared redundancy latch unit. The memory further includes a redundancy decoding circuit coupled to the redundancy latch circuit to receive a replacement address. In response to an addressing address matching the replacement address, the redundancy decoding circuit enables a corresponding redundancy signal line to address a redundancy storage resource in the memory. In this way, the shared redundancy latch unit in the redundancy latch circuit can be shared by at least two redundancy latch areas and thus can be shared and utilized by at least two memory areas, thereby improving the utilization rate of replacement resources, saving replacement resources, and saving circuit area. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced. Obviously, the drawings in the following description only relate to some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without any creative effort based on these drawings also fall within the protection scope of the present application.

[0018] In the formula, the redundant latch decoding circuit is provided by the present application.

[0019] Figure 1 is a structural schematic diagram of an embodiment of the redundant latch decoding circuit provided by the present application;

[0020] Figure 2 is a structural schematic diagram of another embodiment of the redundant latch decoding circuit provided by the present application;

[0021] Figure 3 is a structural schematic diagram of an embodiment of the redundant latch array or the redundant latch circuit provided by the present application;

[0022] Figure 4 is a structural schematic diagram of another embodiment of the redundant latch array or the redundant latch circuit provided by the present application;

[0023] Figure 5 is a structural schematic diagram of an embodiment of the redundant decoding circuit provided by the present application;

[0024] Figure 6 is a structural schematic diagram of an embodiment of the first redundant decoding unit provided by the present application;

[0025] Figure 7 is a structural schematic diagram of an embodiment of the memory provided by the present application;

[0026] Figure 8 is a structural schematic diagram of an embodiment of the memory array provided by the present application;

[0027] Figure 9 is a structural schematic diagram of another embodiment of the memory provided by the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, and not all the structures. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the protection scope of the present application.

[0029] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0030] The application provides a redundancy latch decoding circuit, which is applied to a memory and includes: a redundancy latch circuit including a plurality of redundancy latch areas corresponding to a plurality of storage areas of the memory, wherein each of the redundancy latch areas includes at least one normal redundancy latch unit, and at least part of the plurality of redundancy latch areas is configured into at least one redundancy latch sharing group, each of the redundancy latch sharing groups includes at least one shared redundancy latch unit, and each of the redundancy latch sharing groups corresponds to at least two redundancy latch areas sharing the at least one shared redundancy latch unit; and a redundancy decoding circuit coupled to the redundancy latch circuit to receive a replacement address, wherein, in response to an address address matching the replacement address, the redundancy decoding circuit enables a corresponding redundancy signal line to address a redundancy storage resource in the memory. In this way, the shared redundancy latch unit in the redundancy latch circuit can be shared by at least two redundancy latch areas, and thus can be shared and utilized by at least two storage areas, thereby improving the utilization rate of replacement resources, saving replacement resources and circuit area.

[0031] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of an embodiment of the redundancy latch decoding circuit provided by the application. The redundancy latch decoding circuit 100 is used to latch a bad block address and decode a replacement address to activate a corresponding replacement resource (such as a redundancy signal line), and can also perform normal addressing. It can be understood that in the manufacturing process of a random memory, especially a dynamic random memory, there can be defects in the storage units in the row direction, which cannot normally perform storage operations; or there can be defects in the storage units in the column direction, which cannot normally perform storage operations. Therefore, in order to improve the yield of the random memory, some spare circuits and spare storage units need to be added to replace the damaged word lines, bit lines and storage units. These spare circuits and spare storage units are collectively referred to as replacement resources. Specifically, when there are defects in the storage units in the row direction, row replacement is needed, and when there are defects in the storage units in the column direction, column replacement is needed.

[0032] The redundant latch decoding circuit 100 can include, but is not limited to, a redundant latch circuit 140 and a redundant decoding circuit 130. In the present embodiment, the redundant latch circuit 140 can latch the bad block address and can output the address of the replacement resource (e.g., redundant signal line) corresponding to the section of the currently active word line (WL). The redundant decoding circuit 130 is used to decode the replacement address to activate the corresponding replacement resource, or to perform normal addressing. The replacement address refers to the address of the replacement resource (e.g., redundant signal line) corresponding to the section of the currently active word line (WL). The redundant latch decoding circuit 100 can be applied in row replacement technology, or can be applied in column replacement technology. That is, the redundant latch circuit 140 includes a column redundant latch circuit and a row redundant latch circuit. The redundant decoding circuit 130 includes a column redundant decoding circuit and a row redundant decoding circuit. The redundant signal line includes a redundant column select signal line and a redundant row select signal line. The present embodiment takes the redundant latch decoding circuit 100 applied in column replacement technology as an example.

[0033] Specifically, the redundant latch circuit 140 includes the aforementioned plurality of redundant latch sections, and in a further embodiment, further receives the bad block address BFBIT <a-1:0>, storage area indication information EFLATCOLT<*> and a reset signal RST, so as to latch the bad block address to the corresponding redundant latching area bit by bit. In further embodiments, the bad block address BFBIT <a-1:0>EFLATCOLT* is the address information of the storage resource damaged in the row direction or the column direction. The storage area indication information EFLATCOLT* is the information of the storage area where the bad block address is located. <a-1:0>and storage zone indication information EFLATCOLT* can be obtained by pre-testing the storage resources in the memory and stored in a programmable storage module (EFUSE). When the programmable storage module is powered on, the bad block address BFBIT <a-1:0>and the storage area indication information EFLATCOLT<*> are delivered to the redundancy latching circuit 140. The redundancy latching circuit 140 also receives the first group of selection signals CRFT0<*> and the second group of selection signals CRFT1<*> to output the replacement address CRCAT<a-1:0> to the redundancy decoding circuit 130. The redundancy decoding circuit 130 is coupled to the redundancy latching circuit 140 to receive the replacement address CRCAT<a-1:0> (e.g., one of CRCAT1<a-1:0>~CRCATy<a-1:0> in Figure 1 response to the addressing address CA<a-2:0> matching the replacement address CRCAT<a-1:0> (the replacement address CRCAT<a-1:0> further includes information of whether the replacement resource is normal, thus one more bit than the addressing address CA<a-2:0>), the redundancy decoding circuit 130 enables the corresponding redundancy signal line RYST to address the redundant storage resource in the memory. The redundant storage resource is used to replace the damaged storage resource in the memory. In response to the addressing address CA<a-2:0> not matching the replacement address CRCAT<a-1:0>, the redundancy decoding circuit 130 enables the corresponding normal signal line YST to address the normal storage resource in the memory based on the addressing address CA<a-2:0>. The redundancy decoding circuit 130 also receives the clock signal CYCLKB to decode the addressing address CA <a-2:0>, thereby enabling the corresponding normal signal line YST.

[0034] Please refer to Figure 1 , Figure 3 and Figure 4 , Figure 3 is a structural schematic diagram of an embodiment of the redundancy latch array or the redundancy latch circuit provided by the present application, Figure 4 is a structural schematic diagram of another embodiment of the redundancy latch array or the redundancy latch circuit provided by the present application. For example Figure 1 The redundancy latch circuit 140 shown in FIG. 1 1 includes a plurality of redundancy latch areas 1 1 1 corresponding to a plurality of storage sections of a memory. Each redundancy latch area 1 1 1 includes at least one normal redundancy latch unit 1 1 1 1, and at least part of the plurality of redundancy latch areas 1 1 1 are configured into at least one redundancy latch sharing group 1 12. Each redundancy latch sharing group 1 12 includes at least one shared redundancy latch unit 1 12 1. Each redundancy latch sharing group 1 12 corresponds to at least two redundancy latch areas 1 1 1. At least two redundancy latch areas 1 1 1 share at least one shared redundancy latch unit 1 12 1. In this way, the shared redundancy latch unit 1 12 1 in the redundancy latch circuit 100 can be shared by at least two redundancy latch areas 1 1 1, and thus can be shared and utilized by at least two storage sections to store replacement addresses, thereby improving the utilization rate of replacement resources, saving replacement resources and circuit area.

[0035] Please refer to Figure 2 , Figure 2 is a structural schematic diagram of another embodiment of the redundancy latch decoding circuit provided by the present application. The redundancy latch decoding circuit 100 is used to latch a bad block address and decode a replacement address to activate the corresponding replacement resource (such as a redundancy signal line), while also performing normal addressing. It can be understood that in the manufacturing process of a random memory, especially a dynamic random memory DRAM or a pseudo-static random memory PSRAM, there can be defects in the storage units in the row direction, which cannot normally perform storage operations; or there can be defects in the storage units in the column direction, which cannot normally perform storage operations. Therefore, in order to improve the yield of the random memory, some spare circuits and spare storage units need to be added to replace the damaged word lines, bit lines and storage units. These spare circuits and spare storage units are collectively referred to as replacement resources. Specifically, when there are defects in the storage units in the row direction, row replacement is needed, and when there are defects in the storage units in the column direction, column replacement is needed.

[0036] The redundancy latch decoding circuit 100 can include, but is not limited to, a redundancy latch array 1 10, a selection circuit 120 and a redundancy decoding circuit 130. The redundancy latch circuit 140 includes the redundancy latch array 1 10 and the selection circuit 120. Figure 1 The plurality of redundant latch regions 111 shown forms a redundant latch array 110 for bit-wise latching bad block addresses. The selection circuit 120 is used to select a bad block address corresponding to a section of a currently active word line (WL) from all bad block addresses. The redundant decoding circuit 130 is used to decode a replacement address (e.g. an address of a redundant signal line) to activate a corresponding replacement resource (e.g. a redundant signal line) or to perform normal addressing. The replacement address corresponds to a bad block address corresponding to a section of a currently active word line (WL). The redundant latch decoding circuit 100 can be applied in a row replacement technique or in a column replacement technique. That is, the redundant latch circuit 140 includes a column redundant latch circuit and a row redundant latch circuit. The redundant decoding circuit 130 includes a column redundant decoding circuit and a row redundant decoding circuit. The redundant signal line includes a redundant column select signal line (or a redundant bit line) and a redundant row select signal line (or a redundant word line). The present embodiment takes the redundant latch decoding circuit 100 applied in a column replacement technique as an example.

[0037] Please refer to Figure 2 , Figure 3 and Figure 4 . The redundant latch array 110 includes a plurality of redundant latch regions 111 corresponding to a plurality of sections of a memory. Each redundant latch region 111 includes at least one normal redundant latch unit 1111. At least a portion of the plurality of redundant latch regions 111 is configured into at least one redundant latch sharing group 112. Each redundant latch sharing group 112 includes at least one shared redundant latch unit 1121. Each redundant latch sharing group 112 corresponds to at least two redundant latch regions 111. The at least two redundant latch regions 111 corresponding to each redundant latch sharing group 112 can share the at least one shared redundant latch unit 1121 in the redundant latch sharing group 112, thereby improving the utilization of redundant latch units, saving replacement resources and circuit area. In the present embodiment, the at least one shared redundant latch unit 1121 is disposed in one of the at least two redundant latch regions 111 corresponding to the redundant latch sharing group 112. The other of the at least two redundant latch regions 111 corresponding to the redundant latch sharing group 112 shares the at least one shared redundant latch unit 1121. In other embodiments, the at least one shared redundant latch unit 1121 is dispersedly disposed in the at least two redundant latch regions 111. The at least two redundant latch regions 111 corresponding to the redundant latch sharing group 112 share the at least one shared redundant latch unit 1121.

[0038] Further, please refer to Figure 3 and Figure 7 , Figure 7 is a structural diagram of an embodiment of the memory provided by the present application. In an embodiment, the redundant latch array 110 includes k redundant latch areas 111 corresponding to k storage areas of the memory, specifically including redundant latch area Latch_S1 to redundant latch area Latch_Sk. In the present embodiment, k is a positive integer greater than 1 and is a multiple of 6. In other embodiments, k can be any positive integer greater than 1. Each redundant latch sharing group 112 corresponds to two adjacent redundant latch areas 111. Each redundant latch area 111 includes n normal redundant latch cells 1111. Wherein, n is a positive integer. In the present embodiment, n can be equal to y-2, wherein y is a positive integer greater than 2. Any redundant latch sharing group 112 includes m shared redundant latch cells 1121, and the m shared redundant latch cells 1121 are disposed in one of the two adjacent redundant latch areas 111. Wherein, m is a positive integer. In the present embodiment, m can be equal to 2. The other of the two redundant latch areas 111 corresponding to the redundant latch sharing group 112 can share the m shared redundant latch cells 1121. The redundant latch area 111 corresponding to any storage area is configured to include (n+m) redundant latch cells. In the present embodiment, n+m is equal to y. The normal redundant latch cell 1111 and the shared redundant latch cell 1121, i.e. the redundant latch cell, includes a latch block, specifically including latch block Latch1_0 to latch block Latch1_a-1. The a latch blocks correspond to a bit of the bad block address respectively, for latching the address bit of the bad block address.

[0039] For example, if there is a damaged storage resource in the section<1>, the address of the damaged storage resource (bad block address) can be latched in any one of the normal redundant latching units 1111 in the redundant latching area Latch_S1 corresponding to the section<1> or in any one of the shared redundant latching units 1121 in the redundant latching sharing group 112 where the redundant latching area Latch_S1 is located. Similarly, if there is a damaged storage resource in the section<2>, the address of the damaged storage resource (bad block address) can be latched in any one of the normal redundant latching units 1111 in the redundant latching area Latch_S2 corresponding to the section<2> or in any one of the shared redundant latching units 1121 in the redundant latching sharing group 112 where the redundant latching area Latch_S2 is located. In this way, the redundant latching area Latch_S1 and the redundant latching area Latch_S2 are both configured to include (n+m) redundant latching units (n normal redundant latching units 1111 and m shared redundant latching units 1121). In this way, the redundant latching units available to the section<1> and the section<2> are not reduced (n+m normal redundant latching units are configured for each redundant latching area), but the total number of redundant latching units is saved, reducing the circuit area. In this embodiment, n+m normal redundant latching units are configured for each redundant latching area, and (k / 2*m) redundant latching units can be saved.

[0040] In other embodiments, the m shared redundant latching units 1121 included in each redundant latching sharing group 112 can be distributed on the two adjacent redundant latching areas 111 corresponding to the redundant latching sharing group 112. For example, when m=2, one shared redundant latching unit 1121 is arranged in the redundant latching area Latch_S1, and the other shared redundant latching unit 1121 is arranged in the redundant latching area Latch_S2.

[0041] Further, please refer to Figure 4 and Figure 7 In another embodiment, the redundant latch array 110 includes k redundant latch areas 111 corresponding to k storage areas of the memory, specifically including redundant latch area Latch_S1 to redundant latch area Latch_Sk. In this embodiment, k is a positive integer greater than 1 and is a multiple of 6. In other embodiments, k can be any positive integer greater than 1. Each redundant latch sharing group 112 corresponds to three adjacent redundant latch areas 111. Each redundant latch area 111 includes n normal redundant latch cells 1111. Here, n is a positive integer. In this embodiment, n can be equal to y-2, where y is a positive integer greater than 2. Any redundant latch sharing group 112 includes m shared redundant latch cells 1121, and the m shared redundant latch cells 1121 are disposed in one of the three adjacent redundant latch areas 111. Here, m is a positive integer. In this embodiment, m can be equal to 2. The other of the three redundant latch areas 111 corresponding to the redundant latch sharing group 112 can share the m shared redundant latch cells 1121. The redundant latch area 111 corresponding to any storage area is configured to include (n+m) redundant latch cells. In this embodiment, n+m is equal to y. The normal redundant latch cells 1111 and the shared redundant latch cells 1121, i.e., the redundant latch cells, include a latch blocks, specifically including latch block Latch1_0 to latch block Latch1_a-1. The a latch blocks correspond to a bit of the bad block address, respectively, for latching the address bits of the bad block address.

[0042] For example, if there is a defective storage resource in the storage section section<1>, the address of the defective storage resource (bad block address) can be latched in any one of the normal redundant latching units 1111 in the redundant latching section Latch_S1 corresponding to the storage section section<1> or in any one of the shared redundant latching units 1121 in the redundant latching sharing group 112 in which the redundant latching section Latch_S1 is located. Similarly, if there is a defective storage resource in the storage section section<2>, the address of the defective storage resource (bad block address) can be latched in any one of the normal redundant latching units 1111 in the redundant latching section Latch_S2 corresponding to the storage section section<2> or in any one of the shared redundant latching units 1121 in the redundant latching sharing group 112 in which the redundant latching section Latch_S2 is located. Similarly, if there is a defective storage resource in the storage section section<3>, the address of the defective storage resource (bad block address) can be latched in any one of the normal redundant latching units 1111 in the redundant latching section Latch_S3 corresponding to the storage section section<3> or in any one of the shared redundant latching units 1121 in the redundant latching sharing group 112 in which the redundant latching section Latch_S3 is located. In this way, the redundant latching section Latch_S1, the redundant latching section Latch_S2, and the redundant latching section Latch_S3 are each configured to include (n+m) redundant latching units (n normal redundant latching units 1111 and m shared redundant latching units 1121). In this way, the storage section section<1>, the storage section section<2>, and the storage section section<3> can utilize redundant latching units without a reduction (relative to each redundant latching section being configured with n+m normal redundant latching units), but overall save redundant latching units, reducing circuit area. In this embodiment, relative to each redundant latching section being configured with n+m normal redundant latching units, (k / 3*2m) redundant latching units can be saved.

[0043] In other embodiments, the m shared redundant latching units 1121 included in each redundant latching sharing group 112 can be distributed among the three adjacent redundant latching sections 111 corresponding to the redundant latching sharing group 112. For example, when m=2, one shared redundant latching unit 1121 is disposed in the redundant latching section Latch_S1 and the other shared redundant latching unit 1121 is disposed in the redundant latching section Latch_S3.

[0044] Please continue to refer to Figure 2 The redundant latching array 110 including a plurality of redundant latching sections 111 receives a bad block address BFBIT <a-1:0>, storage area indication information EFLATCOLT<*> and a reset signal RST, so as to latch the bad block address to the corresponding redundant latch area 111 bit by bit. Bad block address BFBIT <a-1:0>EFLATCOLT* is information indicating the address of a storage resource damaged in the row direction or the column direction. The storage area indication information EFLATCOLT* is information indicating the storage area (section) in which the bad block address BFBIT is located. <a-1:0>and storage zone indication information EFLATCOLT* can be obtained by pre-testing the storage resources in the memory and stored in a programmable storage module (EFUSE). When the programmable storage module is powered on, the bad block address BFBIT <a-1:0>and the storage area indication information EFLATCOLT<*> is delivered to the redundant latch array 110.

[0045] The selection circuit 120 is coupled to the redundant latch array 110 to receive the address bits. The selection circuit 120 also receives a first set of selection signals CRFT0<*> and a second set of selection signals CRFT1<*>. The selection circuit 120 determines a current redundant latch area corresponding to a current operating storage area based on the first set of selection signals CRFT0<*> to selectively output a first replacement address composed of the address bits latched in the normal redundant latch cells 1111 in the current redundant latch area. The current operating storage area refers to the storage area where the currently activated word line is located. The selection circuit 120 determines a current redundant latch sharing group corresponding to the current redundant latch area based on the second set of selection signals CRFT1<*> to selectively output a second replacement address composed of the address bits latched in the shared redundant latch cells 1121 corresponding to the current redundant latch sharing group. The current redundant latch sharing group refers to the redundant latch sharing group where the current redundant latch area is located. The replacement address includes the first replacement address and the second replacement address.

[0046] Further, the first set of selection signals CRFT0<*> includes a plurality of first selection signals, for example, including a first selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>wherein c, d are positive integers greater than 0. The plurality of first selection signals cooperate to select a current redundancy latching area from the plurality of redundancy latching areas 111. The second set of selection signals CRFT1<*> includes a plurality of second selection signals, for example, including second selection signals CRF1T1 <e:0>and a second select signal CRF2T1 <d:0>where e is a positive integer greater than 0. The plurality of second selection signals cooperate to select a current redundant latch sharing group from the at least one redundant latch sharing group 112, which determines the current redundant latch area.

[0047] In particular, reference is made to Figure 2 and Figure 3 For example, the redundant latch sharing group 112 corresponds to two adjacent redundant latch areas 111. At this time, there are k redundant latch areas 111 and k / 2 redundant latch sharing groups 112 in total. The first group selection signal CRFT0<*> can include a first selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>The second selection signal CRFT1<*> can include the second selection signal CRF1T1 <e:0>and a second select signal CRF2T1 <d:0>. First selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>cooperating to select a current redundant latch area from among the k redundant latch areas 111. The first selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>There are (c+1)*(d+1)=k combinations to achieve the selection of the current redundant latch area from the k redundant latch areas 111. The second selection signal CRF1T1 <e:0>and a second selection signal CRF2T1 <d:0>In cooperation with the selection of the current redundant latch sharing group from the k / 2 redundant latch sharing groups 112, the current redundant latch sharing group in which the current redundant latch region is located is determined. The second selection signal CRF1T1 <e:0>and a second select signal CRF2T1 <d:0>There are (e+1)*(d+1)=k / 2 combinations to achieve the selection of the current redundant latch sharing group from the k / 2 redundant latch sharing groups 112 to determine the current redundant latch sharing group where the current redundant latch area is located.

[0048] In this embodiment, the bad block address information (address bits) inputted from the redundant latch array 110 to the selection circuit 120 includes: OUT1_(a-1:0) <k:1>to OUTy-2_(a-1 :0) <k: 1 > and OUTy-1_(a-1 :0) <k 2:1>to OUTy_(a-1:0) <k 2:1>. wherein the bad block address information OUT1_(a-1:0) <k:1>The address bits of the bad block addresses latched by the normal redundant latching units 1111 in the k redundant latching areas 111 corresponding to OUTy-2_(a-1:0) <k:1>. Among them, the first group of bad block address information OUT1_(a-1:0) <k:1>includes OUT1 0 <k:1>to OUT1_a-1 <k:1>OUT1_0 <k:1>OUT y-2_a-1 corresponds to the first address bit of the bad block address latched by each latch block Latch1_0 in the k redundant latch areas 111, and so on. <k:1>The a-th bit of the bad block address latched in each latch block Latchy-2_a-1 in the k redundant latching areas 111. For example, when the first selection signal CRF1T0<0> and the first selection signal CRF2T0<0> are active, i.e., the first of the k portions of the bad block address information is selected, the bad block address information OUT1_(a-1:0)<1> to OUTy-2_(a-1:0)<1> are selected in the selection circuit 120 and recombined into the first replacement address CRCAT(y-2:1) <a-1:0>The output is to the redundancy decoding circuit 130. The others are similarly processed. Among them, the first replacement address CRCAT(y-2:1) <a-1:0>Includes y-2 first replacement addresses: i.e., the first replacement address CRCAT1_ <a-1:0>to the first replacement address CRCATy-2 <a-1:0>.

[0049] Similarly, bad block address information OUTy-1_(a-1:0) <k 2:1>to OUTy_(a-1:0) <k 2:1>corresponding to the k / 2 redundant latching shared groups 112 latch the address bits of the bad block address of the shared redundant latching unit 1121. Bad block address information OUTy-1_(a-1:0) <k 2:1>includes OUTy-1_0 <k 2:1>to OUTy-1_a-1 <k 2:1>. OUTy-1_0 <k 2:1>corresponding to the first bit of the bad block address latched by each latch block Latchy-1_0 in the k / 2 redundant latched shared group 112, OUTy_a-1,..., OUTy_a-1 <k 2:1>The a-th bit of the bad block address latched in each latch block Latchy_a-1 of the k / 2 redundant latched shared groups 112. For example, when the second selection signal CRF1T1<0> and the second selection signal CRF2T1<0> are active, i.e., the first of the k / 2 portions of the bad block address information is selected, the bad block address information OUTy-1_(a-1:0)<1> to OUTy_(a-1:0)<1> are selected in the selection circuit 120 and recombined into the second replacement address CRCAT(y:y-1) <a-1:0>The output is to the redundancy decoding circuit 130. The others are similarly processed. Among them, the second replacement address CRCAT(y:y-1) <a-1:0>includes two second replacement addresses: second replacement address CRCATy-1 <a-1:0>to a second replacement address CRCATy <a-1:0>.

[0050] In particular, reference is made to Figure 2 and Figure 4 . Take the case of the redundant latch shared group 112 corresponding to the three adjacent redundant latch areas 111. At this time, there are k redundant latch areas 111 and k / 3 redundant latch shared groups 112 in total. The first group selection signal CRFT0<*> can include the first selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>The second selection signal CRFT1<*> can include the second selection signal CRF1T1 <e:0>and a second select signal CRF2T1 <d:0>. First selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>cooperating to select a current redundant latch area from among the k redundant latch areas 111. The first selection signal CRF1T0 <c:0>and the first selection signal CRF2T0 <d:0>There are (c+1)*(d+1)=k combinations to achieve the selection of the current redundant latch area from the k redundant latch areas 111. The second selection signal CRF1T1 <e:0>and a second select signal CRF2T1 <d:0>In cooperation with the selection of the current redundant latch sharing group from the k / 3 redundant latch sharing groups 112, the current redundant latch sharing group in which the current redundant latch region is located is determined. The second selection signal CRF1T1 <e:0>and a second select signal CRF2T1 <d:0>There are (e+1)*(d+1)=k / 3 combinations to achieve the selection of the current redundant latch sharing group from the k / 3 redundant latch sharing groups 112, which determines the current redundant latch sharing group where the current redundant latch area is located.

[0051] In this embodiment, the bad block address information (address bits) inputted from the redundant latch array 110 to the selection circuit 120 includes: OUT1_(a-1:0) <k:1>to OUTy-2_(a-1 :0) <k: 1 > and OUTy-1_(a-1 :0) <k 3:1>to OUTy_(a-1:0) <k 3:1>. wherein the bad block address information OUT1_(a-1:0) <k:1>The address bits of the bad block addresses latched by the normal redundant latching units 1111 in the k redundant latching areas 111 corresponding to OUTy-2_(a-1:0) <k:1>. Among them, the first group of bad block address information OUT1_(a-1:0) <k:1>includes OUT1 0 <k:1>to OUT1_a-1 <k:1>OUT1_0 <k:1>OUT y-2_a-1 corresponds to the first address bit of the bad block address latched by each latch block Latch1_0 in the k redundant latch areas 111, and so on. <k:1>The a-th bit of the bad block address latched in each latch block Latchy-2_a-1 in the k redundant latching areas 111. For example, when the first selection signal CRF1T0<0> and the first selection signal CRF2T0<0> are active, i.e., the first of the k portions of the bad block address information is selected, the bad block address information OUT1_(a-1:0)<1> to OUTy-2_(a-1:0)<1> are selected in the selection circuit 120 and recombined into the first replacement address CRCAT(y-2:1) <a-1:0>The output is to the redundancy decoding circuit 130. The others are similarly processed. Among them, the first replacement address CRCAT(y-2:1) <a-1:0>including y-2 first replacement addresses, i.e. first replacement address CRCAT1 <a-1:0>to the first replacement address CRCATy-2 <a-1:0>.

[0052] Similarly, bad block address information OUTy-1_(a-1:0) <k 3:1>to OUTy_(a-1:0) <k 3:1>corresponding to the k / 3 redundant latching shared groups 112 latch the address bits of the bad block address of the shared redundant latching unit 1121. Bad block address information OUTy-1_(a-1:0) <k 3:1>includes OUTy-1_0 <k 3:1>to OUTy-1_a-1 <k 3:1>. OUTy-1_0 <k 3:1>The first address bit of the bad block address latched by each latch block Latchy-1_0 in the k / 3 redundant latched shared group 112. The others are similar. When the second selection signal CRF1T1<0> and the second selection signal CRF2T1<0> are valid, the bad block address information OUTy-1_(a-1:0)<1> to OUTy_(a-1:0)<1> are selected in the selection circuit 120 and recombined into the second replacement address CRCAT(y:y-1) <a-1:0>The output is to the redundancy decoding circuit 130. The others are similarly processed. Among them, the second replacement address CRCAT(y:y-1) <a-1:0>includes two second replacement addresses: second replacement address CRCATy-1 <a-1:0>to a second replacement address CRCATy <a-1:0>.

[0053] Please continue to refer to Figure 2 . The redundancy decoding circuit 130 is coupled to the selection circuit 120. Wherein, in performing the addressing operation, the redundancy decoding circuit 130 will generate the first replacement address (for example, y-2 first replacement addresses CRCAT(y-2:1)_ <a-1:0>) and a second replacement address (e.g., 2 second replacement addresses CRCAT(y:y-1) <a-1:0>) respectively to the addressed address (e.g. CA <a-2:0>) comparison. In response to the addressing address matching either of the first replacement address and the second replacement address, the redundancy decoding circuit 130 enables the corresponding redundancy signal line to address the replacement resource in the memory.

[0054] In particular, reference is made to Figure 2 , Figure 3 and Figure 4 . The application of the redundancy decoding circuit 130 in the column replacement technique is exemplified. The redundancy signal lines include a redundancy column select signal line RYST. The normal signal lines include a normal column select signal line YST. The addressing address includes a column addressing address CA <a-2:0>. Take an example that each redundancy latch area 111 includes y-2 normal redundancy latch units 1111, and each redundancy latch shared group 112 includes 2 shared redundancy latch units 1121. The first replacement address includes CRCAT(y-2:1) <a-1:0>, specifically including a first replacement address CRCAT1 <a-1:0>to the first replacement address CRCATy-2 <a-1:0>. The second replacement address includes CRCAT(y:y-1) <a-1:0>, specifically including the second replacement address CRCATy-1 <a-1:0>to a second replacement address CRCATy <a-1:0>In performing the addressing operation, the redundant decoding circuit 130 generates the first replacement address CRCAT(y-2:1) from the first address CRCAT(y-2:1) and the second address CRCAT(y-2:1) as follows: <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>respectively, to the address CA <a-2:0>Compare. In response to the addressed address CA <a-2:0>With the first replacement address CRCAT(y-2:1)_ <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>For any match, the redundancy decoding circuit 130 enables the corresponding redundancy signal line RYST to address the redundant storage resource in the memory.

[0055] Please refer to Figure 2 and Figure 5 , Figure 5 is a structural schematic diagram of an embodiment of the redundancy decoding circuit provided in the present application. The redundancy decoding circuit 130 comprises a first redundancy decoding unit 131 and a second redundancy decoding unit 132. The first redundancy decoding unit 131 is coupled to the selection circuit 120 and receives the addressing address CA <a-2:0>In performing the addressing operation, the first redundancy decoding unit 131 generates the first replacement address CRCAT(y-2:1) from the first address A(y-2:1) and the first redundancy information R(y-2:1) as follows. <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>respectively, to the address CA <a-2:0>Compare, and based on the addressed address CA <a-2:0>With the first replacement address CRCAT(y-2:1)_ <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>For any match, the corresponding redundant enable signal CRFGB<*> is generated. Wherein, the redundant enable signal CRFGB<*> includes y redundant enable signals (corresponding to y redundant signal lines respectively), corresponding to the redundant enable signal CRFGB <y-2:1>a redundancy enable signal CRFGB corresponding to the second replacement address <y:y-1>The second redundancy decoding unit 132 is coupled to the first redundancy decoding unit 131 and receives the address CA <a-2:0>. Wherein, in performing the addressing operation, the second redundancy decoding unit 132 masks the addressing address CA in response to the first redundancy decoding unit 131 generating a corresponding redundancy enable signal CRFGB<*> <a-2:0>and enables the corresponding redundant signal line RYST based on a redundancy enable signal CRFGB<*> to address the corresponding redundant storage resource in the memory. In response to the first redundancy decoding unit 131 not generating the corresponding redundancy enable signal CRFGB<*>, the second redundancy decoding unit 132 enables the corresponding redundant signal line RYST based on the address CA <a-2:0>The corresponding normal signal line YST is enabled to normally address the corresponding normal storage resource in the memory. In this embodiment, the number of normal signal lines YST is x, including normal signal line YST<0> to normal signal line YST <x-1>The number of the redundant signal lines RYST is y, including the redundant signal line RYST<0> to the redundant signal line RYST <y-1>. In response to one of the y redundancy enable signals CRFGB<*> being set, the second redundancy decoding unit 132 enables one of the y redundant signal lines RYST corresponding thereto. And in response to none of the y redundancy enable signals CRFGB<*> being set, the second redundancy decoding unit 132 enables the redundant signal line RYST based on the addressing address CA <a-2:0>enables one of the corresponding x normal signal lines YST.

[0056] Specifically, in the first redundancy decoding unit 131, the address CA <a-2:0>with the replacement address CRCAT <a-1:0>bit comparison to obtain the first redundancy enabling information CRFB <a-2:0>. wherein the replacement address CRCAT <a-1:0>includes a first replacement address CRCAT(y-2:1) <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>. Replacement address CRC AT <a-1:0>Compare Address CA <a-2:0>More than one CRCAT <a-1>CRCAT <a-1>Used to indicate whether the addressed alternate resource is normal. ~CRCAT <a-1>is CRC AT <a-1>CRET = ~CRCAT <a-1>CRCAT<0>. First redundancy enable information CRFB <a-2:0>and the second redundancy enable information CRET to obtain a redundancy enable signal CRFGB<*>. When the first redundancy enable information CRFB <a-2:0>The redundancy enable signal CRFGB<*> is active when both the first redundancy enable information CRET and the second redundancy enable information CRET are active.

[0057] Optionally, the first redundancy decoding unit 131 also receives a first timing signal CRFLAT1T and a second timing signal CRFLAT1B to address the address CA during a limited period. <a-2:0>The sampling latch ensures that the first redundant decoding unit 131 performs the replacement address CRC AT <a-1:0>With the address CA <a-2:0>Not subject to addressing address CA when compared <a-2:0>Influence of Fluctuations. The second redundant decoding unit 132 also receives a clock signal CYCLKB to decode the addressing address CA under control of the clock signal CYCLKB <a-2:0>to enable the corresponding normal signal line YST.

[0058] Please refer to Figure 5 and Figure 6 , Figure 6 is a structural diagram of an embodiment of the first redundancy decoding unit provided in the present application. The first redundancy decoding unit 131 comprises a plurality of logic gate circuits 1311. Each of the logic gate circuits receives the first replacement address CRCAT(y-2:1) <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>one of the addresses CA <a-2:0>to the first replacement address CRCAT(y-2:1) <a-1:0>and the second replacement address CRCAT(y:y-1) <a-1:0>one of the columns is respectively addressed with the address CA <a-2:0>Comparison. Among them, the logic gate circuit 1311 includes a logic exclusive-OR gate circuit XOR.

[0059] The redundancy latch decoding circuit 100 provided by the present application is applied to a memory, and includes a redundancy latch circuit 140, which includes a plurality of redundancy latch regions 111 corresponding to a plurality of storage regions of the memory. Each redundancy latch region 111 includes at least one normal redundancy latch unit 1111, and at least part of the plurality of redundancy latch regions 111 are configured into at least one redundancy latch sharing group 112. Each redundancy latch sharing group 112 includes at least one shared redundancy latch unit 1121, and each redundancy latch sharing group 112 corresponds to at least two redundancy latch regions 111. The at least two redundancy latch regions 111 share the at least one shared redundancy latch unit 1121. In this way, the shared redundancy latch unit 1121 in the redundancy latch circuit 140 can be shared by at least two redundancy latch regions 111, and can be shared and utilized by at least two storage regions, thereby improving the utilization rate of replacement resources and saving replacement resources and circuit area.

[0060] Please refer to Figure 7 , Figure 7 is a structural schematic diagram of an embodiment of the memory provided by the present application. The memory 1000 is a semiconductor element-based storage device, and in this embodiment, is a dynamic random access memory (DRAM), but the present application is not limited thereto. The memory 1000 can be one of a dynamic random access memory (DRAM), a static random access memory (SRAM), or a pseudo static random access memory (PSRAM), etc. that needs to be repaired by redundancy. The memory 1000 can include but is not limited to a redundancy latch decoding circuit 100, a storage array 200, a sense amplifier circuit 300, and an input / output circuit 400.

[0061] The storage array 200 includes k storage regions 210 arranged in a column direction in sequence from top to bottom, and specifically includes storage region section<0> to storage region section <k>Each memory area corresponds to a row direction of the memory 1000, and more specifically, each memory area 210 includes 8 memory blocks 211 in the row direction, specifically including memory blocks mat<0> to mat<7>. When the memory 1000 performs a read data operation, each memory block 211 outputs 8-bit data, and each memory area 210 outputs 64-bit data.

[0062] The redundant latch decoding circuit 100 can decode a column address and drive a corresponding column selection signal line YST or a redundant column selection signal line RYST to access data in each memory block 211 in the memory area 210. The data in each memory block 211 can be amplified by the sense amplifier circuit 300 and output to the outside through the input / output circuit 400.

[0063] Please refer to Figure 8 , Figure 8 is a structural schematic diagram of an embodiment of the storage array provided in the present application. The storage array 200 includes a plurality of word lines WL, a plurality of pairs of complementary bit lines BL / BL#, and a plurality of memory cells MC. Each memory cell MC is coupled to a word line WL and a pair of complementary bit lines BL / BL#. The pair of complementary bit lines BL / BL# includes a target bit line BL and a complementary bit line BL#. The memory cell MC includes a storage capacitor CP and an access switch CT. The storage capacitor CP is coupled between the access switch CT and a common terminal. The access switch CT is coupled between the storage capacitor CP and the target bit line BL, and a control terminal of the access switch CT is coupled to the word line WL. The storage capacitor CP represents "1" and "0" in logic by more and less of the charge stored therein, or by higher and lower of the voltage difference across the storage capacitor. The on and off of the access switch CT determines whether to allow or prohibit reading and rewriting of the information stored in the storage capacitor CP. Specifically, the word line WL determines the on or off of the access switch CT, and the bit line BL is the only channel for the outside to access the storage capacitor CP. When the access switch CT is turned on, the outside can perform read or write operations on the storage capacitor CP through the bit line BL.

[0064] The memory array 200 further comprises a plurality of initialization modules 201, a plurality of sense amplification modules 202, and a plurality of column gating modules 203. Each of the initialization modules 201 is coupled to a pair of corresponding complementary bitline pairs BL / BL# for charging the corresponding complementary bitline pairs BL / BL# to an initialization potential Vref during a pre-charge phase. Each of the sense amplification modules 202 is coupled to a pair of corresponding complementary bitline pairs BL / BL# for performing a signal amplification operation on the corresponding complementary bitline pairs BL / BL#. Each of the column gating modules 203 is coupled to a pair of complementary bitline pairs BL / BL# and each of the column gating modules 203 is coupled to a column select signal line YST / a redundant column select signal line RYST for gating the complementary bitline pairs BL / BL# and the complementary intermediate input / output line pairs MIO / MIO# when the redundant latch decode circuit 100 drives the column select signal line YST / the redundant column select signal line RYST.

[0065] The input / output circuit 400 comprises a plurality of complementary intermediate input / output line pairs MIO / MIO# and a plurality of complementary input / output line pairs IO / IO#. The complementary intermediate input / output line pairs MIO / MIO# are coupled to the complementary bitline pairs BL / BL# through the column gating modules 203. The complementary intermediate input / output line pairs MIO / MIO# comprise a target intermediate input / output line MIO and a complementary intermediate input / output line MIO#. The target intermediate input / output line MIO is coupled to the target bitline BL through the column gating module 203 and the complementary intermediate input / output line MIO# is coupled to the complementary bitline BL# through the column gating module 203. It is noted that in other embodiments, the input / output circuit 400 further comprises a plurality of complementary local input / output line pairs LIO / LIO# (not shown), the plurality of complementary intermediate input / output line pairs MIO / MIO#, and the plurality of complementary input / output line pairs IO / IO#, wherein the complementary local input / output line pairs LIO / LIO# are coupled to the complementary bitline pairs BL / BL# through the column gating modules 203 and the complementary local input / output line pairs LIO / LIO# are further coupled to the complementary intermediate input / output line pairs MIO / MIO# through a switch circuit (not shown).

[0066] When the random access memory 1000 performs a read operation, the data in the memory cell MC to be accessed is first amplified by the sense amplification module 202 and then gated to the corresponding complementary bitline pairs BL / BL# and the complementary intermediate input / output line pairs MIO / MIO# through the column gating module 203. Subsequently, the data in the memory cell MC is further amplified by the sense amplification circuit 300 and then output to the corresponding complementary input / output line pairs IO / IO#. The sense amplification circuit 300 comprises a plurality of secondary sense amplification modules for further amplifying the data on the complementary intermediate input / output line pairs MIO / MIO# and then outputting the data to the corresponding complementary input / output line pairs IO / IO#.

[0067] In other embodiments, the input / output circuit 400 can further include a write driving module for writing external data into the memory cell MC.

[0068] Further, each column gating module 203 is coupled with a pair of complementary bit lines BL / BL# and each column gating module 203 is coupled with a column selection signal line YST / redundant column selection signal line RYST to enable the complementary bit line pair BL / BL# and the complementary intermediate input / output line pair MIO / MIO# when the redundant latch decoding circuit 100 drives the column selection signal line YST / redundant column selection signal line RYST.

[0069] In the present embodiment, one column selection signal line YST / redundant column selection signal line RYST is coupled with 8 column gating modules 203 in one memory block mat.

[0070] In the present embodiment, when the memory cell MC corresponding to a column selection signal line YST is defective and cannot be normally read and written, the memory cell MC corresponding to the redundant column selection signal line RYST can be used as a substitute to improve the yield of the memory. The address of the abnormal column selection signal line (bad block address) can be locked in the redundant latch circuit 140 in the redundant latch decoding circuit 100. In addition to the aforementioned redundant column selection signal line RYST, the column redundancy resource of the present application can also be a redundant bit line RBL (not shown in the figure) or a redundant input / output line RIO (not shown in the figure), and the present application does not limit this.

[0071] Please refer to Figure 9 , Figure 9 is a structural schematic diagram of another embodiment of the memory provided by the present application. The random memory 1000 can be a random memory DRAM, a static random memory SRAM or a pseudo static random memory (Pseudo SRAM, PSRAM). The random memory 1000 includes a redundant latch decoding circuit 100.

[0072] The above description is merely an embodiment of the present application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process transformation according to the content of the specification and the drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.< / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A redundant latch decoding circuit, applied to a memory, characterized in that, include: A redundant latch circuit includes multiple redundant latch regions corresponding to multiple storage regions of the memory. Each redundant latch region includes at least one normal redundant latch unit, and at least a portion of the multiple redundant latch regions are configured into at least one redundant latch sharing group. Each redundant latch sharing group includes at least one shared redundant latch unit, and each redundant latch sharing group corresponds to at least two redundant latch regions. The at least two redundant latch regions share the at least one shared redundant latch unit. A redundant decoding circuit, coupled to the redundant latch circuit, receives a replacement address, wherein, in response to an addressing address matching the replacement address, the redundant decoding circuit enables a corresponding redundant signal line to address redundant storage resources in the memory. Each redundant latch sharing group corresponds to two adjacent redundant latch areas. Each redundant latch area includes n normal redundant latch units. Any redundant latch sharing group includes m shared redundant latch units, and the m shared redundant latch units are located in one of the two redundant latch areas. The other of the two redundant latch areas shares the m shared redundant latch units. The redundant latch area corresponding to any storage area is configured to include (n+m) redundant latch units; or Each of the redundant latch sharing groups corresponds to three adjacent redundant latch areas. Each redundant latch area includes n normal redundant latch units. Any redundant latch sharing group includes m shared redundant latch units, and the m shared redundant latch units are located in one of the three redundant latch areas. The other three redundant latch areas can share the m shared redundant latch units. The redundant latch area corresponding to any of the storage areas is configured to include (n+m) redundant latch units.

2. The redundant latch decoding circuit according to claim 1, characterized in that, The at least one shared redundant latch unit is disposed in one of the at least two redundant latch regions, and the other at least two redundant latch regions corresponding to the redundant latch sharing group share the at least one shared redundant latch unit; or The at least one shared redundant latch unit is distributed among the at least two redundant latch areas, and the at least two redundant latch areas corresponding to the redundant latch sharing group share the at least one shared redundant latch unit.

3. The redundant latch decoding circuit according to claim 1, characterized in that, The redundant latch circuit includes: A redundant latch array, consisting of the plurality of redundant latch areas, receives bad block addresses, storage area indication information and reset signals to latch the bad block addresses bit by bit to the corresponding redundant latch areas. A selection circuit, coupled to the redundant latch array, receives address bits output by the redundant latch array. The selection circuit also receives a first set of selection signals and a second set of selection signals. The selection circuit determines the current redundant latch area corresponding to the current operating memory area based on the first set of selection signals, and determines the current redundant latch sharing group corresponding to the current redundant latch area based on the second set of selection signals. The selection circuit selectively outputs a first replacement address composed of address bits latched by the normal redundant latch units in the current redundant latch area and a second replacement address composed of address bits latched by the shared redundant latch units corresponding to the current redundant latch sharing group.

4. The redundant latch decoding circuit according to claim 3, characterized in that, The first set of selection signals includes a plurality of first selection signals, which cooperate to select and determine the current redundant latch region from the plurality of redundant latch regions; The second set of selection signals includes a plurality of second selection signals, which cooperate to select from the at least one redundant latch sharing group to determine the current redundant latch area corresponding to the current redundant latch sharing group.

5. The redundant latch decoding circuit according to claim 3, characterized in that, The redundant decoding circuit is coupled to the selection circuit, wherein, during an addressing operation, the redundant decoding circuit compares the first replacement address and the second replacement address with the addressing address, respectively; in response to a match between the addressing address and either the first replacement address or the second replacement address, the redundant decoding circuit enables the corresponding redundant signal line to address the redundant storage resource in the memory.

6. The redundant latch decoding circuit according to claim 5, characterized in that, The redundant decoding circuit includes: A first redundant decoding unit is coupled to the selection circuit and receives the addressing address; wherein, when the addressing operation is performed, the first redundant decoding unit compares the first replacement address and the second replacement address with the addressing address respectively, and generates a corresponding redundancy enable signal based on the match between the addressing address and either the first replacement address or the second replacement address; A second redundant decoding unit is coupled to the first redundant decoding unit and receives the addressing address. During the addressing operation, in response to the first redundant decoding unit generating a corresponding redundancy enable signal, the second redundant decoding unit masks the addressing address and enables the corresponding redundant signal line based on the redundancy enable signal to address the corresponding redundant storage resource in the memory. In response to the first redundant decoding unit not generating the corresponding redundancy enable signal, the second redundant decoding unit enables the corresponding normal signal line based on the addressing address to normally address the corresponding normal storage resource in the memory.

7. The redundant latch decoding circuit according to claim 6, characterized in that, The redundant latch circuit includes a column redundant latch circuit, the redundant decoding circuit includes a column redundant decoding circuit, the redundant signal lines include redundant column strobe signal lines, the normal signal lines include normal column strobe signal lines, and the memory includes k memory areas arranged in the column direction, each memory area corresponding to the row direction of the memory.

8. The redundant latch decoding circuit according to claim 6, characterized in that, The number of normal signal lines is x, and the number of redundant signal lines is y, where: In response to one of the y redundancy enable signals being set, the second redundancy decoding unit enables one of the corresponding y redundant signal lines; and in response to none of the y redundancy enable signals being set, the second redundancy decoding unit enables one of the corresponding x normal signal lines based on the address address.

9. The redundant latch decoding circuit according to claim 6, characterized in that, The first redundant decoding unit includes a plurality of logic gates, each of which receives one of the first replacement address and the second replacement address, and the addressing address, to compare the first replacement address and the second replacement address with the addressing address respectively; wherein, the logic gates include logic XOR gates.

10. A memory, characterized in that, Includes the redundant latch decoding circuit as described in any one of claims 1-9.

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