Chip state control method, state control logic circuit and memory

Abstract

The embodiments of the present disclosure relate to the field of integrated circuits and disclose a chip state control method, a state control logic circuit, and a memory. The chip state control method includes: generating a current state code based on a current state excitation signal and a previous state identification signal; generating a current state identification signal for characterizing the current state of the chip based on the current state code; changing the current state code to a current state transition code in response to the current state identification signal; generating a next state code based on a next state excitation signal and the current state transition code; wherein at least two bits of data are different between the current state code and the next state code, and only one bit of data is different between the current state transition code and the next state code; generating a next state identification signal for characterizing the next state of the chip from the next state code. The embodiments of the present disclosure can avoid unexpected states inside the chip and ensure the reliability and accuracy of the state inside the chip.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a chip state control method, a state control logic circuit, and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0003] Dynamic random access memory (DRAM) chips have multiple operating states, each of which corresponds to a status code. However, in related technologies, there is a risk of errors in the status code during the chip's transition between different states. This can lead to unexpected states within the chip, compromising the reliability and accuracy of the chip's internal state. Summary of the Invention

[0004] In view of this, the embodiments of the present disclosure provide a chip state control method, a state control logic circuit, and a memory, which can avoid unexpected states inside the chip and ensure the reliability and accuracy of the state inside the chip.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] An embodiment of the present disclosure provides a chip state control method, the method comprising: generating a current state code based on a current state excitation signal and a previous state identification signal; generating a current state identification signal for characterizing the current state of the chip based on the current state code; changing the current state code to a current state transition code in response to the current state identification signal; generating a next state code based on a next state excitation signal and the current state transition code; wherein at least two bits of data differ between the current state code and the next state code, only one bit of data differs between the current state transition code and the next state code, and only one bit of data differs between the current state code and the current state transition code; generating a next state identification signal for characterizing the next state of the chip from the next state code.

[0007] In the above scheme, the next state code is generated based on the next state excitation signal and the current state transition code, including: generating a transition state identification signal according to the current state transition code; generating the next state code according to the transition state identification signal and the next state excitation signal.

[0008] In the above solution, the state code is composed of 3 bits of data; the current state code is 001; the current state transition code is 011; and the next state code is 010.

[0009] An embodiment of the present disclosure also provides a state control logic circuit, which includes: a state code generation circuit and a state identification signal generation circuit; the state code generation circuit is connected to the state code generation circuit and is configured to generate a current state code based on a current state excitation signal and a previous state identification signal; the state identification signal generation circuit is configured to generate a current state identification signal for characterizing the current state of the chip based on the current state code; the state code generation circuit is also configured to change the current state code to a current state transition code in response to the current state identification signal; and generate a next state code based on a next state excitation signal and the current state transition code; wherein, there are at least two bits of data different between the current state code and the next state code, and only one bit of data different between the current state transition code and the next state code; the state identification signal generation circuit is also configured to generate a next state identification signal for characterizing the next state of the chip from the next state code.

[0010] In the above scheme, the state identification signal generating circuit is further configured to generate a transition state identification signal based on the current state transition code; the state code generating circuit is further configured to generate the next state code based on the transition state identification signal and the next state excitation signal.

[0011] In the above scheme, the status code generation circuit includes: 3 trigger units; each trigger unit corresponds to one bit of data of the output status code; wherein, the first trigger unit outputs the first bit of data and the first bit of inverted data; the second trigger unit outputs the second bit of data and the second bit of inverted data; the third trigger unit outputs the third bit of data and the third bit of inverted data.

[0012] In the above scheme, the state code generation circuit also includes: 6 control code generation units and 1 transition control code generation unit; each of the control code generation units receives a corresponding state excitation signal and a state identification signal, and outputs a corresponding control code; the transition control code generation unit receives the current state identification signal and outputs a transition control code; the output ends of the 6 control code generation units and the output end of the 1 transition control code generation unit are correspondingly connected to the input ends of the 3 trigger units.

[0013] In the above scheme, the first trigger unit includes: a first RS trigger, a first delay and a second delay; the input end of the first delay receives the fourth control code, and the output end of the first delay is connected to the set end of the first RS trigger; the input end of the second delay receives the sixth control code, and the output end of the second delay is connected to the reset end of the first RS trigger; the in-phase output end of the first RS trigger outputs the first bit data of the status code, and the inverting output end of the first RS trigger outputs the first bit inverted data of the status code.

[0014] In the above scheme, the second trigger unit includes: a second RS trigger, an OR gate and a third delay; the input end of the third delay receives the transition control code, and the output end of the third delay is connected to the set end of the second RS trigger; the input end of the OR gate receives the third and fifth control codes respectively, and the output end of the OR gate is connected to the reset end of the second RS trigger; the in-phase output end of the second RS trigger outputs the second bit data of the status code, and the inverting output end of the second RS trigger outputs the second bit inverted data of the status code.

[0015] In the above scheme, the third trigger unit includes: a third RS trigger, a fourth delay and a fifth delay; the input end of the fourth delay receives the first control code, and the output end of the fourth delay is connected to the set end of the third RS trigger; the input end of the fifth delay receives the second control code, and the output end of the fifth delay is connected to the reset end of the third RS trigger; the in-phase output end of the third RS trigger outputs the third bit data of the status code, and the inverting output end of the third RS trigger outputs the third bit inverted data of the status code.

[0016] In the above scheme, each of the control code generating units includes: a first NAND gate and a first inverter; the input end of the first NAND gate receives the corresponding state excitation signal and the state identification signal, and the output end of the first NAND gate is connected to the input end of the first inverter; the output end of the first inverter outputs the corresponding control code.

[0017] In the above solution, the transition control code generating unit includes: a second inverter and a third inverter; the input end of the second inverter receives the current state identification signal, the output end of the second inverter is connected to the input end of the third inverter; the output end of the third inverter outputs the transition control code.

[0018] In the above scheme, the status identification signal generating circuit includes: multiple status identification signal generating units; each of the status identification signal generating units includes: a second NAND gate and a fourth inverter; the first input end of the second NAND gate receives the first bit data or the first bit inverted data of the status code; the second input end of the second NAND gate receives the second bit data or the second bit inverted data of the status code; the third input end of the second NAND gate receives the third bit data or the third bit inverted data of the status code; the output end of the second NAND gate is connected to the input end of the fourth inverter; and the output end of the fourth inverter outputs the corresponding status identification signal.

[0019] In the above scheme, multiple state identification signal generating units include: a first state identification signal generating unit, a transition state identification signal generating unit and a second state identification signal generating unit; the current state code is 001; the current state transition code is 011; the next state code is 010; the first state identification signal generating unit receives the first inverted data, the second inverted data and the third data of the state code, and outputs the current state identification signal; the transition state identification signal generating unit receives the first inverted data, the second data and the third data of the state code, and outputs the transition state identification signal; the second state identification signal generating unit receives the first inverted data, the second data and the third inverted data of the state code, and outputs the next state identification signal.

[0020] An embodiment of the present disclosure further provides a memory, which includes the state control logic circuit as described in the above solution.

[0021] It can be seen that the embodiment of the present disclosure provides a chip state control method, a state control logic circuit and a memory. The chip state control method includes: generating a current state code based on a current state excitation signal and a previous state identification signal; generating a current state identification signal for representing the current state of the chip based on the current state code; changing the current state code to a current state transition code in response to the current state identification signal; generating a next state code based on a next state excitation signal and the current state transition code; wherein there are at least two bits of data different between the current state code and the next state code, and only one bit of data different between the current state transition code and the next state code; generating a next state identification signal for representing the next state of the chip from the next state code. In this way, by introducing the current state transition code, only one bit of data needs to be changed in the process of generating the next state code from the current state transition code; avoiding the occurrence of an erroneous state code due to competition between the changed bits of data when changing multiple bits of data. Thus, unexpected states are avoided within the chip, ensuring the reliability and accuracy of the state within the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the process of the chip state control method provided in the embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 Schematic diagram of the process of the chip state control method provided in the embodiment of the present disclosure Figure 2 ;

[0024] Figure 3 A schematic diagram of the structure of a state control logic circuit provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of the structure of a status code generation circuit provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of the structure of a status identification signal generating circuit provided in an embodiment of the present disclosure;

[0027] Figure 6 Schematic diagram of the state transition of the memory in an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0030] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] If similar descriptions of "first / second" appear in the invention document, the following explanation is added. In the following description, the terms "first\second\third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] Figure 1 This is an optional flow chart of the chip state control method provided by the embodiment of the present disclosure, which will be combined with Figure 1 The steps shown are explained.

[0034] S101: Generate a current state code based on a current state excitation signal and a previous state identification signal.

[0035] In an embodiment of the present disclosure, a state control logic circuit can be set within the chip to control the state of the chip. After receiving the current state excitation signal, the state control logic circuit can generate a current state code based on the current state excitation signal and the previous state identification signal. The current state excitation signal is sent by the control circuit to the state control logic circuit; the current state excitation signal is used to control the state control logic circuit to generate the corresponding current state code, thereby changing the state of the chip. The previous state identification signal is generated by the state control logic circuit, and the previous state identification signal is used to represent the previous state of the chip.

[0036] It should be noted that the chip can have a variety of different states depending on its operating requirements. Taking memory as an example, according to the JEDEC standard for LPDDR5 (Low Power Double Data Rate SDRAM, the fifth generation of low-power memory), the memory can have PDX (power down exit) state, DSM (deep sleep mode) state and PD (power down entry) state. At the same time, the JEDEC standard for LPDDR5 further specifies the switching order between states, as well as the state excitation signal that triggers the state switching condition. For example, a memory in the DSM state enters the PD state after the CS (chip select signal) undergoes a high-low level toggle. A memory in the PD state can only enter the PDX state after the CS signal undergoes a high-low level toggle. Considering that a high-low level reversal of the CS signal means that the level of the CS signal rises from a low level to a high level, and then drops from a high level to a low level, the change of the CS signal level will also cause the memory to be in different states. In the specific implementation process, a PDpre (power-off ready) state is set as a memory state between the DSM state and the PD state. When the state stimulus signal with a high CS signal level appears, the memory enters the PDpre state from the DSM state. When the state stimulus signal with a low CS signal level appears, the memory enters the PD state from the PDpre state. Similarly, a PDXpre (power-off ready) state is set as a memory state between the PD state and the PDX state.

[0037] It should also be noted that the state excitation signal is used to control the chip to switch between different states. In a specific implementation, this can be reflected as the state excitation signal controlling the state control logic circuit to generate a corresponding state code. However, the state control logic circuit does not generate the state code based solely on the state excitation signal. Instead, it generates the state code by combining the state excitation signal with the existing state identification signal. In other words, the current state code is generated based on the current state excitation signal and the previous state identification signal.

[0038] In the disclosed embodiments, the state code may include multiple bits of data, for example, 3 bits of data. Each bit of data is represented by a binary digit, meaning that each bit of data includes two values, "1" and "0." In the state control logic circuit, the value of each bit of data is represented by a level, with a high level representing "1" and a low level representing "0." Of course, the state code may include more than 3 bits of data, which may be determined by the number of states the memory switches between.

[0039] S102: Generate a current state identification signal for representing the current state of the chip based on the current state code.

[0040] In the embodiment of the present disclosure, after generating the current state code, the state control logic circuit may generate a current state identification signal based on the current state code. The current state identification signal is used to represent the current state of the chip.

[0041] It should be noted that different state identification signals can serve as enable signals for different states in the chip. In other words, the chip can enable different states based on the state identification signals. Different state identification signals are generated by the state control logic circuit according to different state codes. In other words, different values ​​of the state code correspond to different states of the chip.

[0042] It should also be noted that the JEDEC standard for LPDDR5 only specifies the switching order and switching conditions between each state, but does not specify the value of the state code corresponding to each state. In actual production, the value of the state code corresponding to each state can be determined according to the needs of circuit design. For example, in the memory, "001" can correspond to the PDXpre state, "010" to the PDX state, "000" to the PD state, "100" to the PDpre state, and "110" to the DSX state.

[0043] S103: In response to the current state identification signal, change the current state code to a current state transition code.

[0044] In the disclosed embodiment, after the state control logic circuit generates a current state identification signal, it can change the current state code to a current state transition code in response to the current state identification signal. The current state transition code can be a redundant state code, that is, the current state transition code does not correspond to any state in the chip. Accordingly, after the current state code is changed to the current state transition code, the state of the chip may not change, and the current state corresponding to the current state code may remain unchanged.

[0045] S104. Generate a next state code based on the next state excitation signal and the current state transition code; wherein, there are at least two data differences between the current state code and the next state code; there is only one data difference between the current state transition code and the next state code, and there is only one data difference between the current state code and the current state transition code.

[0046] It should be noted that when the state control logic circuit converts the state code, it is difficult to ensure that each bit of data changes at the same time, that is, there is competition in the changes of each bit of data. For example, to convert the state code 001 to the state code 010, it is necessary to change the least significant bit (LSB) data and the second lowest bit data. If the least significant bit data changes first, then the state code conversion order is 001->000->010; that is, during the conversion process, an error (glitch) such as state code 000 occurs. Because each state code corresponds to a state identification signal, which in turn enables other circuits within the chip, a glitch that occurs during the state code conversion process can cause the circuits within the chip to enter unexpected states, such as erroneously entering the PD state, thereby affecting the normal operation of the chip.

[0047] In the embodiment of the present disclosure, after receiving the next state excitation signal, the state control logic circuit can generate the next state code based on the next state excitation signal and the current state transition code. Since there is only one bit of data difference between the current state transition code and the next state code, and there is also only one bit of data difference from the current state code; therefore, in the embodiment of the present disclosure, the state control logic circuit only needs to change one bit of data when converting from the current state code to the current state transition code, and only needs to change one bit of data when converting from the current state transition code to the next state code. No glitch will occur during the conversion process, ensuring the reliability and accuracy of the state in the chip. In contrast, since there are at least two bits of data difference between the current state code and the next state code.

[0048] S105 : Generate a next state identification signal for representing the next state of the chip from the next state code.

[0049] In the disclosed embodiments, after the state control logic circuit generates a next-state code, it can generate a next-state identification signal based on the next-state code. The next-state identification signal is used to indicate the next state of the chip. In other words, the next-state identification signal can enable other circuits within the chip to adjust the chip to the next state.

[0050] It can be understood that the disclosed embodiments introduce a current-state transition code, so that switching from the current state code to the current-state transition code only requires changing one bit of data, and switching from the current state transition code to the next state code also requires changing only one bit of data. This avoids the occurrence of erroneous state codes due to contention between the bits of data being changed when changing multiple bits of data. This prevents unexpected states from occurring within the chip and ensures the reliability and accuracy of the chip's internal state.

[0051] In some embodiments of the present disclosure, Figure 2 S1041 to S1042 shown are implemented Figure 1S104 shown will be described in conjunction with each step.

[0052] S1041. Generate a transition state identification signal according to the current state transition code.

[0053] In the disclosed embodiment, after the state control logic circuit generates the current state transition code, it can generate a transition state identification signal based on the current state transition code. The transition state identification signal does not enable other circuits in the chip, that is, the transition state identification signal does not affect the state of the chip.

[0054] In the disclosed embodiment, redundant state codes can be selected as current state transition codes, in compliance with the state transition sequence and transition conditions specified in the JEDEC standard. The redundant state codes do not correspond to any chip state. Thus, the current state transition code does not correspond to any chip state, and the transition state identification signal does not affect the chip state.

[0055] S1042: Generate a next state code according to the transition state identification signal and the next state excitation signal.

[0056] In the embodiment of the present disclosure, after generating the transition state identification signal, the state control logic circuit may generate a next state code according to the transition state identification signal and the next state excitation signal.

[0057] It is understood that the present embodiment converts the current state transition code to the next state code, and the current state transition code does not correspond to any state of the chip. This prevents unexpected states from occurring within the chip during the generation of the next state code, ensuring the reliability and accuracy of the chip's internal state.

[0058] In some embodiments of the present disclosure, the status code is composed of 3-bit data, the current status code is 001; the current state transition code is 011; and the next state code is 010, wherein the status code "001" corresponds to the PDXpre state, the status code "010" corresponds to the PDX state, and the status code "011" does not correspond to any state. Therefore, in the process of the memory converting from the PDXpre state to the PDX state, the state control logic circuit will first convert from the current state code "001" to the current state transition code "011", and then convert from the current state transition code "011" to the next state code "010". In this way, in the process of the memory converting from the PDXpre state to the PDX state, the memory can be prevented from erroneously entering the PD state corresponding to the status code "000", that is, it can avoid the occurrence of unexpected states inside the memory, thereby ensuring the reliability and accuracy of the state in the memory.

[0059] It should be noted that the content described in the above embodiment, that is, the current state code is 001, corresponding to the PDXpre state; the current state transition code is 011; and the next state code is 010, corresponding to the PDX state, is only a feasible embodiment provided by the present disclosure. In other embodiments, the current state code is 001 and the next state code is 100; at the same time, the state code "000" corresponds to a certain state, while the state code "101" does not correspond to any state (i.e., it is a redundant state code); then, the state transition code can be set to 101, so that the state control logic circuit first converts from the current state code "001" to the current state transition code "101", and then converts from the current state transition code "101" to the next state code "100". In other words, if there are at least two bits of data different between the current state code and the next state code, and there is a suitable redundant state code, then the technical solution provided by the embodiment of the present disclosure can be adopted to prevent the chip from entering an incorrect state.

[0060] The embodiment of the present disclosure also provides a state control logic circuit, such as Figure 3 As shown, the state control logic circuit 80 includes: a state code generation circuit 10 and a state identification signal generation circuit 20.

[0061] State code generation circuit 10, connected to state code generation circuit 20, is configured to generate current state code Code1 based on current state stimulus signal CMD1 and previous state identification signal SI0. State identification signal generation circuit 20 is configured to generate current state identification signal SI1 for representing the current state of the chip based on current state code Code1.

[0062] The state code generation circuit 10 is further configured to, in response to the current state identification signal SI1, change the current state code Code1 to the current state transition code Code1P; and to generate the next state code Code2 based on the next state stimulus signal CMD2 and the current state transition code Code1P. The current state code Code1 and the next state code Code2 differ by at least two bits, while the current state transition code Code1P and the next state code Code2 differ by only one bit. The state identification signal generation circuit 20 is further configured to generate a next state identification signal SI2 from the next state code Code2, which is used to represent the next state of the chip.

[0063] In the embodiments of the present disclosure, reference Figure 3The state control logic circuit 80 controls the chip's state. Upon receiving the current state stimulus signal CMD1, the state control logic circuit 80 generates the current state code Code1 based on the current state stimulus signal CMD1 and the previous state identification signal SI0. The current state stimulus signal CMD1 is sent to the state control logic circuit 80 by the control circuit; the previous state identification signal SI0 is generated by the state identification signal generation circuit 20 and is used to represent the previous state of the chip.

[0064] It should be noted that chips can have multiple different states depending on their operating requirements. Taking memory as an example, according to the JEDEC standard for LPDDR5 (Low Power Double Data Rate SDRAM, the fifth generation of low-power memory), memory can have PDX (power down exit) state, DSM (deep sleep mode) state, and PD (power down entry) state.

[0065] Furthermore, refer to Figure 3 The state excitation signal (including CMD1 and CMD2) is used to control the chip to switch between different states, which is reflected in that the state code generation circuit 10 combines the state excitation signal and the existing state identification signal to generate the state code. For example, the state code generation circuit 10 generates the current state code Code1 based on the current state excitation signal CMD1 and the previous state identification signal SI0.

[0066] In the embodiments of the present disclosure, reference Figure 3 The status code (including Code1 / Code1P / Code2) can include multiple bits of data, for example, 3 bits. Each bit of data is represented by a binary digit, meaning it can have two values: "1" and "0." In the status control logic circuit, the value of each bit of data is represented by a level: a high level represents "1" and a low level represents "0."

[0067] In the embodiments of the present disclosure, reference Figure 3 The state identification signal generating circuit 20 can generate a current state identification signal SI1 based on the current state code Code1. The current state identification signal SI1 is used to represent the current state of the chip.

[0068] It should be noted that different state identification signals can correspond to enable signals for different states in the chip. In other words, the chip can enable different states based on the state identification signal. Different state identification signals are generated by the state control logic circuit according to different state codes. In other words, different values ​​of the state code correspond to different states of the chip. For example, in the memory, "001" can be set to correspond to the PDXpre state, "010" to correspond to the PDX state, and "000" to correspond to the PD state.

[0069] In the embodiments of the present disclosure, reference Figure 3 In response to the current state identification signal SI1, the state code generation circuit 10 can change the current state code Code1 to the current state transition code Code1P. The current state transition code Code1P is a redundant state code; that is, it does not correspond to any state in the chip. Accordingly, after the current state code Code1 is changed to the current state transition code Code1P, the chip state may remain unchanged, maintaining the current state corresponding to the current state code Code1.

[0070] In the embodiments of the present disclosure, reference Figure 3 After receiving the next state excitation signal CMD2, the state code generation circuit 10 can generate the next state code Code2 based on the next state excitation signal CMD2 and the current state transition code Code1P.

[0071] It should be noted that when the state code generation circuit 10 converts the state code, it is difficult to ensure that each bit of data changes simultaneously, that is, there is competition in the changes of each bit of data. For example, to convert the state code 001 to the state code 010, the lowest bit data and the second lowest bit data need to be changed. If the lowest bit data changes first, then the state code conversion order is 001->000->010; that is, during the conversion process, an error (glitch) such as state code 000 occurs. Because each state code corresponds to a state identification signal, which in turn enables other circuits within the chip, a glitch that occurs during the state code conversion process can cause the circuits within the chip to enter unexpected states, thereby affecting the normal operation of the chip.

[0072] In the embodiments of the present disclosure, reference Figure 3Since only one bit of data differs between the current state transition code Code 1P and the next state code Code 2, the state code generation circuit 10 only needs to change one bit of data to convert from the current state transition code Code 1P to the next state code Code 2. This prevents glitches and ensures the reliability and accuracy of the chip's internal state. In contrast, since at least two bits of data differ between the current state code Code 1 and the next state code Code 2, if the state code generation circuit 10 directly converts from the current state code Code 1 to the next state code Code 2, it needs to change at least two bits of data, potentially causing glitches.

[0073] In the embodiments of the present disclosure, reference Figure 3 The state identification signal generating circuit 20 can generate a next state identification signal SI2 based on the next state code Code2. The next state identification signal SI2 is used to represent the next state of the chip. In other words, the next state identification signal SI2 can enable other circuits within the chip to adjust the chip to the next state.

[0074] It is understood that the state control logic circuit provided by the disclosed embodiments, by introducing the current state transition code, only needs to change one bit of data when generating the next state code from the current state transition code. This avoids the occurrence of erroneous state codes due to contention between the bits of data being changed when changing multiple bits of data. This prevents unexpected states from occurring within the chip and ensures the reliability and accuracy of the chip's internal state.

[0075] In some embodiments of the present disclosure, reference Figure 3 The state identification signal generating circuit 20 is further configured to generate a transition state identification signal SI1P according to the current state transition code Cod1P. The state code generating circuit 10 is further configured to generate a next state code Code2 according to the transition state identification signal SI1P and the next state excitation signal CMD2.

[0076] In the embodiments of the present disclosure, reference Figure 3 The state identification signal generating circuit 20 can generate a transition state identification signal SI1P according to the current state transition code Code1P. The transition state identification signal SI1P does not enable other circuits in the chip, that is, the transition state identification signal SI1P does not affect the state of the chip.

[0077] In the disclosed embodiment, a redundant state code can be selected according to the JEDEC standard as the current state transition code Code 1P. The redundant state code does not correspond to any chip state. Thus, the current state transition code Code 1P does not correspond to any chip state, and the transition state identification signal SI1P does not affect the chip state.

[0078] It is understood that in the disclosed embodiments, the current state transition code does not correspond to any chip state, and thus, the transition state identification signal does not affect the chip state. This prevents unexpected states from occurring within the chip during the generation of the next state code, ensuring the reliability and accuracy of the chip's internal state.

[0079] In some embodiments of the present disclosure, reference Figure 4 The state code generation circuit 10 includes three trigger units 101, 102, and 103. Each trigger unit outputs a corresponding bit of state code data. The first trigger unit 101 outputs the first bit of data Q0 and the first bit of inverted data Q0N; the second trigger unit 102 outputs the second bit of data Q1 and the second bit of inverted data Q1N; and the third trigger unit 103 outputs the third bit of data Q2 and the third bit of inverted data Q2N.

[0080] In some embodiments of the present disclosure, continue to refer to Figure 4 The state code generation circuit 10 further includes six control code generation units 104-109 and one transition control code generation unit 110. Each of the control code generation units 104-109 receives a corresponding state excitation signal and a state identification signal and outputs a corresponding control code (i.e., one of C0-C5). The transition control code generation unit 110 receives the current state identification signal and outputs a transition control code C01. The outputs of the six control code generation units 104-109 and the output of the transition control code generation unit 110 are connected to the inputs of the three trigger units 101-103.

[0081] It should be noted that Figure 4 The structure of the state code generating circuit 10 is shown by taking the state of the memory DRAM as an example. Figure 4 In the DRAM, the state excitation signals include CSHi, CSLo, PDEcmd, and DSMcmd, which trigger and activate different states in the DRAM respectively. The state identification signals include PD, PDXPre, PDX, DSM, and PDPre, which correspond to different states in the DRAM respectively.

[0082] For example, PD corresponds to the power down entry state; PDXpre corresponds to the second intermediate state converted from the PD state after receiving the CS signal (chip select signal) as a high level; PDX corresponds to the power down exit state; DSM corresponds to the deep sleep mode state; PDPre corresponds to the first intermediate state converted from the DSM state after receiving the CS signal as a high level.

[0083] In some embodiments of the present disclosure, reference Figure 4 The first trigger unit 101 includes a first RS flip-flop 1011, a first delay device Del1, and a second delay device Del2. The input of the first delay device Del1 receives the fourth control code C3, and the output of the first delay device Del1 is connected to the set terminal S of the first RS flip-flop 1011. The input of the second delay device Del2 receives the sixth control code C5, and the output of the second delay device Del2 is connected to the reset terminal R of the first RS flip-flop 1011. The non-inverting output terminal Q of the first RS flip-flop 1011 outputs the first bit of data Q0 of the status code, and the inverting output terminal Q of the first RS flip-flop 1011 outputs the first inverted bit of data Q0N of the status code.

[0084] In some embodiments of the present disclosure, continue to refer to Figure 4 The second trigger unit 102 includes a second RS flip-flop 1012, an OR gate Or1, and a third delay device Del3. The input of the third delay device Del3 receives the transition control code C01, and the output of the third delay device Del3 is connected to the set terminal S of the second RS flip-flop 1012. The input of the OR gate Or1 receives the third control code C2 and the fifth control code C4, respectively, and the output of the OR gate Or1 is connected to the reset terminal R of the second RS flip-flop 1012. The non-inverting output Q of the second RS flip-flop 1012 outputs the second bit Q1 of the status code, and the inverting output Q of the second RS flip-flop 1012 outputs the second inverted bit Q1N of the status code.

[0085] In some embodiments of the present disclosure, continue to refer to Figure 4 The third trigger unit 103 includes a third RS flip-flop 1013, a fourth delay device Del4, and a fifth delay device Del5. The input of the fourth delay device Del4 receives the first control code C0, and the output of the fourth delay device Del4 is connected to the set terminal S of the third RS flip-flop 1013. The input of the fifth delay device Del5 receives the second control code C1, and the output of the fifth delay device Del5 is connected to the reset terminal R of the third RS flip-flop 1013. The non-inverting output terminal Q of the third RS flip-flop 1013 outputs the third bit Q2 of the status code, and the inverting output terminal Q of the third RS flip-flop 1013 outputs the third inverted bit Q2N of the status code.

[0086] In the embodiments of the present disclosure, reference Figure 4 The three RS flip-flops 1011, 1012, and 1013 each receive a different control code at their set and reset terminals S and R. Triggered by the control code, the three RS flip-flops 1011, 1012, and 1013 each output three bits of data from the status code. These three bits combine to form a status code representing the chip's status. The third bit, Q2, is the least significant bit of the status code, the second bit, Q1, is the second least significant bit, and so on.

[0087] In the embodiment of the present disclosure, the value of each bit of the status code is represented by a level, a high level represents "1", and a low level represents "0". Figure 4 If the status code is "001", the first bit of data Q0 is "0", the second bit of data Q1 is "0", and the third bit of data Q2 is "1"; accordingly, the non-inverting output terminal Q of the first RS trigger 1011 outputs a low level, and the inverting output terminal Q outputs a high level; the non-inverting output terminal Q of the second RS trigger 1012 outputs a low level, and the inverting output terminal Q outputs a high level; the non-inverting output terminal Q of the third RS trigger 1013 outputs a high level, and the inverting output terminal Q outputs a low level.

[0088] In some embodiments of the present disclosure, reference Figure 4 Each of the six control code generation units 104-109 includes a first NAND gate Nand1 and a first inverter Inv1. The input of the first NAND gate Nand1 receives the corresponding state excitation signal and state identification signal, and the output of the first NAND gate Nand1 is connected to the input of the first inverter Inv1. The output of the first inverter Inv1 outputs the corresponding control code.

[0089] In the embodiments of the present disclosure, reference Figure 4 Each of the six control code generation units 104-109 generates a corresponding control code based on the state excitation signal and state identification signal it receives. Specifically, if both the state excitation signal and the state identification signal are high, the corresponding control code is high; if at least one of the state excitation signal and the state identification signal is low, the corresponding control code is low.

[0090] Continue to refer Figure 4In the first control code generation unit 104, the first NAND gate Nand1 receives the state excitation signal CSHi and the state identification signal PD, and outputs the inverted level C0N of the first control code. The first inverter Inv1 outputs the first control code C0. In the second control code generation unit 105, the first NAND gate Nand1 receives the state excitation signal CSLo and the transition state identification signal Q011, and outputs the inverted level C1N of the second control code. The first inverter Inv1 outputs the first control code C1. In the third control code generation unit 106, the first NAND gate Nand1 receives the state excitation signal PDEcmd and the state identification signal PDX, and outputs the inverted level C2N of the third control code. The first inverter Inv1 outputs the third control code C2. In the fourth control code generation unit 107, the first NAND gate Nand1 receives the state excitation signal DSMcmd and the state identification signal PDX, and outputs the inverted level C3N of the fourth control code. The first inverter Inv1 outputs the fourth control code C3. In the fifth control code generation unit 108, the first NAND gate Nand1 receives the state excitation signal CSHi and the state identification signal DSM, and outputs the inverted level C4N of the fifth control code. The first inverter Inv1 outputs the fifth control code C4. In the sixth control code generation unit 109, the first NAND gate Nand1 receives the state excitation signal CSLo and the state identification signal PDPre, and outputs the inverted level C5N of the sixth control code. The first inverter Inv1 outputs the sixth control code C5.

[0091] In some embodiments of the present disclosure, continue to refer to Figure 4 The transition control code generation unit 110 includes a second inverter Inv2 and a third inverter Inv3. The input of the second inverter Inv2 receives the current state identification signal PDXPre, and the output of the second inverter Inv2 is connected to the input of the third inverter Inv3. The output of the third inverter Inv3 outputs the transition control code C01. That is, when the current state identification signal PDXPre is at a high level, the transition control code C01 is output at a high level.

[0092] In some embodiments of the present disclosure, reference Figure 5 The state identification signal generating circuit 20 includes: a plurality of state identification signal generating units 201 - 206. Each of the state identification signal generating units 201 - 206 includes: a second NAND gate Nand2 and a fourth inverter Inv4.

[0093] A first input of the second NAND gate Nand2 receives the first data bit Q0 or the first inverted data bit Q0N of the status code. A second input of the second NAND gate Nand2 receives the second data bit Q1 or the second inverted data bit Q1N of the status code. A third input of the second NAND gate Nand2 receives the third data bit Q2 or the third inverted data bit Q2N of the status code. An output of the second NAND gate Nand2 is connected to an input of a fourth inverter Inv4. An output of the fourth inverter Inv4 outputs a corresponding status identification signal.

[0094] In the disclosed embodiment, different state codes will cause the corresponding state identification signal generating unit to output a high-level state identification signal. In this way, each state of the chip corresponds to a state code, achieving precise control of the chip state.

[0095] refer to Figure 5 For example, in the state identification signal generating unit 201, the second NAND gate Nand2 receives the first-bit inverted data Q0N, the second-bit inverted data Q1N, and the third-bit inverted data Q2N; when the state code is "000", that is, when the first-bit inverted data Q0N, the second-bit inverted data Q1N, and the third-bit inverted data Q2N are all high levels, the fourth inverter Inv4 in the state identification signal generating unit 201 outputs a high-level state identification signal PD; otherwise, it outputs a low-level state identification signal PD.

[0096] For another example, in the status identification signal generating unit 202, the second NAND gate Nand2 receives the first-bit inverted data Q0N, the second-bit inverted data Q1N, and the third-bit data Q2; thus, when the status code is "001", that is, when the first-bit inverted data Q0N, the second-bit inverted data Q1N, and the third-bit data Q2 are all high levels, the fourth inverter Inv4 outputs a high-level status identification signal PDXPre; otherwise, it outputs a low-level status identification signal PDXPre.

[0097] In some embodiments of the present disclosure, reference Figure 5 The multiple state identification signal generating units include: a first state identification signal generating unit 202, a transition state identification signal generating unit 206, and a second state identification signal generating unit 203. The current state code is 001; the current state transition code is 011; and the next state code is 010.

[0098] The first state identification signal generating unit 202 receives the first inverted data bit Q0N, the second inverted data bit Q1N, and the third data bit Q2 of the state code and outputs a current state identification signal PDXpre. The transition state identification signal generating unit 206 receives the first inverted data bit Q0N, the second data bit Q1, and the third data bit Q2 of the state code and outputs a transition state identification signal Q011. The second state identification signal generating unit 203 receives the first inverted data bit Q0N, the second data bit Q1, and the third inverted data bit Q2N of the state code and outputs a next state identification signal PDX.

[0099] In the embodiment of the present disclosure, the state code "001" can be set in the memory DRAM to correspond to the PDXpre state, the state code "010" to correspond to the PDX state; and the state code "011" does not correspond to any state. Figure 4 and Figure 5 When the memory is in the PDX state, the first state identification signal generation unit 202 generates a high-level current state identification signal PDXpre based on the current state code "001." Furthermore, the transition control code generation unit 110 generates a high-level transition control code C01 based on the high-level current state identification signal PDXpre. Furthermore, triggered by the transition control code C01, the trigger unit 102 outputs a high-level second-bit data Q1. In other words, the state code generation circuit 10 outputs the current state transition code "011." Furthermore, the transition state identification signal generation unit 206 outputs a high-level transition state identification signal Q011. However, since the current state transition code "011" does not correspond to any state in the memory, the memory remains in the PDXpre state.

[0100] Further, continue to combine Figure 4 and Figure 5 In the process of the memory converting from the PDXpre state to the PDX state, the next state excitation signal CSLo is at a high level, and the transition state identification signal Q011 is at a high level. Therefore, the second control code generation unit 105 outputs a high-level second control code C1; further, the trigger unit 103 outputs a low-level third-bit data Q2 under the trigger of the second control code C1, that is, the state code generation circuit 10 outputs the current state transition code "010"; further, the second state identification signal generation unit 203 outputs a high-level next state identification signal PDX.

[0101] Understandably, the reference Figure 6During the transition from the PDXpre state to the PDX state, the memory first transitions from the current state code "001" to the current state transition code "011," and then from the current state transition code "011" to the next state code "010." Each state code transition changes only one bit of data. This prevents unexpected states within the memory and ensures the reliability and accuracy of the memory state.

[0102] The present disclosure also provides a memory device, such as Figure 7 As shown, the memory 90 may include the state control logic circuit 80 described in any one of the aforementioned embodiments.

[0103] In some embodiments of the present disclosure, reference Figure 7 , the memory 90 may be a DRAM chip. Further, in some embodiments, the memory 90 complies with the DDR5 memory specification.

[0104] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0105] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0106] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A chip state control method, characterized in that: The method comprises: Generate a current state code based on the current state excitation signal and the previous state identification signal; Generate a current state identification signal for indicating the current state of the chip based on the current state code; In response to the current state identification signal, the current state code is changed to a current state transition code, where the current state transition code is a redundant state code that does not correspond to any state in the chip; generating a next state code based on a next state excitation signal and the current state transition code; wherein the current state code and the next state code differ in at least two bits, the current state transition code and the next state code differ in only one bit, and the current state code and the current state transition code differ in only one bit; A next state identification signal for indicating the next state of the chip is generated from the next state code.

2. The chip state control method according to claim 1, characterized in that: Generating the next state code based on the next state excitation signal and the current state transition code includes: generating a transition state identification signal according to the current state transition code; The next state code is generated according to the transition state identification signal and the next state excitation signal.

3. The chip state control method according to claim 1 or 2, characterized in that: The status code consists of 3 bits of data; The current state code is 001; the current state transition code is 011; and the next state code is 010.

4. A state control logic circuit, characterized in that: The state control logic circuit includes: a state code generating circuit and a state identification signal generating circuit; The state code generating circuit is connected to the state code generating circuit and is configured to generate a current state code based on the current state excitation signal and the previous state identification signal; The state identification signal generating circuit is configured to generate a current state identification signal for indicating the current state of the chip based on the current state code; The state code generation circuit is further configured to, in response to the current state identification signal, change the current state code to a current state transition code; and generate a next state code based on a next state excitation signal and the current state transition code; wherein the current state code and the next state code differ by at least two bits, the current state transition code and the next state code differ by only one bit, and the current state code and the current state transition code differ by only one bit; wherein the current state transition code is a redundant state code that does not correspond to any state in the chip; The state identification signal generating circuit is further configured to generate a next state identification signal for indicating a next state of the chip based on the next state code.

5. The state control logic circuit according to claim 4, characterized in that: The state identification signal generating circuit is further configured to generate a transition state identification signal according to the current state transition code; The state code generation circuit is further configured to generate the next state code according to the transition state identification signal and the next state excitation signal.

6. The state control logic circuit according to claim 5, characterized in that: The state code generating circuit includes: 3 trigger units; Each trigger unit corresponds to one bit of data of the output status code; wherein, the first trigger unit outputs the first bit of data and the first bit of inverted data; the second trigger unit outputs the second bit of data and the second bit of inverted data; the third trigger unit outputs the third bit of data and the third bit of inverted data.

7. The state control logic circuit according to claim 6, characterized in that: The state code generating circuit further comprises: 6 control code generating units and 1 transition control code generating unit; Each of the control code generating units receives a corresponding state excitation signal and a state identification signal, and outputs a corresponding control code; The transition control code generating unit receives the current state identification signal and outputs a transition control code; The output ends of the six control code generating units and the output end of the one transition control code generating unit are correspondingly connected to the input ends of the three triggering units.

8. The state control logic circuit according to claim 7, characterized in that: The first trigger unit includes: a first RS trigger, a first delay device and a second delay device; The input end of the first delay device receives the fourth control code, and the output end of the first delay device is connected to the set end of the first RS trigger; the input end of the second delay device receives the sixth control code, and the output end of the second delay device is connected to the reset end of the first RS trigger; the in-phase output end of the first RS trigger outputs the first bit data of the status code, and the inverting output end of the first RS trigger outputs the first inverted bit data of the status code.

9. The state control logic circuit according to claim 7, characterized in that: The second trigger unit includes: a second RS trigger, an OR gate and a third delay; The input end of the third delay device receives the transition control code, and the output end of the third delay device is connected to the set end of the second RS trigger; the input end of the OR gate receives the third and fifth control codes respectively, and the output end of the OR gate is connected to the reset end of the second RS trigger; the in-phase output end of the second RS trigger outputs the second bit data of the status code, and the inverting output end of the second RS trigger outputs the second inverted data of the status code.

10. The state control logic circuit according to claim 7, characterized in that: The third trigger unit includes: a third RS trigger, a fourth delay device and a fifth delay device; The input end of the fourth delay device receives the first control code, and the output end of the fourth delay device is connected to the set end of the third RS trigger; the input end of the fifth delay device receives the second control code, and the output end of the fifth delay device is connected to the reset end of the third RS trigger; the in-phase output end of the third RS trigger outputs the third bit data of the status code, and the inverting output end of the third RS trigger outputs the third bit inverted data of the status code.

11. The state control logic circuit according to claim 7, characterized in that: Each of the control code generating units includes: a first NAND gate and a first inverter; The input end of the first NAND gate receives the corresponding state excitation signal and the state identification signal, the output end of the first NAND gate is connected to the input end of the first inverter; and the output end of the first inverter outputs the corresponding control code.

12. The state control logic circuit according to claim 7, characterized in that: The transition control code generating unit includes: a second inverter and a third inverter; The input end of the second inverter receives the current state identification signal, the output end of the second inverter is connected to the input end of the third inverter; and the output end of the third inverter outputs the transition control code.

13. The state control logic circuit according to claim 6, characterized in that: The state identification signal generating circuit includes: a plurality of state identification signal generating units; each of the state identification signal generating units includes: a second NAND gate and a fourth inverter; The first input terminal of the second NAND gate receives the first bit of data or the first inverted bit of data of the state code; the second input terminal of the second NAND gate receives the second bit of data or the second inverted bit of data of the state code; the third input terminal of the second NAND gate receives the third bit of data or the third inverted bit of data of the state code; The output end of the second NAND gate is connected to the input end of the fourth inverter; and the output end of the fourth inverter outputs the corresponding state identification signal.

14. The state control logic circuit according to claim 13, characterized in that: The plurality of state identification signal generating units include: a first state identification signal generating unit, a transition state identification signal generating unit, and a second state identification signal generating unit; The current state code is 001; the current state transition code is 011; the next state code is 010; The first state identification signal generating unit receives the first inverted bit data, the second inverted bit data and the third bit data of the state code, and outputs the current state identification signal; The transition state identification signal generating unit receives the first inverted bit data, the second bit data and the third bit data of the state code, and outputs the transition state identification signal; The second state identification signal generating unit receives the first inverted bit data, the second bit data, and the third inverted bit data of the state code, and outputs the next state identification signal.

15. A memory, characterized in that: The memory comprises the state control logic circuit according to any one of claims 4 to 14.

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