Level shifters, half-bridge converter circuits and electronics

Abstract

The present invention relates to the field of electronic technology, and provides a level shifter, a half-bridge conversion circuit and an electronic device, wherein the level shifter comprises an input module, a common-mode current suppression module and an output module; the first end and the second end of the common-mode current suppression module are electrically connected to the input module, and the third end and the fourth end of the common-mode current suppression module are electrically connected to the output module; the input module is used to generate a differential-mode signal according to an input signal, and transmit the differential-mode signal to the common-mode current suppression module; the common-mode current suppression module is used to generate a first voltage signal and a second voltage signal according to the differential-mode signal, and perform interference current suppression processing on the first voltage signal and the second voltage signal to obtain a third voltage signal and a fourth voltage signal and transmit them to the output module; the output module is used to process the third voltage signal and the fourth voltage signal and then output them. The interference current is suppressed by the common-mode current suppression module, thereby ensuring the normal operation of the level shifter and improving the performance of the level shifter.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a level shifter, a half-bridge conversion circuit and an electronic device. Background Art

[0002] With the continuous development of the third-generation semiconductor GaN (Gallium Nitride) power devices, high-power density and high-reliability power supply systems designed based on GaN power devices are gradually being widely used in the market. Due to the high-speed switching capability and high voltage resistance of GaN power devices, they can achieve a wider range of application scenarios compared to traditional Si-based power devices, giving them broad application prospects.

[0003] GaN power devices are often used as switching devices in half-bridge conversion circuits. In a half-bridge conversion circuit, since the switch node voltage between the high-side power tube and the low-side power tube, i.e., the floating ground voltage, will change, a level shifter is needed to adjust the floating power supply voltage of the high-side power tube to ensure that the high-side power tube can be correctly turned on and off according to the PWM (Pulse-Width Modulation) signal under different working conditions. Due to the high switching speed of GaN power devices, the switch node voltage will change greatly in a short period of time. This rapid change will produce coupling through the self-contained capacitance in the half-bridge conversion circuit to affect the floating power supply voltage of the high-side power tube. The common-mode current formed will interfere with the level shifter, affect the normal operation of the level shifter, and reduce the performance of the level shifter. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a level shifter, a half-bridge conversion circuit and an electronic device.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a level shifter, the level shifter comprising an input module, a common-mode current suppression module and an output module; a first end and a second end of the common-mode current suppression module are electrically connected to the input module, and a third end and a fourth end of the common-mode current suppression module are electrically connected to the output module;

[0007] The input module is used to generate a differential mode signal according to an input signal, and transmit the differential mode signal to the common mode current suppression module;

[0008] The common-mode current suppression module is used to generate a first voltage signal and a second voltage signal according to the differential-mode signal, and perform interference current suppression processing on the first voltage signal and the second voltage signal to obtain a third voltage signal and a fourth voltage signal and transmit them to the output module;

[0009] The output module is used for processing the third voltage signal and the fourth voltage signal and then outputting them.

[0010] In an optional embodiment, the common-mode current suppression module includes a first current suppression unit, a signal generating unit, and a second current suppression unit electrically connected in sequence; the signal generating unit is electrically connected to the first signal terminal of the input module through the first end and is electrically connected to the second signal terminal of the input module through the second end, and the signal generating unit is electrically connected to the first signal input terminal of the output module through the third end and is electrically connected to the second signal input terminal of the output module through the fourth end;

[0011] The signal generating unit is used to generate a first voltage signal and a second voltage signal according to the differential mode signal;

[0012] The first current suppression unit is used to perform interference current suppression processing on the first voltage signal to obtain the third voltage signal;

[0013] The second current suppression unit is used to perform interference current suppression processing on the second voltage signal to obtain the fourth voltage signal;

[0014] The signal generating unit is further configured to transmit the third voltage signal and the fourth voltage signal to the output module.

[0015] In an optional implementation, the signal generating unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, and a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;

[0016] The source end of each of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor is connected to a floating power supply voltage;

[0017] The source terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are respectively connected to a floating ground voltage;

[0018] The gate terminal and the drain terminal of the first PMOS tube, the gate terminal of the second PMOS tube and the gate terminal of the fifth PMOS tube are all connected to the first terminal;

[0019] The gate terminal and the drain terminal of the third PMOS tube, the gate terminal of the fourth PMOS tube and the gate terminal of the sixth PMOS tube are all connected to the second terminal;

[0020] The drain terminal of the second PMOS tube is connected to the gate terminal and the drain terminal of the first NMOS tube and the gate terminal of the second NMOS tube;

[0021] The drain terminal of the fourth PMOS tube is connected to the gate terminal and the drain terminal of the fourth NMOS tube and the gate terminal of the third NMOS tube;

[0022] The drain end of the fifth PMOS tube is connected to the drain end of the third NMOS tube, and the drain end of the fifth PMOS tube and the drain end of the third NMOS tube are both connected to the third end;

[0023] The drain end of the sixth PMOS tube is connected to the drain end of the second NMOS tube, and the drain end of the sixth PMOS tube and the drain end of the second NMOS tube are both connected to the fourth end.

[0024] In an optional implementation, the first current suppression unit includes a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube and a fifteenth PMOS tube, and a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and a third high-voltage NMOS tube;

[0025] The source ends of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are respectively connected to a floating power supply voltage;

[0026] The source terminals of the fifth NMOS transistor and the sixth NMOS transistor are respectively connected to a floating ground voltage;

[0027] The gate and drain of the seventh PMOS tube, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, and the gate of the tenth PMOS tube are all connected to the drain of the third high-voltage NMOS tube, and the gate and source of the third high-voltage NMOS tube are grounded;

[0028] The drain terminal of the eighth PMOS tube is connected to the gate terminal and the drain terminal of the fifth NMOS tube and the gate terminal of the sixth NMOS tube;

[0029] The drain end of the ninth PMOS tube is connected to the source end of the fifteenth PMOS tube;

[0030] The drain end of the tenth PMOS tube is connected to the first end;

[0031] The drain end of the sixth NMOS tube is connected to the source end of the seventh NMOS tube;

[0032] The drain end of the seventh NMOS tube and the drain end of the fifteenth PMOS tube are both connected to the third end, and the gate end of the seventh NMOS tube and the gate end of the fifteenth PMOS tube are both connected to the first signal output end of the output module.

[0033] In an optional implementation, the second current suppression unit includes an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube and a sixteenth PMOS tube, and an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube and a fourth high-voltage NMOS tube;

[0034] The source end of each of the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, and the fourteenth PMOS tube is connected to a floating power supply voltage;

[0035] The source terminals of the eighth NMOS transistor and the ninth NMOS transistor are respectively connected to a floating ground voltage;

[0036] The gate terminal and the drain terminal of the eleventh PMOS tube, the gate terminal of the twelfth PMOS tube, the gate terminal of the thirteenth PMOS tube, and the gate terminal of the fourteenth PMOS tube are all connected to the drain terminal of the fourth high-voltage NMOS tube, and the gate terminal and the source terminal of the fourth high-voltage NMOS tube are grounded;

[0037] The drain terminal of the twelfth PMOS tube is connected to the gate terminal and the drain terminal of the ninth NMOS tube and the gate terminal of the eighth NMOS tube;

[0038] The drain end of the thirteenth PMOS tube is connected to the source end of the sixteenth PMOS tube;

[0039] The drain end of the fourteenth PMOS tube is connected to the second end;

[0040] The drain end of the eighth NMOS tube is connected to the source end of the tenth NMOS tube;

[0041] The drain end of the tenth NMOS tube and the drain end of the sixteenth PMOS tube are both connected to the fourth end, and the gate end of the tenth NMOS tube and the gate end of the sixteenth PMOS tube are both connected to the second signal output end of the output module.

[0042] In an optional embodiment, the input module includes a pulse generator, a first high-voltage NMOS transistor and a second high-voltage NMOS transistor;

[0043] The drain terminal of the first high-voltage NMOS tube is connected to the first signal terminal, the gate terminal of the first high-voltage NMOS tube is connected to the pulse generator, and the source terminal of the first high-voltage NMOS tube is grounded;

[0044] The drain terminal of the second high-voltage NMOS tube is connected to the second signal terminal, the gate terminal of the second high-voltage NMOS tube is connected to the pulse generator, and the source terminal of the second high-voltage NMOS tube is grounded.

[0045] In an optional embodiment, the pulse generator includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter, and a first AND gate and a second AND gate;

[0046] The input end of the first inverter, the input end of the fourth inverter and one input end of the first AND gate are connected to a first signal generating end that outputs the input signal;

[0047] The output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is connected to the other input end of the first AND gate;

[0048] The output end of the fourth inverter is connected to the input end of the fifth inverter and one input end of the second AND gate, the output end of the fifth inverter is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter is connected to the other input end of the second AND gate;

[0049] The output end of the first AND gate is connected to the gate end of the first high-voltage NMOS transistor, and the output end of the second AND gate is connected to the gate end of the second high-voltage NMOS transistor.

[0050] In an optional embodiment, the output module has a first signal output terminal and a second signal output terminal, and the output module includes an eighth inverter, a ninth inverter, a tenth inverter, and an eleventh inverter;

[0051] The input end of the eighth inverter and the input end of the ninth inverter are both connected to the first signal input end; the input end of the tenth inverter and the input end of the eleventh inverter are both connected to the second signal input end;

[0052] The output end of the ninth inverter is connected to the input end of the tenth inverter and the input end of the eleventh inverter, and the output end of the tenth inverter is connected to the input end of the eighth inverter and the input end of the ninth inverter;

[0053] The output end of the eight inverters is connected to the first signal output end, and the output end of the eleventh inverter is connected to the second signal output end.

[0054] In a second aspect, the present invention provides a half-bridge conversion circuit, comprising a high-side power tube, a high-side drive circuit, a low-side power tube and a low-side drive circuit, wherein the high-side drive circuit comprises the level shifter described in any one of the aforementioned embodiments; the drain end of the high-side power tube is connected to the bus voltage, the gate end of the high-side power tube is connected to the high-side drive circuit, the source end of the high-side power tube is connected to the drain end of the low-side power tube, the gate end of the low-side power tube is connected to the low-side drive circuit, and the source end of the low-side power tube is grounded.

[0055] In a third aspect, the present invention provides an electronic device, comprising the half-bridge conversion circuit described in the aforementioned embodiment.

[0056] The level shifter, half-bridge conversion circuit and electronic device provided by the present invention, the level shifter includes an input module, a common-mode current suppression module and an output module; the first end and the second end of the common-mode current suppression module are electrically connected to the input module, and the third end and the fourth end of the common-mode current suppression module are electrically connected to the output module; the input module is used to generate a differential mode signal according to the input signal, and transmit the differential mode signal to the common-mode current suppression module; the common-mode current suppression module is used to generate a first voltage signal and a second voltage signal according to the differential mode signal, and perform interference current suppression processing on the first voltage signal and the second voltage signal to obtain a third voltage signal and a fourth voltage signal and transmit them to the output module; the output module is used to process the third voltage signal and the fourth voltage signal and then output them. The interference current is suppressed by the common-mode current suppression module, thereby ensuring the normal operation of the level shifter and improving the performance of the level shifter.

[0057] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 A schematic structural diagram of a half-bridge conversion circuit including an existing level shifter is shown;

[0060] Figure 2 One of the structural schematic diagrams of the level shifter provided in the embodiment of the present invention is shown;

[0061] Figure 3 A second structural schematic diagram of a level shifter provided in an embodiment of the present invention is shown;

[0062] Figure 4 The third structural schematic diagram of the level shifter provided by the embodiment of the present invention is shown;

[0063] Figure 5 A fourth structural schematic diagram of a level shifter provided in an embodiment of the present invention is shown;

[0064] Figure 6 A schematic structural diagram of a pulse generator provided in an embodiment of the present invention is shown.

[0065] Icon: M H -High side power tube; M L -Low side power tube; C B -Bootstrap capacitor; D B-bootstrap diode; N1-first terminal; N2-second terminal; N3-third terminal; N4-fourth terminal; IN1-first signal terminal; IN2-second signal terminal; S1-first signal input terminal; S2-second signal input terminal; OUT1-first signal output terminal; OUT2-second signal output terminal; 110-input module; 120-common mode current suppression module; 130-output module; 121-signal generation unit; 123-first current suppression unit; 125-second current suppression unit; PM1-first PMOS tube; PM 2-second PMOS tube; PM3-third PMOS tube; PM4-fourth PMOS tube; PM5-fifth PMOS tube; PM6-sixth PMOS tube; PM7-seventh PMOS tube; PM8-eighth PMOS tube; PM9-ninth PMOS tube; PM10-tenth PMOS tube; PM11-eleventh PMOS tube; PM12-twelfth PMOS tube; PM13-thirteenth PMOS tube; PM14-fourteenth PMOS tube; PM15-fifteenth PMOS tube; PM16-sixteenth PMOS tube; NM1-first NMOS tube; NM2-second NMOS tube; NM3-third NMOS tube; NM4-fourth NMOS tube; NM5-fifth NMOS tube; NM6-sixth NMOS tube; NM7-seventh NMOS tube; NM8-eighth NMOS tube; NM9-ninth NMOS tube; NM10-tenth NMOS tube; HNM1-first high-voltage NMOS tube; HNM2-second high-voltage NMOS tube; HNM3-third high-voltage NMOS tube; HNM4-fourth high-voltage NMOS tube; AND1-first AND gate; AND2-second AND gate; INV1-first inverter; INV2-second inverter; INV3-third inverter; INV4-fourth inverter; INV5-fifth inverter; INV6-sixth inverter; INV7-seventh inverter; INV8-eighth inverter; INV9-ninth inverter; INV10-tenth inverter; INV11-eleventh inverter; C1-first parasitic capacitor; C2-second parasitic capacitor; C3-third parasitic capacitor; C4-fourth parasitic capacitor. DETAILED DESCRIPTION

[0066] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0068] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0069] See also Figure 1 , is a schematic diagram of a half-bridge conversion circuit including an existing level shifter. The half-bridge conversion circuit includes a high-side power tube M using an E-Mode GaN power device H And low side power tube M L , and a high-side driving circuit and a low-side driving circuit. The high-side driving circuit includes a first signal generating terminal for outputting a PWM_IN1 signal, an existing level shifter, a buffer, a bootstrap capacitor C B and bootstrap diode D B The low-side drive circuit includes a second signal generating terminal for outputting a PWM_IN2 signal and a low-side driver. PWM_IN1 represents an input signal for controlling the on and off of the high-side power tube; PWM_IN2 represents an input signal for controlling the on and off of the low-side power tube. GND represents ground, V DDL Indicates the logic high voltage of the PWM signal output, V BUS Indicates bus voltage, V DDH Represents the floating supply voltage, V SSH Indicates the floating ground voltage.

[0070] In addition, the high-side power tube M H The drain terminal and bus voltage V BUS Connection, high side power tube M H The gate end is connected to the high-side drive circuit, and the high-side power tube M H The source end and the low-side power tube M L The drain end of the low-side power tube ML The gate end is connected to the low-side drive circuit, and the low-side power tube M L The source terminal is grounded.

[0071] Under normal working conditions of the half-bridge converter circuit, the high-side power tube M H And low side power tube M L Only one tube will be in the on state and the other tube will be in the off state. L After shutdown, the floating ground voltage V SSH The voltage will be quickly raised to the bus voltage V due to the inductor freewheeling in the load. BUS , PWM_IN1 rises from GND to V DDL , the output of the level shifter is determined by V SSH Rising to V DDH , high side power tube M H will turn on. The switch node voltage V SSH The large voltage change rate generated during the rapid rise period is dV SSH / dt will pass through the bootstrap capacitor C B Coupled to V DDH , causing great common-mode transient interference to the level shifter, affecting the normal operation of the level shifter. Therefore, the embodiment of the present invention provides a level shifter capable of suppressing common-mode current interference.

[0072] See also Figure 2 , is a schematic diagram of a structure of a level shifter provided by an embodiment of the present invention. The level shifter includes an input module 110, a common-mode current suppression module 120, and an output module 130; a first terminal N1 and a second terminal N2 of the common-mode current suppression module 120 are electrically connected to the input module 110, and a third terminal N3 and a fourth terminal N4 of the common-mode current suppression module 120 are electrically connected to the output module 130. In addition, the input module 110 is electrically connected to the first signal generating terminal, and the output module 130 has a first signal output terminal OUT1 and a second signal output terminal OUT2.

[0073] Among them, the input module 110 is used to generate a differential mode signal according to the input signal, and transmit the differential mode signal to the common mode current suppression module 120; the common mode current suppression module 120 is used to generate a first voltage signal and a second voltage signal according to the differential mode signal, and perform interference current suppression processing on the first voltage signal and the second voltage signal to obtain a third voltage signal and a fourth voltage signal and transmit them to the output module 130; the output module 130 is used to process the third voltage signal and the fourth voltage signal and then output them.

[0074] See also Figure 3, is another structural diagram of a level shifter provided by an embodiment of the present invention. The common-mode current suppression module 120 in the level shifter includes a first current suppression unit 123, a signal generating unit 121, and a second current suppression unit 125 which are electrically connected in sequence; the signal generating unit 121 is electrically connected to the first signal terminal IN1 of the input module 110 through the first terminal N1 and is electrically connected to the second signal terminal IN2 of the input module 110 through the second terminal N2, the signal generating unit 121 is electrically connected to the first signal input terminal S1 of the output module 130 through the third terminal N3 and is electrically connected to the second signal input terminal S2 of the output module 130 through the fourth terminal N4.

[0075] Among them, the signal generating unit 121 is used to generate a first voltage signal and a second voltage signal according to the differential signal; the first current suppression unit 123 is used to perform interference current suppression processing on the first voltage signal to obtain a third voltage signal; the second current suppression unit 125 is used to perform interference current suppression processing on the second voltage signal to obtain a fourth voltage signal; the signal generating unit 121 is also used to transmit the third voltage signal and the fourth voltage signal to the output module 130.

[0076] See also Figure 4 , is another structural diagram of the level shifter provided by an embodiment of the present invention. The signal generating unit 121 in the common-mode current suppression module 120 includes a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5 and a sixth PMOS tube PM6, as well as a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3 and a fourth NMOS tube NM4.

[0077] Wherein, the source terminals of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the floating power supply voltage. The source terminals of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the floating ground voltage. The gate terminal and the drain terminal of the first PMOS transistor PM1, the gate terminal of the second PMOS transistor PM2 and the gate terminal of the fifth PMOS transistor PM5 are all connected to the first terminal N1. The gate terminal and the drain terminal of the third PMOS transistor PM3, the gate terminal of the fourth PMOS transistor PM4 and the gate terminal of the sixth PMOS transistor PM6 are all connected to the second terminal N2. The drain terminal of the second PMOS transistor PM2 is connected to the gate terminal and the drain terminal of the first NMOS transistor NM1 and the gate terminal of the second NMOS transistor NM2. The drain terminal of the fourth PMOS transistor PM4 is connected to the gate terminal and the drain terminal of the fourth NMOS transistor NM4 and the gate terminal of the third NMOS transistor NM3. The drain end of the fifth PMOS transistor PM5 is connected to the drain end of the third NMOS transistor NM3, and the drain end of the fifth PMOS transistor PM5 and the drain end of the third NMOS transistor NM3 are both connected to the third terminal N3. The drain end of the sixth PMOS transistor PM6 is connected to the drain end of the second NMOS transistor NM2, and the drain end of the sixth PMOS transistor PM6 and the drain end of the second NMOS transistor NM2 are both connected to the fourth terminal N4.

[0078] Please continue reading Figure 4 The first current suppression unit 123 in the common-mode current suppression module 120 includes a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10 and a fifteenth PMOS tube PM15, as well as a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7 and a third high-voltage NMOS tube HNM3.

[0079] Among them, the source end of each of the seventh PMOS tube PM7, the eighth PMOS tube PM8, the ninth PMOS tube PM9 and the tenth PMOS tube PM10 is connected to the floating power supply voltage. The source end of each of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 is connected to the floating ground voltage. The gate end and the drain end of the seventh PMOS tube PM7, the gate end of the eighth PMOS tube PM8, the gate end of the ninth PMOS tube PM9 and the gate end of the tenth PMOS tube PM10 are all connected to the drain end of the third high-voltage NMOS tube HNM3, and the gate end and the source end of the third high-voltage NMOS tube HNM3 are grounded. The drain end of the eighth PMOS tube PM8 is connected to the gate end and the drain end of the fifth NMOS tube NM5 and the gate end of the sixth NMOS tube NM6. The drain end of the ninth PMOS tube PM9 is connected to the source end of the fifteenth PMOS tube PM15. The drain end of the tenth PMOS tube PM10 is connected to the first terminal N1. The drain end of the sixth NMOS tube NM6 is connected to the source end of the seventh NMOS tube NM7. The drain terminal of the seventh NMOS transistor NM7 and the drain terminal of the fifteenth PMOS transistor PM15 are both connected to the third terminal N3 , and the gate terminal of the seventh NMOS transistor NM7 and the gate terminal of the fifteenth PMOS transistor PM15 are both connected to the first signal output terminal OUT1 of the output module 130 .

[0080] Please continue reading Figure 4 The second current suppression unit 125 in the common-mode current suppression module 120 includes an eleventh PMOS tube PM11, a twelfth PMOS tube PM12, a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14 and a sixteenth PMOS tube PM16, as well as an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10 and a fourth high-voltage NMOS tube HNM4.

[0081] Among them, the source terminals of the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, and the fourteenth PMOS transistor PM14 are respectively connected to the floating power supply voltage. The source terminals of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are respectively connected to the floating ground voltage. The gate terminal and the drain terminal of the eleventh PMOS transistor PM11, the gate terminal of the twelfth PMOS transistor PM12, the gate terminal of the thirteenth PMOS transistor PM13, and the gate terminal of the fourteenth PMOS transistor PM14 are all connected to the drain terminal of the fourth high-voltage NMOS transistor HNM4, and the gate terminal and the source terminal of the fourth high-voltage NMOS transistor HNM4 are grounded. The drain terminal of the twelfth PMOS transistor PM12 is connected to the gate terminal and the drain terminal of the ninth NMOS transistor NM9 and the gate terminal of the eighth NMOS transistor NM8. The drain terminal of the thirteenth PMOS transistor PM13 is connected to the source terminal of the sixteenth PMOS transistor PM16. The drain terminal of the fourteenth PMOS transistor PM14 is connected to the second terminal N2. The drain terminal of the eighth NMOS transistor NM8 is connected to the source terminal of the tenth NMOS transistor NM10. The drain terminal of the tenth NMOS transistor NM10 and the drain terminal of the sixteenth PMOS transistor PM16 are both connected to the fourth terminal N4, and the gate terminal of the tenth NMOS transistor NM10 and the gate terminal of the sixteenth PMOS transistor PM16 are both connected to the second signal output terminal OUT2 of the output module 130.

[0082] See also Figure 5 , is another structural diagram of a level shifter provided by an embodiment of the present invention. The input module 110 in the level shifter includes a pulse generator, a first high-voltage NMOS transistor HNM1 and a second high-voltage NMOS transistor HNM2.

[0083] The drain terminal of the first high-voltage NMOS transistor HNM1 is connected to the first signal terminal IN1, the gate terminal of the first high-voltage NMOS transistor HNM1 is connected to the pulse generator, and the source terminal of the first high-voltage NMOS transistor HNM1 is grounded. The drain terminal of the second high-voltage NMOS transistor HNM2 is connected to the second signal terminal IN2, the gate terminal of the second high-voltage NMOS transistor HNM2 is connected to the pulse generator, and the source terminal of the second high-voltage NMOS transistor HNM2 is grounded.

[0084] See also Figure 6 , is a schematic diagram of the structure of a pulse generator provided by an embodiment of the present invention. The pulse generator includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6 and a seventh inverter INV7, as well as a first AND gate AND1 and a second AND gate AND2.

[0085] Among them, the input end of the first inverter INV1, the input end of the fourth inverter INV4 and one input end of the first AND gate AND1 are connected to the first signal generating end of the output input signal. The output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected to the other input end of the first AND gate AND1. The output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5 and one input end of the second AND gate AND2, the output end of the fifth inverter INV5 is connected to the input end of the sixth inverter INV6, the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7, and the output end of the seventh inverter INV7 is connected to the other input end of the second AND gate AND2. The output end of the first AND gate AND1 is connected to the gate end of the first high-voltage NMOS transistor HNM1 , and the output end of the second AND gate AND2 is connected to the gate end of the second high-voltage NMOS transistor HNM2 .

[0086] Please continue reading Figure 5 The output module 130 in the level shifter includes an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10 and an eleventh inverter INV11.

[0087] Among them, the input end of the eighth inverter INV8 and the input end of the ninth inverter INV9 are both connected to the first signal input terminal S1; the input end of the tenth inverter INV10 and the input end of the eleventh inverter INV11 are both connected to the second signal input terminal S2. The output end of the ninth inverter INV9 is connected to the input end of the tenth inverter INV10 and the input end of the eleventh inverter INV11, and the output end of the tenth inverter INV10 is connected to the input end of the eighth inverter INV8 and the input end of the ninth inverter INV9. The output end of the eight inverters is connected to the first signal output terminal OUT1, and the output end of the eleventh inverter INV11 is connected to the second signal output terminal OUT2.

[0088] The following will be combined Figure 5 The working principle of the level shifter provided by the embodiment of the present invention is introduced.

[0089] When the rising edge of the input signal PWM_IN1 arrives, the pulse generator generates a narrow pulse IN_R to turn on the first high-voltage NMOS tube HNM1, generating a drain-to-source current I D1 At the same time, the gate terminal signal of the second high-voltage NMOS tube HNM2 maintains the ground level, I D2 is 0.

[0090] In this case, on the one hand, I D1The node at the third terminal N3 is discharged through a current mirror formed by the first PMOS transistor PM1 and the second PMOS transistor PM2, and a current mirror formed by the first NMOS transistor NM1 and the second NMOS transistor NM2. D1 The node at the fourth terminal N4 is charged through the current mirror formed by the first PMOS transistor PM1 and the fifth PMOS transistor PM5. D2 =0, so the third PMOS transistor PM3, the fourth PMOS transistor PM4, the sixth PMOS transistor PM6, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are all turned off.

[0091] Therefore, at this time, the node at the third terminal N3 is mirrored to the differential mode current pull-down of the second NMOS tube NM2, and the node at the fourth terminal N4 is mirrored to the differential mode current pull-up of the fifth PMOS tube PM5. Then the node voltage at the third terminal N3, that is, the first voltage signal, is at a low level, and the node voltage at the fourth terminal N4, that is, the second voltage signal, is at a high level. Then, the first voltage signal and the second voltage signal are transmitted to the output module 130 and output after inversion processing to complete the output signal switching.

[0092] When the falling edge of the input signal PWM_IN1 arrives, the pulse generator generates a narrow pulse IN_F to turn on the second high-voltage NMOS tube HNM2, generating a drain-to-source current I D2 At the same time, the gate terminal signal of the first high-voltage NMOS tube HNM1 maintains the ground level, I D1 is 0.

[0093] In this case, on the one hand, I D2 The node at the fourth terminal N4 is discharged through a current mirror formed by the third PMOS transistor PM3 and the fourth PMOS transistor PM4, and a current mirror formed by the third NMOS transistor NM3 and the fourth NMOS transistor NM4; on the other hand, I D2 The current mirror formed by the third PMOS transistor PM3 and the sixth PMOS transistor PM6 charges the node at the third terminal N3. D1 =0, so the first PMOS transistor PM1, the second PMOS transistor PM2, the fifth PMOS transistor PM5, the first NMOS transistor NM1 and the second NMOS transistor NM2 are all turned off.

[0094] Therefore, at this time, the node at the third terminal N3 is mirrored to the differential mode current pull-up of the sixth PMOS transistor PM6, and the node at the fourth terminal N4 is mirrored to the differential mode current pull-down of the third NMOS transistor NM3. Then the node voltage at the third terminal N3, that is, the first voltage signal, is at a high level, and the node voltage at the fourth terminal N4, that is, the second voltage signal, is at a low level. Then, the first voltage signal and the second voltage signal are transmitted to the output module 130 and output after inversion processing to complete the output signal switching.

[0095] Therefore, the common-mode current suppression module 120 can ensure that the differential-mode signal, ie, the differential-mode current, generated by the input module 110 passes correctly.

[0096] It can be understood that the rising edge of the input signal PWM_IN1 generates a narrow pulse IN_R at the gate end of the first high-voltage NMOS transistor HNM1 through the pulse generator, so that the first high-voltage NMOS transistor HNM1 is turned on and generates a conduction current I D1 The falling edge of the input signal PWM_IN1 passes through the narrow pulse generator to generate a narrow pulse IN_F at the gate end of the second high-voltage NMOS tube HNM2, so that the second high-voltage NMOS tube HNM2 is turned on, generating a conduction current I D2 Since the rising and falling edges of the input signal PWM_IN1 appear alternately, I D1 with I D2 It is the alternating differential mode current.

[0097] Next we will continue to combine Figure 5 The working principle of the common-mode current suppression module 120 is introduced.

[0098] When the floating ground voltage V SSH When rising, transient interference dV is generated SSH / dt, since the drain and source of the first high-voltage NMOS transistor HNM1 are connected to the first parasitic capacitor C1, and the drain and source of the second high-voltage NMOS transistor HNM2 are connected to the second parasitic capacitor C2, a common-mode parasitic current I flowing through the drain and source of the first high-voltage NMOS transistor HNM1 and the second high-voltage NMOS transistor HNM2 will be generated at the same time. COM , and dV SSH The larger the dt, the COM The larger the I is, the first PMOS tube PM1 and the third PMOS tube PM3 need to bear the common mode parasitic current from the first high voltage NMOS tube HNM1 and the second high voltage NMOS tube HNM2. COM The larger the voltage is, the greater the voltage difference between the source terminal and the drain terminal of the first PMOS tube PM1 and the third PMOS tube PM3 is, that is, the lower the drain terminal potential of the first PMOS tube PM1 and the third PMOS tube PM3 is.

[0099] The following takes the rising edge of PWM_IN1 as an example to illustrate the working principle of the common mode current suppression module 120. When the rising edge of PWM_IN1 arrives, the node voltage at the third terminal N3, i.e., the first voltage signal, is at a low level, the node voltage at the fourth terminal N4, i.e., the second voltage signal, is at a high level, and the first signal output terminal OUT1 of the output module 130 outputs the floating power supply voltage V DDH , the second signal output terminal OUT2 outputs a floating ground voltage V SSH .

[0100] When the transient interference dV SSH When / dt arrives, the parasitic current I flowing through the third PMOS tube PM3 COM , through the current mirror formed by the third PMOS transistor PM3 and the sixth PMOS transistor PM6, the node at the third terminal N3 is charged, that is, the node at the third terminal N3 is pulled up. And the parasitic current I flowing through the third PMOS transistor PM3 COM , through the current mirror composed of the third PMOS tube PM3 and the fourth PMOS tube PM4, and the current mirror composed of the third NMOS tube NM3 and the fourth NMOS tube NM4, the node at the fourth terminal N4 is discharged, that is, the node at the fourth terminal N4 is pulled down, which affects the normal output of the level shifter.

[0101] Since high-voltage N-type MOS tubes of the same size as the first high-voltage NMOS tube HNM1 and the second high-voltage NMOS tube HNM2 are added, namely, the third high-voltage NMOS tube HNM3 and the fourth high-voltage NMOS tube HNM4, and the drain and source ends of the third high-voltage NMOS tube HNM3 are connected to the third parasitic capacitor C3, and the drain and source ends of the fourth high-voltage NMOS tube HNM4 are connected to the fourth parasitic capacitor C4, the same magnitude of common-mode parasitic current I flowing through the drain and source ends of the third high-voltage NMOS tube HNM3 and the fourth high-voltage NMOS tube HNM4 is also generated. COM .

[0102] The parasitic current I flowing through the seventh PMOS tube PM7 COM , through the current mirror formed by the seventh PMOS tube PM7 and the tenth PMOS tube PM10, the parasitic current I COM The drain end of the first PMOS tube PM1 is pulled down. And the parasitic current I flowing through the seventh PMOS tube PM7 COM , through the current mirror composed of the seventh PMOS tube PM7 and the eighth PMOS tube PM8, and the current mirror composed of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, since the first signal output terminal OUT1 outputs the floating power supply voltage V DDH , the seventh NMOS tube NM7 is turned on, then the parasitic current I COMThe node at the third terminal N3 is discharged through the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7, that is, the node at the third terminal N3 is pulled down, thereby suppressing the parasitic current I COM The node at the third terminal N3 is pulled up, thereby obtaining the first voltage signal after the interference current suppression process, that is, obtaining the third voltage signal.

[0103] The parasitic current I flowing through the eleventh PMOS tube PM11 COM , through the current mirror formed by the eleventh PMOS tube PM11 and the fourteenth PMOS tube PM14, the parasitic current I COM The drain end of the third PMOS transistor PM3 is pulled down. And the parasitic current I flowing through the eleventh PMOS transistor PM11 COM , through the current mirror formed by the eleventh PMOS transistor PM11 and the thirteenth PMOS transistor PM13, since the second signal output terminal OUT2 outputs the floating ground voltage V SSH , the sixteenth PMOS tube PM16 is turned on, then the parasitic current I COM The node at the fourth terminal N4 is charged through the thirteenth PMOS transistor PM13 and the sixteenth PMOS transistor PM16, that is, the node at the fourth terminal N4 is pulled up, thereby suppressing the parasitic current I COM The node at the fourth terminal N4 is pulled down, thereby obtaining the second voltage signal after the interference current suppression process, that is, obtaining the fourth voltage signal.

[0104] It is understandable that when the falling edge of PWM_IN1 arrives, due to dV SSH The first current suppression unit 123 and the second current suppression unit 125 will also suppress the interference of the common-mode parasitic current in a similar manner to ensure the correct output of the level shifter.

[0105] The embodiment of the present invention further provides a half-bridge conversion circuit, including a high-side power tube, a high-side drive circuit, a low-side power tube and a low-side drive circuit. The high-side drive circuit includes the level shifter provided by the embodiment of the present invention, and the connection relationship between these devices is as follows: Figure 1 shown.

[0106] An embodiment of the present invention further provides an electronic device, comprising the half-bridge conversion circuit provided by the embodiment of the present invention.

[0107] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0108] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0109] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A level shifter, characterized in that: The level shifter comprises an input module, a common-mode current suppression module and an output module; a first end and a second end of the common-mode current suppression module are electrically connected to the input module, and a third end and a fourth end of the common-mode current suppression module are electrically connected to the output module; The common-mode current suppression module comprises a first current suppression unit, a signal generating unit and a second current suppression unit which are electrically connected in sequence; the signal generating unit is electrically connected to the first signal terminal of the input module through the first terminal and is electrically connected to the second signal terminal of the input module through the second terminal, the signal generating unit is electrically connected to the first signal input terminal of the output module through the third terminal and is electrically connected to the second signal input terminal of the output module through the fourth terminal; The first current suppression unit includes a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube and a fifteenth PMOS tube, as well as a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and a third high-voltage NMOS tube; the source ends of the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube and the tenth PMOS tube are respectively connected to a floating power supply voltage; the source ends of the fifth NMOS tube and the sixth NMOS tube are respectively connected to a floating ground voltage; the gate end and the drain end of the seventh PMOS tube, the gate end of the eighth PMOS tube, the gate end of the ninth PMOS tube and the gate end of the tenth PMOS tube are all connected to the third high voltage NMOS tube. The drain end of the eighth PMOS tube is connected to the gate and drain ends of the fifth NMOS tube and the gate end of the sixth NMOS tube; the drain end of the ninth PMOS tube is connected to the source end of the fifteenth PMOS tube; the drain end of the tenth PMOS tube is connected to the first end; the drain end of the sixth NMOS tube is connected to the source end of the seventh NMOS tube; the drain end of the seventh NMOS tube and the drain end of the fifteenth PMOS tube are both connected to the third end, and the gate end of the seventh NMOS tube and the gate end of the fifteenth PMOS tube are both connected to the first signal output end of the output module; The second current suppression unit includes an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube and a sixteenth PMOS tube, as well as an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube and a fourth high-voltage NMOS tube; the source ends of the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube and the fourteenth PMOS tube are respectively connected to a floating power supply voltage; the source ends of the eighth NMOS tube and the ninth NMOS tube are respectively connected to a floating ground voltage; the gate end and the drain end of the eleventh PMOS tube, the gate end of the twelfth PMOS tube, the gate end of the thirteenth PMOS tube and the gate end of the fourteenth PMOS tube are all connected to the floating ground voltage. The drain end of the fourth high-voltage NMOS tube is connected to the drain end of the fourth high-voltage NMOS tube, and the gate end and the source end of the fourth high-voltage NMOS tube are grounded; the drain end of the twelfth PMOS tube is connected to the gate end and the drain end of the ninth NMOS tube and the gate end of the eighth NMOS tube; the drain end of the thirteenth PMOS tube is connected to the source end of the sixteenth PMOS tube; the drain end of the fourteenth PMOS tube is connected to the second end; the drain end of the eighth NMOS tube is connected to the source end of the tenth NMOS tube; the drain end of the tenth NMOS tube and the drain end of the sixteenth PMOS tube are both connected to the fourth end, and the gate end of the tenth NMOS tube and the gate end of the sixteenth PMOS tube are both connected to the second signal output end of the output module; The input module is used to generate a differential mode signal according to an input signal, and transmit the differential mode signal to the common mode current suppression module; The signal generating unit of the common mode current suppression module is used to generate a first voltage signal and a second voltage signal according to the differential mode signal; The first current suppression unit of the common mode current suppression module is used to perform interference current suppression processing on the first voltage signal to obtain a third voltage signal; The second current suppression unit of the common mode current suppression module is used to perform interference current suppression processing on the second voltage signal to obtain a fourth voltage signal; The signal generating unit of the common mode current suppression module is further used to transmit the third voltage signal and the fourth voltage signal to the output module; The output module is used for processing the third voltage signal and the fourth voltage signal and then outputting them.

2. The level shifter according to claim 1, wherein: The signal generating unit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, and a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; The source end of each of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor is connected to a floating power supply voltage; The source terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are respectively connected to a floating ground voltage; The gate terminal and the drain terminal of the first PMOS tube, the gate terminal of the second PMOS tube and the gate terminal of the fifth PMOS tube are all connected to the first terminal; The gate terminal and the drain terminal of the third PMOS tube, the gate terminal of the fourth PMOS tube and the gate terminal of the sixth PMOS tube are all connected to the second terminal; The drain terminal of the second PMOS tube is connected to the gate terminal and the drain terminal of the first NMOS tube and the gate terminal of the second NMOS tube; The drain terminal of the fourth PMOS tube is connected to the gate terminal and the drain terminal of the fourth NMOS tube and the gate terminal of the third NMOS tube; The drain end of the fifth PMOS tube is connected to the drain end of the third NMOS tube, and the drain end of the fifth PMOS tube and the drain end of the third NMOS tube are both connected to the third end; The drain end of the sixth PMOS tube is connected to the drain end of the second NMOS tube, and the drain end of the sixth PMOS tube and the drain end of the second NMOS tube are both connected to the fourth end.

3. The level shifter according to claim 2, characterized in that: The input module includes a pulse generator, a first high-voltage NMOS tube and a second high-voltage NMOS tube; The drain terminal of the first high-voltage NMOS tube is connected to the first signal terminal, the gate terminal of the first high-voltage NMOS tube is connected to the pulse generator, and the source terminal of the first high-voltage NMOS tube is grounded; The drain terminal of the second high-voltage NMOS tube is connected to the second signal terminal, the gate terminal of the second high-voltage NMOS tube is connected to the pulse generator, and the source terminal of the second high-voltage NMOS tube is grounded.

4. The level shifter according to claim 3, characterized in that: The pulse generator includes a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter, and a first AND gate and a second AND gate; The input end of the first inverter, the input end of the fourth inverter and one input end of the first AND gate are connected to a first signal generating end that outputs the input signal; The output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is connected to the input end of the third inverter, and the output end of the third inverter is connected to the other input end of the first AND gate; The output end of the fourth inverter is connected to the input end of the fifth inverter and one input end of the second AND gate, the output end of the fifth inverter is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter is connected to the other input end of the second AND gate; The output end of the first AND gate is connected to the gate end of the first high-voltage NMOS transistor, and the output end of the second AND gate is connected to the gate end of the second high-voltage NMOS transistor.

5. The level shifter according to claim 2, wherein: The output module has a first signal output terminal and a second signal output terminal, and the output module includes an eighth inverter, a ninth inverter, a tenth inverter and an eleventh inverter; The input end of the eighth inverter and the input end of the ninth inverter are both connected to the first signal input end; the input end of the tenth inverter and the input end of the eleventh inverter are both connected to the second signal input end; The output end of the ninth inverter is connected to the input end of the tenth inverter and the input end of the eleventh inverter, and the output end of the tenth inverter is connected to the input end of the eighth inverter and the input end of the ninth inverter; The output end of the eight inverters is connected to the first signal output end, and the output end of the eleventh inverter is connected to the second signal output end.

6. A half-bridge conversion circuit, characterized in that: It comprises a high-side power tube, a high-side driving circuit, a low-side power tube and a low-side driving circuit, wherein the high-side driving circuit comprises the level shifter described in any one of claims 1 to 5; the drain end of the high-side power tube is connected to the bus voltage, the gate end of the high-side power tube is connected to the high-side driving circuit, the source end of the high-side power tube is connected to the drain end of the low-side power tube, the gate end of the low-side power tube is connected to the low-side driving circuit, and the source end of the low-side power tube is grounded.

7. An electronic device, characterized in that: Includes the half-bridge converter circuit as claimed in claim 6.

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