Comparator offset voltage adjustment circuit and chip, electronic equipment

Abstract

A comparator offset voltage adjustment circuit and chip, and electronic equipment belong to the technical field of electronic circuits. A first control signal is accessed through an adjustment current source, and a reference current is mirrored according to the first control signal to output a first adjustment current; the polarity of the first adjustment current is associated with the first control signal; a voltage difference generating circuit converts the first adjustment current into an adjustment voltage, and outputs a positive adjustment signal and a negative adjustment signal based on the reference voltage and the adjustment voltage; the positive adjustment signal and the negative adjustment signal are used for comparator offset voltage adjustment, so a resistor, namely the resistor of the voltage difference generating circuit, is set in the comparator offset voltage adjustment circuit, so that the adjustment of positive and negative offset voltages can be realized, thereby saving the layout area and improving the accuracy of offset voltage adjustment.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic circuits, and in particular, relates to a comparator offset voltage adjustment circuit and chip, and electronic equipment. Background Art

[0002] For an ideal comparator, the output will change from low to high the moment the voltage at the positive input exceeds the negative input voltage. However, due to the mismatch of components in the comparator or the asymmetry of the circuit itself, in practice, the comparator output will only flip when the voltage at the positive input is a small voltage higher than the negative input voltage; this phenomenon is called offset, and the difference between the positive and negative input voltages at this moment is defined as the offset voltage.

[0003] The relevant comparator offset voltage adjustment circuit includes a comparator module circuit, a digital-to-analog conversion module circuit and an automatic offset correction system; the digital-to-analog conversion module circuit has two digital-to-analog conversions, which provide the comparator with a voltage value for offsetting the offset voltage through an auxiliary input terminal; the automatic offset voltage correction system has more than 8 state control modules inside, which can call the corresponding state control module to set the resistance value of the digital-to-analog conversion module circuit according to the comparator output voltage state in the previous clock cycle; thereby setting the resistance value of the digital-to-analog conversion module circuit according to the comparator output voltage state, and then adjusting the voltage value of the auxiliary input terminal to reduce the offset voltage.

[0004] However, the resistance setting of the digital-to-analog conversion module circuit is usually achieved through a resistor array and a corresponding switch array. On the one hand, the layout area of ​​the resistor is large; on the other hand, in the integrated circuit, the resistor will be unstable and have poor accuracy due to different processes.

[0005] Therefore, the accuracy of the related comparator offset voltage adjustment circuit is poor and the layout area is large. Summary of the invention

[0006] The purpose of the present application is to provide a comparator offset voltage trimming circuit and chip, and electronic equipment, aiming to solve the problems of poor accuracy and large layout area of ​​the related comparator offset voltage trimming circuit.

[0007] The embodiment of the present application provides a comparator offset voltage adjustment circuit, comprising:

[0008] a trimming current source configured to receive a first control signal and mirror a reference current according to the first control signal to output a first regulated current; the polarity of the first regulated current is associated with the first control signal;

[0009] a voltage difference generating circuit, connected to the trimming current source and the comparator, configured to convert the first regulating current into a regulating voltage, and output a positive regulating signal and a negative regulating signal based on a reference voltage and the regulating voltage;

[0010] The positive regulation signal and the negative regulation signal are used for adjusting the offset voltage of the comparator.

[0011] An embodiment of the present application further provides a comparator, characterized in that the comparator includes a comparison module and the above-mentioned comparator offset voltage adjustment circuit.

[0012] An embodiment of the present application provides a chip, which includes the above-mentioned comparator.

[0013] An embodiment of the present application further provides an electronic device, which includes the above-mentioned comparator.

[0014] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the trimming current source is connected to the first control signal, and the reference current is mirrored according to the first control signal to output the first trimming current; the polarity of the first trimming current is associated with the first control signal; the voltage difference generating circuit converts the first trimming current into a trimming voltage, and outputs a positive trimming signal and a negative trimming signal based on the reference voltage and the trimming voltage; the positive trimming signal and the negative trimming signal are used for trimming the offset voltage of the comparator, so a resistor, namely the resistor of the voltage difference generating circuit, is set in the offset voltage trimming circuit of the comparator, so that the offset voltage trimming can be realized, thereby saving the layout area and improving the accuracy of the offset voltage trimming. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic diagram of a comparator offset voltage adjustment circuit provided in an embodiment of the present application;

[0017] Figure 2 Another structural schematic diagram of a comparator offset voltage adjustment circuit provided in an embodiment of the present application;

[0018] Figure 3 Another structural schematic diagram of a comparator offset voltage adjustment circuit provided in an embodiment of the present application;

[0019] Figure 4 Another structural schematic diagram of a comparator offset voltage adjustment circuit provided in an embodiment of the present application;

[0020] Figure 5Another structural schematic diagram of a signal generating circuit in a comparator offset voltage adjustment circuit provided in an embodiment of the present application;

[0021] Figure 6 A partial exemplary circuit schematic diagram of a comparator offset voltage adjustment circuit provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of a hysteresis control range and a hysteresis adjustment range of a comparator provided in one embodiment of the present application;

[0023] Figure 8 A graph showing an offset voltage and a hysteresis voltage curve of a comparator provided in an embodiment of the present application;

[0024] Fig. 9 A partial exemplary circuit schematic diagram of a comparison module provided in an embodiment of the present application;

[0025] Fig.10 A schematic diagram of the structure of an output circuit in a comparator provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0028] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0029] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0030] Figure 1 The schematic diagram of the structure of the comparator offset voltage adjustment circuit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0031] The comparator offset voltage adjustment circuit comprises an adjustment current source 01 and a voltage difference generating circuit 02 .

[0032] The trimming current source 01 is configured to receive a first control signal and output a first regulated current according to the first control signal; the polarity of the first regulated current is associated with the first control signal;

[0033] The voltage difference generating circuit 02 is connected to the trimming current source 01 and the comparator, and is configured to convert the first regulating current into a regulating voltage, and output a positive regulating signal inp_trm and a negative regulating signal inn_trm based on the reference voltage ref and the regulating voltage;

[0034] The positive regulation signal inp_trm and the negative regulation signal inn_trm are used for comparator offset voltage trimming.

[0035] It should be noted that the first control signal can be provided by a digital circuit.

[0036] It should be emphasized that the polarity of the first regulating current is associated with the first control signal, so that the polarity of the first regulating current is controlled by the first control signal to achieve positive and negative bidirectional adjustment of the offset voltage.

[0037] like Figure 2 As shown, the comparator offset voltage adjustment circuit further includes a hysteresis control circuit 03.

[0038] The hysteresis control circuit 03 is configured to receive a second control signal and output a second regulating current according to the second control signal;

[0039] The voltage difference generating circuit 02 is specifically configured to superimpose the first regulating current and the second regulating current, and convert the superimposed current into a regulating voltage, and output a positive regulating signal inp_trm and a negative regulating signal inn_trm based on the reference voltage ref and the regulating voltage;

[0040] The positive regulation signal inp_trm and the negative regulation signal inn_trm are used for comparator offset voltage adjustment and comparator hysteresis voltage control.

[0041] By setting the hysteresis control circuit 03 to adjust the second adjustment current through the second control signal, the hysteresis voltage control of the comparator is realized on the basis of the bidirectional adjustment of the offset voltage.

[0042] like Figure 3 As shown, the hysteresis control circuit 03 includes a hysteresis adjustment circuit 031 and a control circuit 032 .

[0043] A hysteresis adjustment circuit 031 is configured to mirror the reference current according to a calibration signal to output a first current;

[0044] The control circuit 032 is connected to the hysteresis adjustment circuit 031, the adjustment current source 01, the voltage difference generating circuit 02 and the comparator, and is configured to mirror the first current according to the second control signal to output a second adjustment current.

[0045] The hysteresis voltage is adjusted by the hysteresis adjustment circuit 031 , and the hysteresis voltage is numerically controlled by the control circuit 032 , thereby improving the accuracy of the hysteresis voltage while achieving a wide range of hysteresis voltage control.

[0046] like Figure 4 As shown, the first control signal includes a first first sub-control signal, a second first sub-control signal and a third first sub-control signal; the comparator offset voltage adjustment circuit also includes a signal generating circuit 05.

[0047] The signal generating circuit 05 is connected to the trimming current source 01 and is configured to output a second first sub-control signal and a third first sub-control signal according to the second adjustment signal, the first first sub-control signal and the power-off signal.

[0048] The second adjustment signal includes a plurality of second sub-control signals; Figure 5 As shown, the signal generating circuit 05 includes a first NOR gate U1, a second NOR gate U2, an inverter U3, an AND gate U4 and an OR gate U5.

[0049] A first NOR gate U1 is configured to perform a NOR operation on a plurality of second sub-control signals to output a first digital signal OfftrmON;

[0050] A second NOR gate U2 is connected to the first NOR gate U1 and is configured to perform a NOR operation on the first digital signal OfftrmON and the power-off signal pdbuf to output a second digital signal pdB_Offtrm;

[0051] The inverter U3 is connected to the second NOR gate U2 and configured to invert the second digital signal pdB_Offtrm to output an inverted second digital signal pd_Offtrm;

[0052] The AND gate U4 is connected to the second NOR gate U2 and the inverter U3, and is configured to react the second digital signal pdB_Offtrm and the first first sub-control signal Offtrm <l>Performing an AND operation to output a second first sub-control signal pd_OffNMOS;

[0053] The OR gate U5 is connected to the inverter U3 and configured to invert the second digital signal pd_Offtrm and the first sub-control signal Offtrm. <l>An OR operation is performed to output a third first sub-control signal pd_OffPMOS. pd_OffNMOS and pd_OffPMOS determine the positive and negative polarities of the offset voltage adjustment.

[0054] Figure 6 A partial exemplary circuit structure of a comparator offset voltage adjustment circuit provided by an embodiment of the present invention is shown. For the sake of convenience, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0055] The control circuit 032 includes a fourth switch K4, m switch tubes Mbi, a first NMOS tube Mb0 and m first switches Kbi; i is a positive integer less than or equal to m;

[0056] The drain of the first NMOS transistor Mb0, the gate of the first NMOS transistor Mb0 and the gates of the m switch transistors Mbi serve together as the first current input terminal of the control circuit 032, and are connected to the hysteresis adjustment circuit 031 to access the first current;

[0057] The first ends of the m first switches Kbi are connected to the drains of the m switch tubes Mbi in a one-to-one correspondence;

[0058] The second ends of the m first switches Kbi are commonly connected to the first end of the fourth switch K4;

[0059] The second end of the fourth switch K4 is used as the second regulating current output end of the control circuit 032, and is connected to the trimming current source 01 and the voltage difference generating circuit 02 to output the second regulating current;

[0060] The control end of the fourth switch K4 serves as a switch signal input end of the control circuit 032 to receive the switch signal;

[0061] The control terminals of the m first switches Kbi serve together as the second control signal input terminal of the control circuit 032 to receive the second control signal;

[0062] The sources of the m switch tubes Mbi and the source of the first NMOS tube Mb0 are connected to the power ground.

[0063] A current mirror is formed by m switch tubes Mbi and the first NMOS tube Mb0 to realize the mirroring of the first current, and a preset multiple of the mirroring of the first current is controlled by m first switches Kbi.

[0064] The hysteresis adjustment circuit 031 includes a second NMOS transistor Mh0, a first PMOS transistor MP1, a second PMOS transistor MP2, 2n-1 field effect transistors Mhj and 2n-1 second switches Kcj; j is a positive integer less than or equal to n and a positive integer less than n';

[0065] The drain of the second NMOS transistor Mh0, the gate of the second NMOS transistor Mh0 and the gates of the 2n-1 field effect transistors Mhj are used together as the reference current input terminal of the hysteresis adjustment circuit 031 to access the reference current;

[0066] The drains of 2n-1 field effect transistors Mhj are connected to the first ends of 2n-1 second switches Kcj in a one-to-one correspondence;

[0067] The second ends of the 2n-1 second switches Kcj are connected to the drain of the first PMOS transistor MP1, the gate of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2;

[0068] The drain of the second PMOS transistor MP2 is used as the first current output terminal of the hysteresis adjustment circuit 031 and is connected to the control circuit 032 to output the first current;

[0069] The source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are connected to the first power source vdd;

[0070] The source of the second NMOS transistor Mh0 and the sources of 2n-1 field effect transistors Mhj are connected to the power ground.

[0071] A current mirror is formed by the second NMOS tube Mh0 and 2n-1 field effect tubes Mhj to realize the mirroring of the reference current, and a preset multiple of the reference current mirror is controlled by 2n-1 second switches Kcj; the current mirror including the first PMOS tube MP1 and the second PMOS tube MP2 mirrors the mirrored reference current again to output the first current.

[0072] The trimming current source O1 includes a second NMOS transistor Mh0, a third PMOS transistor Mo0, L transistors Mok, L third switches Kdk, a fourth PMOS transistor Ms1, a fifth PMOS transistor Ms2, a third NMOS transistor Ms3, a fourth NMOS transistor Mn1, a fifth NMOS transistor Mn2 and a sixth NMOS transistor Mo0'; k is a positive integer less than or equal to L;

[0073] The drain of the second NMOS transistor Mh0, the gate of the second NMOS transistor Mh0 and the gate of the sixth NMOS transistor Mo0' are used together as the reference current input terminal of the trimming current source O1 to access the reference current;

[0074] The drain of the sixth NMOS transistor Mo0' is connected to the drain of the third PMOS transistor Mo0, the gate of the third PMOS transistor Mo0, and the gates of the L transistors Mok, the drains of the L transistors Mok are connected to the first ends of the L third switches Kdk in a one-to-one correspondence, the second ends of the L third switches Kdk are connected to the source of the fourth PMOS transistor Ms1 and the source of the fifth PMOS transistor Ms2, the drain of the fifth PMOS transistor Ms2 is connected to the drain of the fourth NMOS transistor Mn1, the gate of the fourth NMOS transistor Mn1, and the gate of the fifth NMOS transistor Mn2, the source of the third NMOS transistor Ms3 is connected to the drain of the fifth NMOS transistor Mn2, and the drain of the third NMOS transistor Ms3 is connected to the drain of the fourth PMOS transistor Ms1;

[0075] The control terminals of the L third switches Kdk are used together as the first adjustment signal input terminal of the trimming current source O1 to receive the first adjustment signal;

[0076] The gate of the fifth PMOS transistor Ms2 is used as the first first sub-control signal input terminal of the trimming current source O1 to receive the first first sub-control signal;

[0077] The gate of the fourth PMOS transistor Ms1 serves as the third first sub-control signal input terminal of the trimming current source O1 to receive the third first sub-control signal;

[0078] The third NMOS transistor Ms3 is used as the second first sub-control signal input terminal of the trimming current source O1 to receive the second first sub-control signal;

[0079] The source of the third PMOS transistor Mo0 and the sources of the L transistors Mok are connected to the first power supply vdd;

[0080] The source of the fourth NMOS transistor Mn1 and the source of the fifth NMOS transistor Mn2 are connected to the power ground.

[0081] The current mirror including the second NMOS tube Mh0 and the sixth NMOS tube Mo0' mirrors the reference current, the current mirror including the third PMOS tube Mo0 and L transistors Mok mirrors the reference current again, and the L third switches Kdk control the preset multiple of the mirrored reference current again. The fourth PMOS tube Ms1, the fifth PMOS tube Ms2 and the third NMOS tube Ms3 control the polarity of the first regulating current.

[0082] The voltage difference generating circuit 02 includes a trimming resistor Rtrm; the first end of the trimming resistor Rtrm is connected to the reference voltage ref; the first end of the trimming resistor Rtrm also serves as the positive adjustment signal output end of the voltage difference generating circuit 02, and is connected to the comparator to output the positive adjustment signal; the second end of the trimming resistor Rtrm serves as the negative adjustment signal output end of the voltage difference generating circuit 02, and is connected to the comparator to output the negative adjustment signal; the second end of the trimming resistor Rtrm also serves as the first adjustment current input end of the voltage difference generating circuit 02, and is connected to the trimming current source 01 to access the first adjustment current; the second end of the trimming resistor Rtrm also serves as the second adjustment current input end of the voltage difference generating circuit 02, and is connected to the hysteresis control circuit 03 to access the second adjustment current.

[0083] In a specific implementation, the reference voltage can be connected to the first end of the trimming resistor Rtrm through a current limiting resistor Rx with a relatively small resistance.

[0084] The following is a combination of working principles Figure 6 As shown for further explanation:

[0085] The offset adjustment of the comparator is achieved by changing the current on the adjustment resistor Rtrm. In the adjustment current source O1, the reference current Io is copied into k currents through the first current mirror (the first current mirror includes the third PMOS tube Mo0 and L transistors (Mo1 to Mok). The sum of these k currents is used to generate the offset adjustment voltage V off,trm As an example, the offset adjustment module (adjustment current source 01) shown in the present application receives k first adjustment signals (Offtrm <0> To Offtrm <k>). And the inverter generates the inverted first adjustment signal (Offtrmb <0> To Offtrmb <k>, used to control the magnitude of the first regulating current. The k-way current passes through the second current mirror (the second current mirror includes the fourth NMOS tube Mn1 and the fifth NMOS tube Mn2) to copy the regulating current in the opposite direction. The first first sub-control signal Offtrm<k+1> By controlling the on and off of the fourth PMOS tube Ms1, the fifth PMOS tube Ms2 and the third NMOS tube Ms3, the direction of the offset adjustment current is controlled. There are four working modes for offset voltage adjustment. Taking L equal to 3 as an example, the following is combined with Figure 5 and Figure 6 For detailed explanation:

[0086] Working mode 1: Trim on, zero trim mode. The trim code is 1000 or 0000. In this mode, Offtrm <0> ,Offtrm <1> and Offtrm <2> Both are low, so OfftrmOn is high, and pdbuf is low in this mode, so pdB_Offtrm is low, and pd_Offtrm is high. <3> Whether it is high or low, pd_OffNMOS must be low and pd_OffPMOS must be high. Therefore, no trimming current (first trimming current) flows through the trimming resistor Rtrm, that is, the offset trimming voltage V off,trm is 0.

[0087] Working mode 2: Trim on, positive offset trim voltage V off,trm The trim code is 0001 to 0111. In this mode, Offtrm <0> ,Offtrm <1> and Offtrm <2> There is always one high, so OfftrmOn is low, and in this mode pdbuf is low, so pdB_Offtrm is high, and pd_Offtrm is low. <3> is low, pd_OffNMOS is low, and pd_OffPMOS is low. Therefore, the fourth PMOS tube Ms1 is turned on, the fifth PMOS tube Ms2 and the third NMOS tube Ms3 are turned off, and the polarity of the first regulating current is positive, so V inp,hys -V inm_hys <0, so the offset adjustment voltage V off,trm >0.

[0088] Working mode 3: Trim on, negative offset trim voltage V off,trm The adjustment code is 1001~1111. In this mode, Offtrm <0> ,Offtrm <1> and Offtrm <2> There is always one high, so OfftrmOn is low, and in this mode pdbuf is low, so pdB_Offtrm is high, and pd_Offtrm is low. <3> is high, pd_OffNMOS is high, and pd_OffPMOS is high. Therefore, the fifth PMOS tube Ms2 and the third NMOS tube Ms3 are turned on, the fourth PMOS tube Ms1 is turned off, and the polarity of the first regulating current is negative, so V inp,hys -V inm_hys >0, thus the offset adjustment voltage V off,trm <0.

[0089] Working mode 4: trimming off mode. The trimming code is xxxx. In this mode, pdbuf is high, so pdB_Offtrm is low, pd_Offtrm is high, so pd_OffNMOS is low, pd_OffPMOS is high, so the fourth PMOS tube Ms1 and the third NMOS tube Ms3 are both turned off, the first adjustment current is 0, so V inp,hys -V inm_hys =0, so the offset adjustment voltage V off,trm =0.

[0090] It should be noted that, in a specific implementation, the fourth NMOS transistor Mn1 and the fifth NMOS transistor Mn2 have the same size, and the maximum trimming current flowing through the fourth NMOS transistor Mn1 and the fifth NMOS transistor Mn2 is also the same, which means that if the trimming voltage V off,trm The maximum value of hys max , then its minimum value is -hys max Typically, the sizes of transistor Mo1 , transistor Mo2 and transistor Mo3 are 1, 2 and 4 times of the third PMOS transistor Mo0 , respectively, which is similar to the current source configuration of the control circuit 032 .

[0091] The hysteresis adjustment circuit 031 receives the external input reference current I0 and generates a hysteresis reference current I0 through a third current mirror (the third current mirror includes a second NMOS transistor Mh0 and 2n-1 field effect transistors Mhj). hys , I hys The size of the calibration signal htrim <1> to htrim<2n-1> control, and I hys After being copied by the fourth current mirror (the fourth current mirror includes Mp1 and Mp2 (the two have the same size)), the current is converted into the first current I0 ′. The first current I0 ′ serves as the input current of the control circuit 032 .

[0092] Hysteresis reference current I hys0 It is obtained by adding the n currents,

[0093] I hys0 =I h1 +I h2 +…+I h(n-1) +I hn

[0094] These n currents are generated by field effect transistor Mh1, field effect transistor Mh2, ... field effect transistor Mh(n-1) and field effect transistor Mhn respectively. In this way, the calibration signal htrim of hysteresis trimming <1> to htrim <n>are set high, closing the corresponding switches.

[0095] It should be noted that, in the current mirror of the hysteresis adjustment circuit 031, there are usually

[0096] I h2 =2I h1 ,I h3 =2I hl ,…I hn =2I h(n-1)

[0097] In order to be able to adjust the positive and negative hysteresis voltage V hys Deviation, hysteresis adjustment voltage V hys,trm It is necessary to cover its variation range, so the hysteresis adjustment current I hys The hysteresis reference current I hys0 Using the calibration signal to turn off Mh1,…Mh(n-1) can make I hys hys0 , and turning on Mh1', ...Mh(n-1)' can make I hys >I hys0 . And there are

[0098] I h1 '=I h1 ,…I h(n-1) '=I h(n-1)

[0099] By controlling the state of the second switch Kcj, the hysteresis current I hys The minimum and maximum values ​​are

[0100] I hys,min =I hn ,I hys,max =I hys0 +I h1 '+I h2 '+…+I h(n-1) '

[0101] It can be seen that the hysteresis reference current I hys0 That is I hys,max and I hys,min The mean of .

[0102] The comparator requires a variable hysteresis voltage V hys , and the hysteresis voltage V hys The change step size is fixed. Let V hys The minimum unit of change is V hys0 , and the maximum number of steps is h, then the expected V hys,trm The range should include 0,V hys0 ,2V hys0 …hV​ hys0 . Accordingly, V hys0 =I hys0 R trm Therefore, the achievable V hys Adjustment and control range can be referenced Figure 7 The process of hysteresis control and calibration is: determine the external second control signal according to the expected hysteresis amount, and use the control circuit 032 to obtain the biased V hys On this basis, the calibration signal is determined, and the adjusted V can be obtained by using the hysteresis adjustment circuit 031. hys,trm .

[0103] The control circuit 032 receives the first current I0' outputted from the hysteresis trimming circuit 031, and generates multiple hysteresis control currents by using the fifth current mirror (the fifth current mirror includes m switch tubes Mbi and the first NMOS tube Mb0). These currents converge into the second adjustment current, and these currents are controlled by the second control signal trim <0> To trim <m>Control the on and off, they determine the number of hysteresis steps. When the signal is high, the switch on the current branch is turned on, and when it is low, the switch is turned off.

[0104] The second regulating current finally flows into the trimming resistor Rtrm through the fourth switch controlled by the switch signal Comp_out. This is to ensure that the hysteresis only occurs when the voltage at the positive input terminal of the comparison signal changes from high to low, because the definition of hysteresis is based on the flip voltage when the voltage at the positive input terminal of the comparison signal changes from high to low (assuming that the voltage at the negative input terminal remains unchanged). This ensures that V hys >0, please refer to Figure 8 .

[0105] In a specific implementation, if the comparator is in the comparison mode, when the voltage at its positive input terminal gradually increases until it is higher than the negative input terminal, the output switch signal Comp_out jumps to high, and the switch controlled by it is correspondingly in the off state, so that no second adjustment current passes through the trimming resistor Rtrm, and the comparator does not produce hysteresis at this moment.

[0106] When the voltage at the positive input terminal of the comparator gradually decreases until it is lower than the negative input terminal, the switch signal COMP_out jumps to low, and the fourth switch K4 controlled by it is in the on state accordingly, so that the second regulating current flows through the trimming resistor Rtrm, and at this moment the comparator generates hysteresis.

[0107] In order to ensure a constant hysteresis reference voltage V hys0 Increment, the size of each hysteresis current needs to be set according to the following width-to-length ratio: Mb1:Ib1, Mb2:2Ib1, ...Mbn:2^(m-1)*Ib1. And it needs to satisfy,

[0108] V hys0 =I b1 +2I b1 +…+2^(m-1)*I b1 (10)

[0109] An embodiment of the present application further provides a comparator, which includes a comparison module and the above-mentioned comparator offset voltage adjustment circuit.

[0110] like Fig. 9 As shown, the comparison module includes two branches, a regulating circuit 13 and an output circuit 14 .

[0111] two branches, each having a main differential transistor and a load, configured to variably divide a first bias current according to an input positive signal and an input negative signal;

[0112] The regulating circuit 13 is connected to the two branches and the comparator offset voltage adjustment circuit, and is configured to output a first compensation current according to the positive regulation signal, and output a second compensation current according to the negative regulation signal; wherein the first compensation current and the second compensation current are output to two loads respectively;

[0113] The output circuit 14 , connected to the two branches and the regulating circuit 13 , is configured to generate a voltage signal based on the current flowing through the two loads.

[0114] Please refer to further Fig. 9 , the two branches are respectively a first branch 11 and a second branch 12; the first branch 11 includes a first main differential transistor M1 and a first load R1 connected in series between the first current source Ic1 and the power ground; the second branch 12 includes a second main differential transistor M2 and a second load R2 connected in series between the first current source Ic1 and the power ground. The gate of the first main differential transistor M1 serves as the negative input signal input terminal of the comparator to access the negative input signal; the gate of the second main differential transistor M2 serves as the positive input signal input terminal of the comparator to access the positive input signal. The first current source Ic1 is used to provide a first bias current Ic1.

[0115] The regulating circuit 13 includes a first auxiliary differential transistor M3 and a second auxiliary differential transistor M4; the source of the first auxiliary differential transistor M3 and the source of the second auxiliary differential transistor M4 are commonly connected to the negative electrode of the second current source Ic2; the drain of the first auxiliary differential transistor M3 serves as the second compensation current output terminal of the regulating circuit 13 to output the second compensation current; the drain of the second auxiliary differential transistor M4 serves as the first compensation current output terminal of the regulating circuit 13 to output the first compensation current; the gate of the first auxiliary differential transistor M3 serves as the negative regulation signal input terminal of the regulating circuit 13, connected to the comparator offset voltage adjustment circuit to receive the negative regulation signal; the gate of the second auxiliary differential transistor M4 serves as the positive regulation signal input terminal of the regulating circuit 13, connected to the comparator offset voltage adjustment circuit to receive the positive regulation signal.

[0116] The positive electrode of the second current source Ic2 and the positive electrode of the first current source Ic1 are connected to the first power source vdd.

[0117] It can be understood that the comparator core circuit adapted by the comparator offset voltage adjustment circuit in the present application is not limited to the above structure.

[0118] like Fig.10 As shown, the output circuit 14 includes an amplifier circuit 141 and a Schmitt trigger 142 .

[0119] an amplifier circuit 141, connected to the output circuit 14, and configured to amplify a first voltage, wherein the first voltage is a difference between voltage drops on two loads;

[0120] The Schmitt trigger 142 is connected to the amplifier circuit 141 and outputs a final comparison signal according to the polarity of the amplified first voltage.

[0121] The amplifier circuit 141 can ensure sufficient gain. The Schmitt trigger 142 is used to increase the anti-noise interference capability of the comparator output.

[0122] Combine the following Fig. 9 As shown in the following further description:

[0123] For an ideal comparator, the output will change from low to high the moment the voltage at the positive input exceeds the negative input voltage. However, due to the mismatch of components in the comparator or the asymmetry of the circuit itself, in practice, the comparator output will only flip when the voltage at the positive input is a small voltage higher than the negative input voltage; this phenomenon is called offset, and the difference between the positive and negative input voltages at this moment is defined as the offset voltage V off .

[0124] In some special comparators, when the positive input of the comparator changes from low to high and from high to low, the input voltage threshold corresponding to the output flip needs to be different. For example, if the positive input changes from high to low, when it is significantly lower than the negative input by a significant voltage (this voltage is artificially controlled rather than the offset voltage), the comparator output is expected to flip. This phenomenon is called hysteresis, and the artificially controlled voltage difference between the two ends is defined as the hysteresis voltage Vhys. The offset voltage and hysteresis voltage curves of the comparator are shown in Figure 1. Fig. 9 shown.

[0125] When the comparator output flips, the currents at the differential input terminals of the comparison signals are completely equal. Combined with the above definition, the offset voltage V off and hysteresis voltage V hys It can be obtained when the currents of the differential input pair are completely equal. Therefore, a compensation current associated with the input stage of the comparator core circuit is introduced to change the differential current of the comparison signal input stage corresponding to the comparator flip point, so that the expected hysteresis voltage V hys . And because the offset voltage V off and hysteresis voltage V hys Variations with process corners, temperature, and supply voltage (called V off and V hys Deviation), a trimming mechanism is needed for these two to generate the corresponding offset trimming voltage V off,trm and hysteresis trim voltage V hys,trm .

[0126] In the comparator core circuit, the comparison signal input terminal and the adjustment input terminal are both differential input pairs composed of MOS transistors (first MOS transistor M1, second MOS transistor M2, third MOS transistor M3 and fourth MOS transistor M4), and they share the load (first resistor R1 and second resistor R2).

[0127] When the currents in the first resistor R1 and the second resistor R1 are the same, the comparator output flips. Therefore, at the flip point,

[0128] g m1 *V inm +g m3 *V inm,trm =g m2 *V inp +g m4 *V inp,trm (1)

[0129] where g m1 , g m2 , g m3 and g m4 are the transconductances of M1, M2, M3 and M4 respectively, and the negative input signal V inm 、Input positive signal V inp , negative regulation signal V inm,trm and the positive regulation signal V inp,trm They are the input voltages of the inm, inp, inm_trm and inp_trm ports respectively.

[0130] In a specific implementation, the same first bias current Ic1 and second bias current Ic2 can be used, and the sizes of M1, M2, M3 and M4 are all W / L.

[0131] g m1 *V inm +g m2 *V inp =g m3 *V inm,trm +g m4 *V inp,trm (2)

[0132] Combining (1) and (2), we have

[0133] g m1 *V inm =g m4 *V inp,trm, g m3 *V inm,trm =g m2 *V inp (3)

[0134] where g m2 =(2*I d2 *μ p C ox *W / L)^0.5,g m3 =(2*I d3 *μ p C ox *W / L)^0.5,I d2 and I d3 are the drain currents of M2 and M3 respectively.

[0135] When there is no offset and hysteresis (ideal equilibrium state), there is V inm =V inp ,V inm,trm =V inp,trm , then I d20 =I d30 (the current in the ideal equilibrium state), and

[0136] g m2 =g m3 (4)

[0137] When an unbalanced voltage change is introduced in the balanced state, the change in the positive comparison signal that causes the comparator hysteresis is ΔV inp , accordingly, the change in the negative terminal signal of the trim input is ΔV inm,trm , and by ΔV inp and ΔV inm,trm The current change caused is ΔI d2 and ΔI d3 , then according to (3),

[0138] (2*((I d30 +ΔI d3 )*μ p Cox*W / L)^0.5*ΔV inm,trm =(2*(I d2 +ΔI d2 )*μ p Cox*W / L)^0.5*ΔV inp

[0139] Due to ΔI d2 =g m2 ΔV inp , ΔI d3 =g m3 ΔV inp,trm , combined with (4) we have

[0140] ΔI d2 =ΔI d3 , ΔV inp =ΔV inm,trm (5)

[0141] Therefore, to generate a V with a value of ΔV hys , a second regulating current is required to generate a voltage difference at the trimming input terminal to satisfy V inp,trm –V inm,trm =ΔV.

[0142] Similarly, a voltage difference can also be applied to the trimming input terminal, and the offset trimming voltage V can be generated at the comparison signal input terminal through the first adjustment current. off,trm , thereby achieving an offset voltage V off Adjustment.

[0143] Based on the above ideas, Figure 7 Combination Fig.10 , offset adjustment, hysteresis control and hysteresis adjustment can be realized at the same time. Figure 7 In the example, inp_trm and the reference voltage ref can be connected through a very small resistor, thereby determining the positive regulation signal V inp,trm The trimming resistor Rtrm is located between inp_trm and inm_trm. Adjusting the current flowing through the trimming resistor Rtrm can change the hysteresis voltage V hys , offset adjustment voltage V off,trm and hysteresis trim voltage V hys,trm size.

[0144] An embodiment of the present application also provides a chip, which includes the above-mentioned comparator.

[0145] It should be noted that the chip may be an octal small form factor pluggable (OSFP) optical module. The comparator in the OSFP optical module needs to compare the voltage signal inside the chip and has requirements for low offset and controllable hysteresis.

[0146] An embodiment of the present application further provides an electronic device, which includes the above-mentioned comparator.

[0147] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0148] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.< / m> < / n> < / k> < / k> < / l> < / l>

Claims

1. A comparator offset voltage adjustment circuit, characterized in that: include: A trimming current source is configured to receive a first control signal and mirror a reference current according to the first control signal to output a first regulated current; The polarity of the first regulating current is associated with the first control signal; a voltage difference generating circuit, connected to the trimming current source and the comparator, configured to convert the first regulating current into a regulating voltage, and output a positive regulating signal and a negative regulating signal based on a reference voltage and the regulating voltage; a hysteresis control circuit, configured to receive a second control signal and output a second regulating current according to the second control signal; The voltage difference generating circuit is specifically configured to superimpose the first regulating current and the second regulating current, convert the superimposed current into a regulating voltage, and output the positive regulating signal and the negative regulating signal based on a reference voltage and the regulating voltage; The positive regulation signal and the negative regulation signal are used for offset voltage adjustment of the comparator and hysteresis voltage control of the comparator; The hysteresis control circuit comprises: a hysteresis adjustment circuit configured to mirror the reference current according to a calibration signal to output a first current; a control circuit connected to the hysteresis trimming circuit, the trimming current source, the voltage difference generating circuit and the comparator, and configured to mirror the first current according to the second control signal to output the second regulated current; The control circuit includes a fourth switch, m switch tubes, a first NMOS tube and m first switches; i is a positive integer less than or equal to m; The drain of the first NMOS tube, the gate of the first NMOS tube and the gates of the m switch tubes serve together as a first current input terminal of the control circuit, and are connected to the hysteresis adjustment circuit to access the first current; The first ends of the m first switches are connected to the drains of the m switch tubes in a one-to-one correspondence; The second ends of the m first switches are commonly connected to the first end of the fourth switch; The second end of the fourth switch is connected to the voltage difference generating circuit and the comparator; The second end of the fourth switch serves as a second regulating current output end of the control circuit and is connected to the trimming current source to output the second regulating current; The control end of the fourth switch serves as a switch signal input end of the control circuit to receive a switch signal; The control terminals of the m first switches are commonly used as the second control signal input terminal of the control circuit to receive the second control signal; The sources of the m switch tubes and the source of the first NMOS tube are connected to the power ground.

2. The comparator offset voltage adjustment circuit according to claim 1, wherein: The hysteresis adjustment circuit includes a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, 2n-1 field effect transistors and 2n-1 second switches; j is a positive integer less than or equal to n and a positive integer less than n'; The drain of the second NMOS tube, the gate of the second NMOS tube and the gates of 2n-1 field effect tubes serve together as a reference current input terminal of the hysteresis adjustment circuit to access the reference current; The drains of 2n-1 of the field effect transistors are connected to the first ends of 2n-1 of the second switches in a one-to-one correspondence; The second ends of 2n-1 second switches are connected to the drain of the first PMOS tube, the gate of the first PMOS tube and the drain of the second PMOS tube; The drain of the second PMOS tube serves as the first current output terminal of the hysteresis adjustment circuit and is connected to the control circuit to output the first current; The source of the first PMOS tube and the source of the second PMOS tube are connected to a first power source; The source of the second NMOS tube and the sources of 2n-1 field effect tubes are connected to the power ground.

3. The comparator offset voltage adjustment circuit according to claim 1, wherein: The first control signal includes a first first sub-control signal, a second first sub-control signal and a third first sub-control signal; the comparator offset voltage adjustment circuit also includes: The signal generating circuit is connected to the trimming current source and configured to output the second first sub-control signal and the third first sub-control signal according to the second adjustment signal, the first first sub-control signal and the power-off signal.

4. The comparator offset voltage adjustment circuit as claimed in claim 3, characterized in that: The second adjustment signal includes a plurality of second sub-control signals; The signal generating circuit comprises: A first NOR gate is configured to perform a NOR operation on a plurality of inverted second sub-control signals to output a first digital signal; a second NOR gate, connected to the first NOR gate, and configured to perform a NOR operation on the first digital signal and the power-off signal to output a second digital signal; an inverter, connected to the second NOR gate, and configured to invert the second digital signal to output the inverted second digital signal; an AND gate connected to the second NOR gate and the inverter, and configured to perform an AND operation on the second digital signal and the first first sub-control signal to output the second first sub-control signal; An OR gate is connected to the inverter and is configured to perform an OR operation on the inverted second digital signal and the first first sub-control signal to output the third first sub-control signal.

5. The comparator offset voltage adjustment circuit as claimed in claim 3, characterized in that: The trimming current source includes a second NMOS tube, a third PMOS tube, L transistors, L third switches, a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; k is a positive integer less than or equal to L; The drain of the second NMOS tube, the gate of the second NMOS tube and the gate of the sixth NMOS tube are used together as a reference current input terminal of the trimming current source to access the reference current; The drain of the sixth NMOS tube is connected to the drain of the third PMOS tube, the gate of the third PMOS tube, and the gates of the L transistors, the drains of the L transistors are connected to the first ends of the L third switches in a one-to-one correspondence, the second ends of the L third switches are connected to the source of the fourth PMOS tube and the source of the fifth PMOS tube, the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube, and the gate of the fifth NMOS tube, and the source of the third NMOS tube is connected to the drain of the fifth NMOS tube; The control terminals of the L third switches are used together as the first regulating signal input terminal of the trimming current source to receive the first regulating signal; The gate of the fifth PMOS tube serves as the first first sub-control signal input terminal of the trimming current source to receive the first first sub-control signal; The gate of the fourth PMOS tube serves as the third first sub-control signal input terminal of the trimming current source to receive the third first sub-control signal; The third NMOS transistor serves as the second first sub-control signal input terminal of the trimming current source to receive the second first sub-control signal; The source of the third PMOS tube and the sources of the L transistors are connected to the first power supply; The source of the fourth NMOS tube and the source of the fifth NMOS tube are connected to the power ground.

6. A chip, characterized in that: The chip includes the comparator offset voltage adjustment circuit as claimed in any one of claims 1 to 5.

7. An electronic device, characterized in that: The electronic device comprises the comparator offset voltage adjustment circuit as claimed in any one of claims 1 to 5.

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