Semiconductor structure fabrication methods and semiconductor structures

Abstract

This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The fabrication method includes: providing a substrate having a first region and a second region spaced apart; growing a SiGe epitaxial layer in the first region; treating the surface of the SiGe epitaxial layer and the surface of the second region with a pre-prepared first reagent to form a first protective layer on the surface of the SiGe epitaxial layer and a second protective layer on the surface of the second region of the substrate; treating the first and second protective layers with a pre-prepared second reagent to remove the second protective layer; and forming a SiGe epitaxial layer with the first protective layer. This disclosure can effectively protect the SiGe epitaxial layer from loss during the manufacturing process of PMOS devices, improve the carrier mobility of PMOS devices, and thus improve the electrical performance of PMOS devices.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM includes Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) based on high-k dielectric and high-k metal gate (HKMG) technology.

[0003] In the HKMG-based MOSFET process of related technologies, the source and drain regions of P-type metal-oxide-semiconductor (PMOS) devices are provided with germanium-silicon (SiGe) epitaxial layers. The strained SiGe epitaxial layers can improve the carrier mobility of PMOS devices, thereby enhancing the electrical performance of PMOS devices.

[0004] However, in the SiGe epitaxial layer fabrication process of related technologies, the SiGe epitaxial layer is easily damaged and consumed, which affects the improvement of carrier mobility and thus affects the electrical performance of PMOS devices. Summary of the Invention

[0005] In a first aspect, this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0006] A substrate is provided, the substrate having a first region and a second region spaced apart;

[0007] A SiGe epitaxial layer is grown in the first region;

[0008] The surface of the SiGe epitaxial layer and the surface of the second region are treated with a pre-prepared first reagent to form a first protective layer on the surface of the SiGe epitaxial layer and a second protective layer on the surface of the second region of the substrate.

[0009] The first protective layer and the second protective layer are treated with a pre-prepared second reagent to remove the second protective layer;

[0010] The SiGe epitaxial layer with the first protective layer is formed.

[0011] In the above-described method for preparing the semiconductor structure, optionally, the first reagent includes SiH4.

[0012] In the above-described method for fabricating the semiconductor structure, optionally, pre-configured SiH4 is used to treat the surface of the SiGe epitaxial layer and the surface of the second region, including:

[0013] Under conditions of 580℃-650℃ and 3 torr-22 torr, the surface of the SiGe epitaxial layer and the surface of the second region are treated with SiH4 at a flow rate of 150 sccm-300 sccm for a time of 50 s-200 s.

[0014] In the above-described method for preparing the semiconductor structure, the second reagent may optionally include DCS and HCl.

[0015] In the above-described method for fabricating the semiconductor structure, optionally, the surface of the SiGe epitaxial layer and the surface of the second region are treated using pre-configured DCS and HCl, including:

[0016] Under conditions of 670℃-780℃ and 3 torr-22 torr, the surface of the SiGe epitaxial layer and the surface of the second region are treated with DCS at a flow rate of 50 sccm-150 sccm and HCl at a flow rate of 350 sccm-450 sccm for a surface treatment time of 150 s-330 s.

[0017] Optionally, in the above-described method for fabricating the semiconductor structure, after providing the substrate, the method further includes: forming an intermediate layer in the second region;

[0018] Remove a portion of the intermediate layer of the second region, and remove at least a portion of the first protective layer.

[0019] In the above-described method for fabricating a semiconductor structure, optionally, the substrate includes an array region, a peripheral core region, and a peripheral edge region, wherein the peripheral core region surrounds the outer periphery of the array region, and the peripheral edge region surrounds the outer periphery of the peripheral core region;

[0020] The peripheral core region includes a core PMOS region and a core NMOS region, and the peripheral edge region includes an edge PMOS region and an edge NMOS region;

[0021] The core PMOS region forms the first region, and the array region, the core NMOS region, the edge PMOS region, and the edge NMOS region form the second region.

[0022] In the above-described method for fabricating the semiconductor structure, optionally, after forming the SiGe epitaxial layer having the first protective layer, the method further includes:

[0023] A first mask layer is formed in the peripheral core region and the array region, and the first mask layer exposes the peripheral edge region;

[0024] A first gate oxide layer is formed along the first mask layer in the peripheral edge region;

[0025] A second mask layer is formed in the peripheral edge region and the array region, the second mask layer exposing the peripheral core region;

[0026] A second gate oxide layer is formed in the peripheral core region along the second mask layer;

[0027] The thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0028] In the above-described method for fabricating the semiconductor structure, optionally, the material of the first protective layer includes monocrystalline silicon, and the material of the second protective layer includes polycrystalline silicon.

[0029] In a second aspect, this disclosure provides a semiconductor structure including a substrate, a SiGe epitaxial layer, a first protective layer, a gate oxide layer, and a gate, wherein the substrate has a first region and a second region spaced apart.

[0030] The SiGe epitaxial layer is located in the first region, the first protective layer is located on the SiGe epitaxial layer, the gate oxide layer is located on the first protective layer, and the gate is located on the gate oxide layer;

[0031] The first protective layer is obtained by treatment with a pre-configured first reagent and a second reagent.

[0032] The semiconductor structure fabrication method and semiconductor structure disclosed herein form a first protective layer on the surface of a SiGe epitaxial layer using a first reagent, and a second protective layer on the remaining positions of the SiGe epitaxial layer; the second protective layer is removed using a second reagent while the first protective layer is retained. This effectively protects the SiGe epitaxial layer from loss during the manufacturing process of a PMOS device, improves the carrier mobility of the PMOS device, and thus improves the electrical performance of the PMOS device.

[0033] The structure of this disclosure, as well as its other disclosed purposes and beneficial effects, will become more apparent and understandable through the description of preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0036] Figure 2 This is a schematic diagram of a first cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0037] Figure 3 A schematic flowchart of a method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0038] Figure 4 This is a schematic diagram of a second cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0039] Figure 5 This is a schematic diagram of a third cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0040] Figure 6 This is a fourth cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure;

[0041] Figure 7 This is a fifth cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0042] Figure 8 Another schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0043] Figure 9 This is a sixth cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0044] Figure 10 This is a seventh cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0045] Figure 11 This is an eighth cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 12 A ninth cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure;

[0047] Figure 13 This is a tenth cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0048] Figure 14 This is an eleventh cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0049] Figure 15 This is a schematic diagram of the twelfth cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Figure 16 A thirteenth cross-sectional view of the semiconductor structure provided in this embodiment of the disclosure;

[0051] Figure 17 This is a schematic diagram of the fourteenth cross-sectional structure of the semiconductor structure provided in the embodiments of this disclosure.

[0052] Explanation of reference numerals in the attached figures:

[0053] 100 - Semiconductor structure; 110 - Substrate; 1101 - First region; 1102 - Second region; 111 - Array region; 112 - Peripheral core region; 113 - Peripheral edge region; 1121 - Core PMOS region; 1122 - Core NMOS region; 1131 - Edge PMOS region; 1132 - Edge NMOS region; 120 - SiGe epitaxial layer; 130 - First protective layer; 140 - Second protective layer; 150 - Intermediate layer; 161 - First mask layer; 171 - First gate oxide layer; 162 - Second mask layer; 172 - Second gate oxide layer; 180 - Gate conductive layer. Detailed Implementation

[0054] In related technologies, mobility, as an important parameter reflecting the conductivity of charge carriers in a semiconductor, is closely related to the thickness of the SiGe epitaxial layer. In one feasible implementation, for every increase in the thickness of the SiGe epitaxial layer... For every 1mV decrease in the threshold voltage of the PMOS gate, the threshold voltage decreases by 12mV for every 1% increase in the Ge concentration in the SiGe epitaxial layer. When SiGe undergoes loss, the thickness of the SiGe epitaxial layer decreases, and the Ge concentration in the SiGe epitaxial layer increases, causing the threshold voltage of the PMOS gate to rise. An excessively high threshold voltage is detrimental to the operation of the PMOS device and affects its electrical performance.

[0055] Based on the aforementioned technical problems, this disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure. A first protective layer is formed on the surface of a SiGe epitaxial layer using a first reagent, and a second protective layer is formed at the remaining locations of the SiGe epitaxial layer. The second protective layer is removed using a second reagent, leaving the first protective layer for protecting the SiGe epitaxial layer. This effectively protects the SiGe epitaxial layer from loss during PMOS device manufacturing, avoids reducing the thickness of the SiGe epitaxial layer, and avoids reducing the Ge concentration in the SiGe epitaxial layer. This, in turn, prevents the threshold voltage of the PMOS gate from rising, improves the carrier mobility of the PMOS device, and ultimately improves the electrical performance of the PMOS device.

[0056] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar structural components or structural components having the same or similar functions throughout. The described embodiments are partial embodiments of the structure of this disclosure, not embodiments of the entire structure. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0057] Firstly, refer to the appendix Figure 1 and attached Figure 2 As shown, this disclosure provides a semiconductor structure 100, which may include a substrate 110, and the substrate 110 may include an array region 111, a peripheral core region 112 and a peripheral edge region 113.

[0058] Specifically, the outer core region 112 surrounds the outer periphery of the array region 111, and the outer edge region 113 surrounds the outer periphery of the outer core region 112; the outer core region 112 includes a core PMOS region 1121 and a core NMOS region 1122, and the outer edge region 113 includes an edge PMOS region 1131 and an edge NMOS region 1132; the core PMOS region 1121 forms the first region 1101, and the array region 111, the core NMOS region 1122, the edge PMOS region 1131, and the edge NMOS region 1132 form the second region 1102.

[0059] It is understandable that the area between the first region 1101 and the second region 1102 can be a doped region, which can be an N-type doped region or a P-type doped region.

[0060] It should be noted that the substrate 110 can be ion-doped, wherein the type of ions doped in the substrate 110 can be opposite to the type of ions doped in the doped region. For example, when the doped region is an N-type doped region, the doped region is doped with N-type ions, and the substrate 110 is doped with P-type ions; in another example, when the doped region is a P-type doped region, the doped region is doped with P-type ions, and the substrate 110 is doped with N-type ions.

[0061] In some embodiments, the N-type ion can specifically be a phosphorus ion, an arsenic ion, or an antimony ion, and the P-type ion can specifically be a boron ion, an indium ion, or a boron fluoride ion.

[0062] It should be noted that the substrate 110 may have trenches, the first region 1101 may be located in the trenches, and the second region 1102 may also be located in the trenches, that is, the SiGe epitaxial layer 120, the first protective layer 130 and the second protective layer 140 may all be located in the trenches.

[0063] In some embodiments, the substrate 110 may be made of a semiconductor material. For example, the substrate 110 may be any one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate.

[0064] The embodiments disclosed herein do not limit the materials or types used to prepare the substrate 110, nor are they limited to the examples described above.

[0065] Secondly, refer to the appendix. Figure 3 Appendix Figure 8 As shown, this disclosure provides a method for fabricating a semiconductor structure 100, comprising:

[0066] See attached document Figure 2 Appendix Figure 3 and appendix Figure 4 As shown, S100 provides a substrate having a first region and a second region spaced apart.

[0067] See attached document Figure 3 Appendix Figure 5 and appendix Figure 8 As shown, in S200, a SiGe epitaxial layer is grown in the first region.

[0068] It is understandable that the SiGe epitaxial layer 120 can be grown using a selective epitaxial growth process.

[0069] Furthermore, the selective epitaxial growth process can be an epitaxial growth performed within the first region 1101 of the substrate 110.

[0070] See attached document Figure 3 Appendix Figure 6 and appendix Figure 8As shown, in step S300, a pre-prepared first reagent is used to treat the surface of the SiGe epitaxial layer and the surface of the second region, so that a first protective layer is formed on the surface of the SiGe epitaxial layer and a second protective layer is formed on the surface of the second region of the substrate.

[0071] It is understandable that after the SiGe epitaxial layer 120 is grown in the first region 1101, a first protective layer 130 can be formed on the surface of the SiGe epitaxial layer 120 by using a first reagent. The first protective layer 130 can protect the surface of the SiGe epitaxial layer 120 from the influence of subsequent manufacturing processes.

[0072] It should be noted that the first protective layer 130 can be preferentially consumed in subsequent manufacturing processes to protect the SiGe epitaxial layer 120; or, the first protective layer 130 can isolate the SiGe epitaxial layer 120 from other structures in subsequent manufacturing processes to protect the SiGe epitaxial layer 120.

[0073] See attached document Figure 3 Appendix Figure 7 and appendix Figure 8 As shown, in step S400, a pre-prepared second reagent is used to treat the first and second protective layers to remove the second protective layer.

[0074] It is understandable that the second protective layer 140 can be removed by the second reagent on the surface of the SiGe epitaxial layer 120 and the surface of the second region 1102, so as to retain the first protective layer 130 corresponding to the SiGe epitaxial layer 120, thereby achieving selectivity.

[0075] See attached document Figure 1 and attached Figure 2 As can be seen, in the embodiments disclosed herein, the SiGe epitaxial layer 120 can be formed in the core PMOS region 1121, and the intermediate layer 150 can be formed in the array region 111, the core NMOS region 1122, the edge PMOS region 1131, and the edge NMOS region 1132.

[0076] See attached document Figure 3 Appendix Figure 7 and appendix Figure 8 As shown, in S500, a SiGe epitaxial layer with a first protective layer is formed.

[0077] A first protective layer 130 is formed on the surface of the SiGe epitaxial layer 120 using a first reagent, and a second protective layer 140 is formed at the remaining positions of the SiGe epitaxial layer 120. The second protective layer 140 is removed using a second reagent, leaving the first protective layer 130 for protecting the SiGe epitaxial layer 120. In subsequent manufacturing processes, the first protective layer 130 can effectively protect the SiGe epitaxial layer 120 from loss, improve the carrier mobility of the PMOS device, and thus improve the electrical performance of the PMOS device.

[0078] As an optional implementation, the first reagent includes SiH4.

[0079] It is understood that SiH4 can be in a gaseous state. By introducing SiH4 into the substrate 110 and the SiGe epitaxial layer 120, SiH4 can form a first protective layer 130 on the surface of the SiGe epitaxial layer 120 in the first region 1101. The first protective layer 130 can be used to protect the SiGe epitaxial layer 120 from being damaged, which can improve the carrier mobility of the PMOS device and thus improve the electrical performance of the PMOS device. SiH4 can also form a second protective layer 140 on the surface of the substrate 110 in the second region 1102. The second protective layer 140 can protect the substrate 110.

[0080] It should be noted that the first protective layer 130 located at the SiGe epitaxial layer 120 can have the same or different thickness as the second protective layer 140 located in the second region 1102. For example, the thickness of the first protective layer 130 can be in the range of 1nm-2nm. For example, the thickness of the first protective layer 130 can be any one of 1.0nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2.0nm, etc.

[0081] In some embodiments, the thickness of the second protective layer 140 may also be in the range of 1nm-2nm. For example, the thickness of the second protective layer 140 may be any one of 1.0nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2.0nm, etc.

[0082] In some embodiments, the thickness of the second protective layer 140 may be greater than the thickness of the first protective layer 130, such as the thickness of the second protective layer 140 being in the range of 2nm-3nm.

[0083] In other embodiments, the thickness of the second protective layer 140 may also be less than the thickness of the first protective layer 130, such as the thickness of the first protective layer 130 being in the range of 0.5nm-1.0nm.

[0084] It is understood that when the second reagent is introduced, the second reagent can remove the second protective layer 140. The second protective layer 140 is a transitional structure in this embodiment of the disclosure, and the thickness of the second protective layer 140 is not limited in this embodiment of the disclosure, nor is it limited to the above example.

[0085] As an optional implementation, the first protective layer 130 is made of monocrystalline silicon, and the second protective layer 140 is made of polycrystalline silicon.

[0086] The material of the first protective layer 130 in this embodiment is not limited, nor is it limited to the examples described above. The second protective layer 140 is a transitional structure in this embodiment, and the material of the second protective layer 140 is not limited, nor is it limited to the examples described above.

[0087] It is understood that the material of the first protective layer 130 can be the same as the material of the substrate 110. For example, when the material of the substrate 110 is monocrystalline silicon, the material of the first protective layer 130 can be monocrystalline silicon.

[0088] By using the same material to prepare the first protective layer 130 and the substrate 110, the first protective layer 130 can improve the material purity and uniformity of the PMOS device, with higher surface flatness, higher cleanliness, fewer surface defects, fewer surface impurities, and reduced possibility of surface defects. It also has a more uniform resistivity, which can ensure the stability and reliability of the PMOS device, and thus ensure the electrical performance of the PMOS device.

[0089] As an optional implementation, the surface of the SiGe epitaxial layer 120 and the surface of the second region 1102 are processed using pre-configured SiH4, including:

[0090] Under conditions of 580℃-650℃ and 3 torr-22 torr, the surface of the SiGe epitaxial layer 120 and the surface of the second region 1102 were treated with SiH4 at a flow rate of 150 sccm-300 sccm for 50 s-200 s.

[0091] Understandably, SiH4 has certain requirements regarding its operating environment. Specifically, regarding the reaction temperature, if the temperature is below 580℃, the formation rate of the first protective layer 130 is slow, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device. If the temperature is above 650℃, the structure of the SiGe epitaxial layer 120 may change, and the degree of deformation increases with the increase of temperature, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device.

[0092] Regarding the reaction pressure, if the pressure is less than 3 torr, it is difficult for the pressure equipment to provide the pressure within the above range, which is quite challenging; if the pressure is greater than 22 torr, the SiH4 reaction rate is too fast, which is not conducive to the selective control.

[0093] Regarding the reaction time, if the surface treatment time is less than 50s, the first protective layer 130 is not completely deposited, and selectivity cannot be achieved, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device. If the surface treatment time is greater than 200s, the first protective layer 130 is over-deposited, the thickness of the first protective layer 130 is too large, the impedance increases, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device.

[0094] Regarding the SiH4 flow rate, if the flow rate is less than 150 sccm, the first protective layer 130 is not completely deposited, making it impossible to achieve selectivity. This is detrimental to improving the carrier mobility of the PMOS device, and consequently, it cannot improve the electrical performance of the PMOS device. If the flow rate is greater than 300 sccm, the first protective layer 130 is over-deposited, resulting in an excessively thick first protective layer 130 and increased impedance. This is also detrimental to improving the carrier mobility of the PMOS device, and consequently, it cannot improve the electrical performance of the PMOS device.

[0095] As an optional implementation, the second reagent includes DCS and HCl.

[0096] By using DCS (dichlorosilane) and HCl (hydrogen chloride), DCS and HCl can remove the second protective layer 140 on the surface of the substrate 110 in the second region 1102, thereby retaining the first protective layer 130 on the surface of the SiGe epitaxial layer 120 in the first region 1101. The first protective layer 130 can be used to protect the SiGe epitaxial layer 120 from being damaged, thereby improving the carrier mobility of the semiconductor structure 100 and thus improving the electrical performance of the semiconductor structure 100.

[0097] It should be noted that the order in which DCS and HCl are introduced can be: DCS first, then HCl; HCl first, then DCS; or both DCS and HCl can be introduced simultaneously. This disclosure does not limit the order in which DCS and HCl are introduced, nor is it limited to the examples described above.

[0098] As an optional implementation, the surface of the SiGe epitaxial layer 120 and the surface of the second region 1102 are processed using pre-configured DCS and HCl, including:

[0099] Under conditions of 670℃-780℃ and 3 torr-22 torr, the surface of SiGe epitaxial layer 120 and the surface of second region 1102 were treated with DCS with a flow rate of 50 sccm-150 sccm and HCl with a flow rate of 350 sccm-450 sccm for 150 s-330 s.

[0100] It is understandable that DCS and HCl have certain requirements for their operating environment. Specifically, if the temperature is below 670℃, the second protective layer 140 decomposes slowly, and residues of the second protective layer 140 are easily left behind, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device. If the temperature is above 780℃, while removing the second protective layer 140, the structure of the SiGe epitaxial layer 120 may be changed, and the degree of deformation increases with the increase of temperature, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device.

[0101] Regarding the reaction pressure, if the pressure is less than 3 torr, it is difficult for the pressure equipment to provide the pressure within the above range, making it difficult to achieve; if the pressure is greater than 22 torr, the reaction rate of DCS and HCl is too fast, which may affect the first protective layer 130 and is not conducive to selective control.

[0102] Regarding the reaction time, if the surface treatment time is less than 150s, the second protective layer 140 may not be completely removed, and some of the second protective layer 140 may remain, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device. If the surface treatment time is greater than 330s, it may affect the first protective layer 130, which is not conducive to selective control, not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device.

[0103] Regarding the DCS flow rate, if the DCS flow rate is less than 50 sccm, the second protective layer 140 may not be completely removed, and some of the second protective layer 140 may remain, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device. If the DCS flow rate is greater than 150 sccm, it may affect the first protective layer 130, which is not conducive to selective control, not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device.

[0104] Regarding the HCl flow rate, if the HCl flow rate is less than 350 sccm, the second protective layer 140 may not be completely removed, and some of the second protective layer 140 may remain, which is not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device. If the HCl flow rate is greater than 450 sccm, it may affect the first protective layer 130, which is not conducive to selective control, not conducive to improving the carrier mobility of the PMOS device, and thus cannot improve the electrical performance of the PMOS device.

[0105] As an optional implementation, after providing the substrate 110, the method further includes:

[0106] See attached document Figure 8 and appendix Figure 9 As shown, S110 forms an intermediate layer in the second region.

[0107] It should be noted that the formation order of the intermediate layer 150 and the SiGe epitaxial layer 120 can be arbitrary. For example, the intermediate layer 150 can be formed first, and then the SiGe epitaxial layer 120 can be formed; the SiGe epitaxial layer 120 can be formed first, and then the intermediate layer 150 can be formed; or the intermediate layer 150 and the SiGe epitaxial layer 120 can be formed simultaneously.

[0108] As an alternative implementation, after forming the intermediate layer 150 in the second region 1102, the SiGe epitaxial layer 120 is grown in the first region 1101, which will not be described in detail here.

[0109] It is understood that the intermediate layer 150 may include a first dielectric layer (not shown in the figure), a second dielectric layer (not shown in the figure), and a third dielectric layer (not shown in the figure) stacked together.

[0110] The first and third dielectric layers can be made of the same material, and can be oxides formed by atomic layer deposition.

[0111] It is understood that the second dielectric layer can be a nitride, and the material of the second dielectric layer can include silicon nitride.

[0112] A second protective layer 140 is formed on the surface of the second region 1102, comprising:

[0113] The second protective layer 140 is located on the intermediate layer 150.

[0114] See attached document Figure 10 As shown, the second protective layer 140 can be located on the intermediate layer 150, that is, the second protective layer 140 can be located on the first dielectric layer, the second dielectric layer and the third dielectric layer, that is, on the first dielectric layer or the third dielectric layer.

[0115] Understandably, refer to the appendix Figure 10As shown, the second protective layer 140 and the first protective layer 130 can be generated simultaneously. When a pre-prepared first reagent, namely pre-prepared SiH4, is introduced, the SiH4 forms the first protective layer 130 on the surface of the SiGe epitaxial layer 120, and at the same time, the second protective layer 140 is formed on the surface of the second region 1102, so as to protect the SiGe epitaxial layer 120 and the substrate 110 respectively.

[0116] See attached document Figure 11 As shown, the second protective layer 140 is removed by a pre-configured second reagent, namely a pre-configured DCS and HCl, to retain the first protective layer 130.

[0117] Furthermore, after removing the second protective layer 140 and before forming the gate oxide layer and the gate, the following steps are also included:

[0118] See attached document Figure 8 and appendix Figure 12 As shown, in step S510, a portion of the intermediate layer of the second region is removed, and at least a portion of the first protective layer is removed.

[0119] It should be noted that the first protective layer 130 can be preferentially consumed in subsequent manufacturing processes to protect the SiGe epitaxial layer 120. For example, during the removal of the intermediate layer 150, only a portion of the first protective layer 130 can be consumed, leaving the remaining portion. The remaining portion of the first protective layer 130 can improve the interface integrity of the PMOS device, which is beneficial to improving the electrical performance of the PMOS device.

[0120] See attached document Figure 8 and appendix Figure 12 As shown, as an optional implementation, removing a portion of the intermediate layer 150 of the second region 1102 includes:

[0121] S511: Remove the intermediate layer of the core NMOS region, the edge PMOS region, and the edge NMOS region, and retain the intermediate layer of the array region.

[0122] As an optional implementation, after forming the SiGe epitaxial layer 120 having the first protective layer 130, the method further includes:

[0123] S600, a gate oxide layer and a gate are formed in the first region based on a SiGe epitaxial layer with a first protective layer.

[0124] Furthermore, removing at least a portion of the first protective layer 130 also includes:

[0125] Remove the first protective layer 130, and the gate oxide layer and gate of the first region 1101 are located on the SiGe epitaxial layer 120.

[0126] Alternatively, a portion of the thickness of the first protective layer 130 may be removed, with the gate oxide layer and gate of the first region 1101 located on the retained first protective layer 130.

[0127] Understandably, the first protective layer 130 can be completely or partially removed. When the first protective layer 130 is completely removed, the gate oxide layer and the gate can be directly formed on the surface of the SiGe epitaxial layer 120. In this case, the impedance of the PMOS device is relatively small, which is beneficial to improving the carrier mobility of the PMOS device and thus improving the electrical performance of the PMOS device. When the first protective layer 130 is partially removed, the gate oxide layer and the gate are located on the retained first protective layer 130. The first protective layer 130 can be used to protect the SiGe epitaxial layer 120 from being damaged, which can improve the carrier mobility of the PMOS device and thus improve the electrical performance of the PMOS device.

[0128] In this embodiment of the disclosure, removing at least a portion of the first protective layer 130 further includes:

[0129] Remove part of the thickness of the first protective layer 130.

[0130] It is understandable that after removing part of the thickness of the first protective layer 130, the gate oxide layer and the gate of the first region 1101 can be located on the retained first protective layer 130.

[0131] As an optional implementation, after forming the SiGe epitaxial layer 120 having the first protective layer 130, that is, after forming a gate oxide layer and a gate in the first region 1101 based on the SiGe epitaxial layer 120 having the first protective layer 130, the method further includes:

[0132] See attached document Figure 8 Appendix Figure 13 As shown, S610 forms a first mask layer in the outer core region and array region, and the first mask layer exposes the outer edge region.

[0133] See attached document Figure 8 Appendix Figure 14 As shown, in step S620, a first gate oxide layer is formed in the peripheral edge region along the first mask layer.

[0134] See attached document Figure 8 Appendix Figure 15 As shown, S630 forms a second mask layer in the peripheral edge region and array region, and the second mask layer exposes the peripheral core region.

[0135] It is understandable that the first mask layer 161 can be removed before the second mask layer 162 is formed to expose the outer core region 112 and the array region 111.

[0136] See attached document Figure 8 Appendix Figure 16 As shown, in step S640, a second gate oxide layer is formed in the outer core region along the second mask layer.

[0137] As an optional implementation, after forming the second gate oxide layer 172 in the peripheral core region 112, the method further includes:

[0138] See attached document Figure 8 Appendix Figure 17 As shown, in S700, a gate conductive layer is formed on the first gate oxide layer and the second gate oxide layer, and a gate is formed.

[0139] In some embodiments, before forming the gate conductive layer 180, the second mask layer 162 may be removed to expose the peripheral edge region 113 and form the gate conductive layer 180.

[0140] It is understood that the first gate oxide layer 171 and the second gate oxide layer 172 can be high dielectric constant layers; wherein, the material of the high dielectric constant layer can include one or more of hafnium oxide, doped hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide; the material for preparing the gate conductive layer 180 can include one or more of tungsten, polycrystalline silicon, and titanium silicon nitride.

[0141] It should be noted that the materials used to prepare the first gate oxide layer 171 and the second gate oxide layer 172 may be the same or different. This disclosure does not limit whether the materials used to prepare the first gate oxide layer 171 and the second gate oxide layer 172 are the same, nor is it limited to the above example.

[0142] Using the above method, a first gate oxide layer 171 can be formed in the peripheral edge region 113, and then a second gate oxide layer 172 can be formed in the peripheral core region 112 to avoid conflict between the first gate oxide layer 171 and the second gate oxide layer 172.

[0143] In some embodiments, the thickness of the second gate oxide layer 172 is less than the thickness of the first gate oxide layer 171.

[0144] It is understandable that by using the first reagent and the second reagent to obtain the first protective layer 130 in the SiGe epitaxial layer 120, the first protective layer 130 can be used to protect the SiGe epitaxial layer 120 from being damaged, which can improve the carrier mobility of the PMOS device and thus improve the electrical performance of the PMOS device.

[0145] Through the above-described method for fabricating the semiconductor structure 100, this disclosure provides a semiconductor structure 100, which includes a substrate 110, a SiGe epitaxial layer 120, a first protective layer 130, a gate oxide layer, and a gate. The substrate 110 has a first region 1101 and a second region 1102 spaced apart. The SiGe epitaxial layer 120 is located on the surface of the first region 1101, the first protective layer 130 is located on the SiGe epitaxial layer 120, the gate oxide layer is located on the first protective layer 130, and the gate is located on the gate oxide layer. The first protective layer 130 is obtained by treatment with a pre-configured first reagent and a second reagent.

[0146] It is understood that the semiconductor structure 100 can be DRAM, which includes a substrate 110, a SiGe epitaxial layer 120, a first protective layer 130, a gate oxide layer, and a gate.

[0147] A first protective layer 130 is obtained by using a first reagent and a second reagent on the SiGe epitaxial layer 120. The first protective layer 130 can be used to protect the SiGe epitaxial layer 120 from being damaged, which can improve the carrier mobility of the semiconductor structure 100 and thus improve the electrical performance of the semiconductor structure 100.

[0148] In the description of the embodiments of this disclosure, it should be understood that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, the connection of internal structures of two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0149] The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure. In the description of this disclosure, "a plurality of" means two or more, unless otherwise precisely specified.

[0150] The terms “first,” “second,” “third,” “fourth,” etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to the structural or full structural technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a first region and a second region spaced apart; A SiGe epitaxial layer is grown in the first region; The surface of the SiGe epitaxial layer and the surface of the second region are treated with a pre-prepared first reagent to form a first protective layer on the surface of the SiGe epitaxial layer and a second protective layer on the surface of the second region of the substrate. The first protective layer and the second protective layer are treated with a pre-prepared second reagent to remove the second protective layer; The SiGe epitaxial layer with the first protective layer is formed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first reagent includes SiH4.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The surface of the SiGe epitaxial layer and the surface of the second region are processed using pre-configured SiH4, including: Under conditions of 580℃-650℃ and 3 torr-22 torr, the surface of the SiGe epitaxial layer and the surface of the second region are treated with SiH4 at a flow rate of 150 sccm-300 sccm for a time of 50 s-200 s.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The second reagent includes DCS and HCl.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The surface of the SiGe epitaxial layer and the surface of the second region are treated using a pre-configured DCS and HCl, including: Under conditions of 670℃-780℃ and 3 torr-22 torr, the surface of the SiGe epitaxial layer and the surface of the second region are treated with DCS at a flow rate of 50 sccm-150 sccm and HCl at a flow rate of 350 sccm-450 sccm for a surface treatment time of 150 s-330 s.

6. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, After providing the substrate, the method further includes: forming an intermediate layer in the second region; Remove a portion of the intermediate layer of the second region, and remove at least a portion of the first protective layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The substrate includes an array region, a peripheral core region, and a peripheral edge region. The peripheral core region surrounds the outer periphery of the array region, and the peripheral edge region surrounds the outer periphery of the peripheral core region. The peripheral core region includes a core PMOS region and a core NMOS region, and the peripheral edge region includes an edge PMOS region and an edge NMOS region; The core PMOS region forms the first region, and the array region, the core NMOS region, the edge PMOS region, and the edge NMOS region form the second region.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After forming the SiGe epitaxial layer having the first protective layer, the method further includes: A first mask layer is formed in the peripheral core region and the array region, and the first mask layer exposes the peripheral edge region; A first gate oxide layer is formed along the first mask layer in the peripheral edge region; A second mask layer is formed in the peripheral edge region and the array region, the second mask layer exposing the peripheral core region; A second gate oxide layer is formed in the peripheral core region along the second mask layer; The thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

9. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The first protective layer is made of monocrystalline silicon, and the second protective layer is made of polycrystalline silicon.

10. A semiconductor structure, prepared according to any one of claims 1-9, characterized in that, The system includes a substrate, a SiGe epitaxial layer, a first protective layer, a gate oxide layer, and a gate electrode. The substrate has a first region and a second region spaced apart from each other. The SiGe epitaxial layer is located in the first region, the first protective layer is located on the SiGe epitaxial layer, the gate oxide layer is located on the first protective layer, and the gate is located on the gate oxide layer.

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