A drive circuit for a battery management system

Abstract

The application belongs to the technical field of driving circuit, and discloses a driving circuit of a battery management system. The driving circuit comprises: a MOSFET module circuit connected between a normal power and a positive electrode of a storage battery; an input end of a latch circuit is connected with an output port of a master control chip and an output end of an overcurrent detection circuit, and an output end of the latch circuit is connected with a first driving chip and a second driving chip; an input end of a first HSD power supply circuit is connected with the output port of the master control chip and the positive electrode of the storage battery, and an output end is connected with an input end of the first driving chip; an input end of a second HSD power supply circuit is connected with the output port of the master control chip, and an output end is connected with an input end of the second driving chip; an output end of the first driving chip and an output end of the second driving chip are connected with an input end of the MOSFET module circuit; one end of a freewheeling loop circuit is connected with the positive electrode of the storage battery, and one end is connected with a negative electrode of the storage battery. The power consumption of the driving circuit can be reduced, and the safety and reliability can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of driving circuit, in particular to a driving circuit of a battery management system. BACKGROUND

[0002] At present, most of the 12V low-voltage storage batteries on new energy vehicles are lead-acid batteries, not lithium batteries. Compared with lithium batteries, lead-acid batteries have the disadvantages of large size, large mass, short charge-discharge times and short service life. Therefore, the demand for replacing traditional lead-acid batteries with 12V lithium batteries is increasingly obvious, and the use of lithium batteries requires a 12V battery management system to effectively manage the battery cells to ensure the consistency and service life of the battery cells. A key part of the 12V battery management system is the switching MOSFET module driving circuit, which controls the power supply or no power supply to the outside through the closing and opening of the switching MOSFET module.

[0003] However, the existing switching MOS driving circuit needs to increase more driving chips and latch chips when coping with the increasing charge-discharge current requirements. When entering standby mode (ordinary sleep mode), the MOSFET module needs to remain closed, and the driving chip needs to remain powered, resulting in high static power consumption. When a hardware overcurrent occurs, the overcurrent protection needs to be triggered by the main control chip through current acquisition, which has a long fault response time. At the same time, since the storage battery does not have anti-reverse connection requirements, the freewheeling circuit module has high safety risks. SUMMARY

[0004] Therefore, the embodiment of the present application provides a driving circuit of a battery management system, which can reduce the power consumption loss of the driving circuit in standby mode, reduce the response time of the driving circuit to overcurrent faults, avoid MOSFET damage, and improve the reliability of control.

[0005] The present application is realized by the following technical solutions:

[0006] A driving circuit of a battery management system, the driving circuit comprising:

[0007] a MOSFET module circuit, a latch circuit, an HSD power supply circuit, a freewheeling circuit, a first driving chip and a second driving chip;

[0008] One end of the MOSFET module circuit is connected with a constant voltage B+, and the other end of the MOSFET module circuit is connected with a positive electrode KL30 of the storage battery; the MOSFET module circuit includes a first MOSFET unit and a second MOSFET unit connected in parallel;

[0009] The input end of the latch circuit is connected with the output port of the master control chip and the output end of the overcurrent detection circuit, and the output end of the latch circuit is connected with the control pin of the first driving chip and the second driving chip.

[0010] The HSD power supply circuit comprises a first HSD power supply circuit and a second HSD power supply circuit, the control end of the first HSD power supply circuit is connected with the output port of the master control chip and the positive electrode KL30 of the storage battery, the output end of the first HSD power supply circuit is connected with the power supply pin of the first driving chip, and the output end of the first driving chip is connected with the control end of the first MOSFET unit.

[0011] The control end of the second HSD power supply circuit is connected with the output port of the master control chip, and the output end of the second HSD power supply circuit is connected with the power supply pin of the second driving chip; and the output end of the second driving chip is connected with the control end of the second MOSFET unit.

[0012] One end of the freewheeling circuit is connected with the positive electrode KL30 of the storage battery, and the other end is connected with the negative electrode KL31 of the storage battery.

[0013] In a preferred example of the present application, the first HSD power supply circuit comprises a MOS tube Q4, a diode D2 and a diode D3; the source of the MOS tube Q4 is connected with the constant voltage B+, the gate of the MOS tube Q4 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with the positive electrode KL30 of the storage battery; the gate of the MOS tube Q4 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with the HSD1_EN port of the master control chip, receives the power supply enable signal of the master control chip, and the drain of the MOS tube Q4 is connected with the power supply pin of the first driving chip HSD1.

[0014] In a preferred example of the present application, the second HSD power supply circuit comprises a MOS tube Q5; the source of the MOS tube Q5 is connected with the constant voltage B+, the gate of the MOS tube Q5 is connected with the HSD2_EN port of the master control chip, receives the power supply enable signal output by the master control chip through the HSD2_EN port, and the drain of the MOS tube Q5 is connected with the power supply pin of the second driving chip HSD2.

[0015] In a preferred example of the present application, the latch circuit can further be configured to include a latch SR1; a CLK port of the latch SR1 is connected to an output end of the overcurrent detection circuit, for receiving an overcurrent signal output by the overcurrent detection circuit; a CLR port of the latch SR1 is connected to an output port of the master control chip, for receiving a latch clear signal output by the master control chip; a PRE port of the latch SR1 is connected to an output port of the master control chip, for receiving an off-latch signal of the master control chip before the master control chip enters the sleep state; and a Latch_OUT port of the latch SR1 is connected to the first drive chip HSD1 and the second drive chip HSD2.

[0016] In a preferred example of the present application, in the normal working state, the Latch_OUT port of the latch SR1 outputs a low-level signal to the first drive chip HSD1 and the second drive chip HSD2, and the master control chip controls the closing or opening of the MOSFET module circuit by adjusting the high level or low level of the input end of the HSD power supply circuit.

[0017] In a preferred example of the present application, the freewheeling circuit can further include a MOS tube Q6, a diode D1, a diode D7, and a diode D8; the drain of the MOS tube Q6 is connected to the negative electrode KL31 of the battery, the source of the MOS tube Q6 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the positive electrode KL30 of the battery; the gate of the MOS tube Q6 is connected to the cathode of the diode D7, and the anode of the diode D7 is connected to the output end of the overcurrent detection circuit; the gate of the MOS tube Q6 is connected to the cathode of the diode D8, and the anode of the diode D8 is connected to the output port of the master control chip.

[0018] In a preferred example of the present application, in the normal working state, the MOS tube Q6 is open, and the freewheeling circuit does not work.

[0019] In a preferred example of the present application, when the hardware overcurrent occurs, the freewheeling circuit receives a high-level signal of the OC_CTRL port of the master control chip, the MOS tube Q6 is closed, and the diode D1 works to protect the MOSFET module circuit; when it is needed to open the MOSFET module circuit, the freewheeling circuit receives a high-level signal transmitted by the Diode_CTRL port of the master control chip to protect the drive circuit.

[0020] In a preferred example of the present application, in the standby state, the master control chip enters the sleep state, the first HSD power supply circuit supplies power through the positive electrode KL30 of the battery, and the second HSD power supply circuit does not work.

[0021] In a preferred example of the present application, further provided is that when the battery appears to feed, before the main control chip enters the sleep mode, the main control chip controls the MOSFET module circuit to be disconnected, and transmits a low-level signal to the Sleep_MOS_Lock port of the latch SR1, and the Latch_Lock port of the latch SR1 outputs a high-level signal; after the main control chip enters the sleep mode, the output signal of the Latch_Lock port of the latch SR1 is latched as a high-level signal, the first driving chip HSD1 and the second driving chip HSD2 output a low-level signal to the MOSFET module circuit, and the MOSFET module circuit remains in a disconnected state.

[0022] In summary, compared with the prior art, the technical scheme provided by the embodiment of the present application has at least the following beneficial effects: in the driving circuit of the present application, the latch circuit is directly connected with the output end of the overcurrent detection circuit, in normal operation, the main control chip controls the MOSFET module circuit to be closed or disconnected through the control port; in the standby mode or the sleep mode, when the hardware appears to overcurrent, the latch is directly triggered to control the driving chip to turn off the MOSFET module circuit, without the need to collect signals through the main control chip and then determine whether to turn off the MOSFET module circuit, so that the response time is changed from the mS level to the uS level, the response speed is faster, and the safety factor of the control circuit is improved; in the standby mode, only the first HSD power supply circuit needs to be kept working, so as to reduce the power consumption of the driving circuit; in addition, the freewheeling circuit is arranged between the KL30 and the KL31, which can quickly protect the driving circuit load when the hardware overcurrent appears, without the need to perform a protection action through the main control chip, so as to ensure the safety and reliability of the driving circuit. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The circuit principle diagram of the driving circuit of the battery management system provided by an embodiment of the present application is shown in the figure;

[0024] The reference signs are explained as follows:

[0025] MOSFET module circuit-1, first MOSFET unit-11, second MOSFET unit-12, latch circuit-2, HSD power supply circuit-3, first HSD power supply circuit-31, second HSD power supply circuit-32, freewheeling circuit-4, first driving chip-5, and second driving chip-6. DETAILED DESCRIPTION

[0026] The present embodiment is only an explanation of the present application, and is not a limitation of the present application, and those skilled in the art can make modifications to the present embodiment without creative contribution after reading the present specification, but as long as the modifications are within the scope of the claims of the present application, they are protected by the patent law.

[0027] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0028] In addition, the term "and / or" in the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent three cases of existence of A alone, existence of A and B simultaneously, and existence of B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the associated objects, unless otherwise specified.

[0029] The terms "first", "second", and the like in the present application are used to distinguish the same items or similar items with basically the same function, and it should be understood that there is no logical or time sequence dependence between "first", "second", and "n", and the quantity and execution order are not limited.

[0030] The embodiments of the present application will be described in further detail below with reference to the drawings of the specification.

[0031] In an embodiment of the present application, a circuit schematic diagram of a driving circuit of a battery management system is provided, as shown in Figure 1 The circuit schematic diagram comprises:

[0032] a MOSFET module circuit 1, a latch circuit 2, an HSD power supply circuit 3, a freewheeling circuit 4, a first driving chip 5 and a second driving chip 6, a first MOSFET unit 11, a second MOSFET unit 12, a first HSD power supply circuit 31, and a second HSD power supply circuit 32.

[0033] One end of the MOSFET module circuit 1 is connected with the constant voltage B+, the other end of the MOSFET module circuit 1 is connected with the positive electrode KL30 of the battery, the MOSFET module circuit 1 comprises the first MOSFET unit 11 and the second MOSFET unit 12, the first MOSFET unit 11 and the second MOSFET unit 12 are connected in parallel, the first MOSFET unit 11 (MOS3) and the second MOSFET unit 12 (MOS2) each comprise a plurality of MOS tubes. The control end DRV_MOS1 of the first MOSFET unit 11 is connected with the output end of the first driving chip 5, the control end DRV_MOS2 of the second MOSFET unit 12 is connected with the output end of the second driving chip 6. The constant voltage B+ / B- adopts 12V constant voltage, the closing or opening of the MOSFET module circuit is controlled by the control signal of the driving chip, so as to supply power to the external load (low-voltage controller).

[0034] The input end of the latch circuit 2 is connected with the output port of the master control chip and the output end of the overcurrent detection circuit, the output end of the latch circuit 2 is connected with the first driving chip 5 and the second driving chip 6. Since the latch circuit 2 needs 5V constant voltage for power supply, the driving circuit of the application adopts one latch circuit 2 to control two driving chips, can receive the output signals of the master control chip and the overcurrent detection circuit, and control the working state of the two driving chips according to the needs, so as to realize efficient driving control.

[0035] The input end of the HSD power supply circuit 3 is connected with the positive electrode KL30 of the battery and the master control chip, the output end of the HSD power supply circuit 3 is connected with the driving chip, for supplying power to the driving chip. The HSD power supply circuit 3 comprises the first HSD power supply circuit 31 and the second HSD power supply circuit 32, the control end of the first HSD power supply circuit 31 is connected with the output port of the master control chip and the positive electrode KL30 of the battery, the output end of the first HSD power supply circuit 31 is connected with the power supply pin of the first driving chip 5, the output end of the first driving chip 5 is connected with the control end DRV_MOS1 of the first MOSFET unit 11. The first HSD power supply circuit 31 is used for supplying power to the first driving chip 5.

[0036] The control end of the second HSD power supply circuit 32 is connected with the output port of the master control chip, the output end of the second HSD power supply circuit 32 is connected with the power supply pin of the second driving chip 6; the output end of the second driving chip 6 is connected with the control end DRV_MOS2 of the second MOSFET unit. The second HSD power supply circuit 32 is used for supplying power to the second driving chip 6.

[0037] One end of the freewheeling circuit 4 is connected to the positive electrode KL30 (P+) of the vehicle battery, and the other end is connected to the negative electrode KL31 (P-) of the vehicle battery. When overcurrent occurs in the hardware, the freewheeling circuit 4 plays a role in protecting the MOSFET module circuit.

[0038] In some embodiments, the first HSD power supply circuit 31 includes a MOS tube Q4, a diode D2 and a diode D3; wherein the source of the MOS tube Q4 is connected to the constant power (B+) through the anti-reverse diode D4, the gate of the MOS tube Q4 is connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the positive electrode KL30 of the battery; the gate of the MOS tube Q4 is connected to the cathode of the diode D3, the anode of the diode D3 is connected to the HSD1_EN port of the master chip, and the power supply enabling signal of the master chip is received through the HSD1_EN port, and the drain of the MOS tube Q4 is connected to the power supply pin of the first drive chip HSD1; the power supply of the MOS tube Q4 is controlled, and the control signal is the HSD1_EN power supply enabling signal of the battery positive electrode KL30 and the single-chip microcomputer. After the MOS tube Q4 is closed, the power supply pin of the first drive chip HSD1 is constant, the control pin of the first drive chip HSD1 is pulled down by default, and after the first drive chip HSD1 works, the first MOSFET unit 11 of the MOSFET module circuit 1 will be closed.

[0039] In some embodiments, the second HSD power supply circuit 32 includes a MOS tube Q5; the source of the MOS tube Q5 is connected to the constant power B+ through the anti-reverse diode D4, the gate of the MOS tube Q5 is connected to the HSD2_EN port of the master chip, and the power supply enabling signal of the master chip is received, and the drain of the MOS tube Q5 is connected to the power supply pin of the second drive chip HSD2. The power supply of the MOS tube Q5 is controlled, and the control signal is the HSD2_EN power supply enabling signal of the master chip. After the MOS tube Q5 is closed, the power supply pin of the second drive chip HSD2 is constant, the control pin of the second drive chip HSD2 is pulled down by default, and after the second drive chip HSD2 works, the second MOSFET unit 12 of the MOSFET module circuit 1 will be closed.

[0040] The power supply of the first HSD power supply circuit 31 is controlled by the master control chip and the positive electrode KL30 of the storage battery, and the power supply of the second HSD power supply circuit 32 is controlled by the master control chip. When the external low-voltage controller needs to enter the standby state (normal sleep mode), the master control chip sleeps, and the control signals of the HSD1_EN port and the HSD2_EN port of the master control chip are invalid. However, the positive electrode KL30 of the storage battery can still provide voltage for the first HSD power supply circuit 31, so that the first drive chip HSD1 is normally powered, and the second drive chip HSD2 is not powered. At this time, the first MOSFET unit 11 remains in a closed state, and the second MOSFET unit 12 remains in an open state. In the standby state (normal sleep mode), the master control chip enters a sleep state, the first HSD power supply circuit is enabled by the positive electrode KL30 of the storage battery, and the power supply is normal; the second HSD power supply circuit does not work, and the second drive chip HSD2 cannot be normally powered. At this time, the control pin of the first drive chip HSD1 is internally pulled down, is low effective, and is normally powered, so that the first drive chip HSD1 output DRV_MOS1 still remains high, the first MOSFET unit (MOS3) module remains in a closed state, and the second MOSFET unit (MOS2) module is in an open state. Therefore, in the standby state, the power consumption of the drive can be reduced, and the positive electrode KL30 of the storage battery can still continuously supply power to the outside.

[0041] When the low-voltage controller enters the standby state (normal sleep mode), by disconnecting the power supply of the second HSD power supply circuit 32, unnecessary power consumption can be reduced, and the energy consumption of the entire drive circuit can be reduced. The power supply of the first HSD power supply circuit 31 is retained, which can ensure the normal operation of the external low-voltage controller. Therefore, the power supply strategy of the application can realize energy saving and system stability in the standby state.

[0042] In some embodiments, the latch circuit 2 includes a latch SR1; the CLK port of the latch SR1 is connected with the output end of the overcurrent detection circuit, for receiving the high effective overcurrent signal OC_CTRL output by the overcurrent detection circuit; specifically, forming a rising edge signal on the CLK pin of the latch SR1 will directly output the D pin of the latch SR1 to the Latch_OUT in high level, so that the MOSFET module can be controlled to be disconnected by the driving chip, and the fault response time of the process is in the order of uS, which is faster and safer than the mS level way of software triggered overcurrent. The CLR port of the latch SR1 is connected with the output port of the master control chip, for receiving the latch clear signal HSD_State_CLR output by the master control chip; the PRE port of the latch SR1 is connected with the output port of the master control chip, for receiving the off latch signal Sleep_MOS_LOCK of the master control chip; the Latch_OUT port of the latch SR1 is connected with the first driving chip HSD1 and the second driving chip HSD2. The control truth table of the latch is: / CLR=1, / PRE=1, CLK=0, D=1, Q=hold; / CLR=1, / PRE=1, CLK=rising edge, D=1, Q=1(high level); / CLR=0, / PRE=1, / CLK=x, D=1, Q=0(low level); / CLR=1, / PRE=0, CLK=x, D=1, Q=1(high level).

[0043] In some embodiments, the freewheeling circuit 4 comprises a MOS tube Q6, a freewheeling diode D1, a diode D7 and a diode D8; wherein the drain of the MOS tube Q6 is connected with the negative electrode KL31 of the battery, the source of the MOS tube Q6 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the positive electrode KL30 of the battery; the diode D6 is connected in parallel with the MOS tube Q6, the anode of the diode D6 is connected with the source of the MOS tube Q6, and the cathode of the diode D6 is connected with the drain of the MOS tube Q6; the gate of the MOS tube Q6 is connected with the cathode of the diode D7, the anode of the diode D7 is connected with the output end of the overcurrent detection circuit, and receives the overcurrent signal OC_CTRL of the overcurrent detection circuit; the gate of the MOS tube Q6 is connected with the negative electrode of the diode D8, and the anode of the diode D8 is connected with the output port of the main control chip, and receives the freewheeling circuit control enable signal Diode_CTRL sent by the main control chip. If the hardware overcurrent occurs at this time, the OC_CTRL signal is high level, the MOS tube Q6 is turned on, and the freewheeling diode D1 starts to work to clamp the negative voltage generated by the disconnection of the MOSFET module circuit, so as to avoid the damage of the MOSFET module circuit; if it is needed to actively disconnect the MOSFET module circuit, the main control chip controls Diode_CTRL to be high level, the MOS tube Q6 is turned on, the freewheeling diode D1 starts to work, and then the main control chip controls the MOSFET module circuit to be disconnected, so that the MOSFET module circuit can also be protected.

[0044] In some embodiments, in normal working state, the Latch_OUT port of the latch SR1 outputs a low level signal to the control pins of the first driving chip HSD1 and the second driving chip HSD2, and the master control chip controls the closing or opening of the MOSFET module circuit 1 by controlling the high level or low level of the enable signal of the HSD power supply circuit. According to the external current demand, the first MOSFET unit 11 and the second MOSFET unit 12 can be closed or opened simultaneously, or only one of them can be closed or opened, thereby reducing the power consumption of the battery while meeting the current demand. For example, when a 12V battery is connected, the normal charging and discharging current demand is relatively large, generally 200A@300s, and the peak current can reach 1000A, at this time the first MOSFET unit 11 and the second MOSFET unit 12 need to be closed simultaneously for power supply; when entering the standby state (ordinary sleep mode), the current demand is relatively small, about a few amperes, at this time in order to reduce power consumption, only the first MOSFET unit can be closed. Specifically, the Latch_OUT port of the latch SR1 outputs a low level signal to the first driving chip HSD1 and the second driving chip HSD2, and the master control chip controls the power supply of the first driving chip HSD1 and the second driving chip HSD2 by controlling the high level or low level of the power supply enable signals HSD1_EN and HSD2_EN, and controls the closing or opening of the MOSFET module circuit by controlling the high level or low level of IN1_ON and IN2_ON. When the MOSFET module circuit needs to be closed, the HSD1_EN port and the HSD2_EN port output high level, and the first driving chip HSD1 and the second driving chip HSD2 normally supply power. When the IN1_ON port and the IN2_ON port output low level and the DRV_MOS1 and the DRV_MOS2 are high level, the MOSFET module circuit is closed at this time. When the first MOSFET unit 11 (MOS3) needs to be opened, IN1_ON is high level, HSD1_EN is low level or Latch_OUT is high level; when the second MOSFET unit 12 (MOS2) needs to be opened, IN2_ON is high level, HSD2_EN is low level or Latch_OUT is high level. When in ordinary sleep state, the first MOSFET unit 11 (MOS3) remains closed, and the second MOSFET unit 12 (MOS2) is opened, which can reduce power consumption and can continuously supply power to the external controller.

[0045] In some embodiments, when the battery is fed, before entering the Sleep hibernation mode, the master chip first controls the MOSFET module circuit to be disconnected, and transmits a low-level signal to the Sleep_MOS_Lock port of the latch SR1, and the output signal of the Latch_Lock port of the latch SR1 is a high-level signal; after the master chip hibernation mode, the Latch_Lock port output signal of the latch SR1 is latched as a high-level signal, the first drive chip HSD1 and the second drive chip HSD2 output DRV_MOS1 and DRV_MOS2 remain low, the MOSFET module circuit remains in a disconnected state, and the KL30 is not powered. Even if the battery management system enters the normal working state, because the Latch_Lock port output is high, the MOSFET module circuit remains in a disconnected state. Only when the master chip changes the HSD_State_CLR signal to a low-level signal, the latch state is cleared, that is, the Latch_Lock signal becomes a low-level signal, the MOSFET module circuit can be normally controlled to be closed or disconnected by the master chip.

[0046] It also needs to be explained that when Jump Start is needed, a 24V voltage is applied to the positive electrode KL30 of the battery, the first drive chip HSD1 is normally powered, but the control pin of the first drive chip HSD1 is high, and the first MOSFET unit remains in a disconnected state. Only when the master chip recovers, the level of the HSD_State_CLR port is pulled low, and the Latch_Lock becomes low, the closing or disconnecting of the MOSFET module circuit will be controlled by the master chip. At the same time, when doing Jump Start, even if the external power supply is connected in reverse, at this time, because the MOS tube Q6 is in a disconnected state, the freewheeling diode D1 will not be damaged. In this way, the safety of the Jump Start is increased, and the potential risk to the vehicle electrical system is reduced.

[0047] The driving circuit proposed in the application can significantly reduce the power consumption in the standby mode (ordinary hibernation mode), and the power consumption is lowest in the hibernation mode and the standby mode; on the basis of the overcurrent protection of the master chip, the hardware overcurrent trigger latch function is added, so that the overcurrent fault protection response time is faster, the damage risk of the MOSFET module circuit is reduced, and the control reliability is improved; the freewheeling circuit control is more flexible, and the risk of damage due to misoperation is lower.

[0048] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the system described in the present application is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A drive circuit of a battery management system, characterized by, The drive circuit comprises: MOSFET module circuit, latch circuit, HSD power supply circuit, freewheeling loop circuit, first drive chip and second drive chip; One end of the MOSFET module circuit is connected with the constant power B+, and the other end of the MOSFET module circuit is connected with the positive electrode KL30 of the battery; the MOSFET module circuit comprises a first MOSFET unit and a second MOSFET unit connected in parallel; The input end of the latch circuit is connected with the output port of the main control chip and the output end of the overcurrent detection circuit, and the output end of the latch circuit is connected with the control pin of the first drive chip and the second drive chip; The HSD power supply circuit comprises a first HSD power supply circuit and a second HSD power supply circuit, the control end of the first HSD power supply circuit is connected with the output port of the main control chip and the positive electrode KL30 of the battery, the output end of the first HSD power supply circuit is connected with the power supply pin of the first drive chip, and the output end of the first drive chip is connected with the control end of the first MOSFET unit; wherein the first HSD power supply circuit comprises a MOS tube Q4, a diode D2 and a diode D3; wherein the source of the MOS tube Q4 is connected with the constant power B+, the gate of the MOS tube Q4 is connected with the cathode of the diode D2, the anode of the diode D2 is connected with the positive electrode KL30 of the battery; the gate of the MOS tube Q4 is connected with the cathode of the diode D3, the anode of the diode D3 is connected with the HSD1_EN port of the main control chip, receives the power supply enable signal of the main control chip, and the drain of the MOS tube Q4 is connected with the power supply pin of the first drive chip HSD1; The control end of the second HSD power supply circuit is connected with the output port of the main control chip, the output end of the second HSD power supply circuit is connected with the power supply pin of the second drive chip, and the output end of the second drive chip is connected with the control end of the second MOSFET unit; wherein the second HSD power supply circuit comprises a MOS tube Q5; wherein the source of the MOS tube Q5 is connected with the constant power B+, the gate of the MOS tube Q5 is connected with the HSD2_EN port of the main control chip, receives the power supply enable signal output by the main control chip through the HSD2_EN port, and the drain of the MOS tube Q5 is connected with the power supply pin of the second drive chip HSD2; One end of the freewheeling loop circuit is connected with the positive electrode KL30 of the battery, and one end is connected with the negative electrode KL31 of the battery. In the standby state, the main control chip enters the sleep state, the first HSD power supply circuit supplies power through the positive electrode KL30 of the battery, and the second HSD power supply circuit does not work.

2. The drive circuit of the battery management system according to claim 1, wherein, The latch circuit comprises a latch SR1; the CLK port of the latch SR1 is connected with the output end of the overcurrent detection circuit, for receiving the overcurrent signal output by the overcurrent detection circuit; the CLR port of the latch SR1 is connected with the output port of the main control chip, for receiving the latch clearing signal output by the main control chip; the PRE port of the latch SR1 is connected with the output port of the main control chip, for receiving the latch-off signal of the main control chip before sleep; and the Latch_OUT port of the latch SR1 is connected with the first drive chip HSD1 and the second drive chip HSD2.

3. The drive circuit of the battery management system according to claim 2, wherein, In normal working state, the Latch_OUT port of the latch SR1 outputs low level signal to the first driving chip HSD1 and the second driving chip HSD2, and the master control chip controls the closing or opening of the MOSFET module circuit by adjusting the high level or low level of the input end of the HSD power supply circuit.

4. The drive circuit of the battery management system according to claim 1, wherein, The freewheeling circuit includes a MOS tube Q6, a diode D1, a diode D7 and a diode D8; wherein the drain of the MOS tube Q6 is connected with the negative pole KL31 of the battery, the source of the MOS tube Q6 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the positive pole KL30 of the battery; the gate of the MOS tube Q6 is connected with the cathode of the diode D7, the anode of the diode D7 is connected with the output end of the overcurrent detection circuit; the gate of the MOS tube Q6 is connected with the cathode of the diode D8, the anode of the diode D8 is connected with the output port of the master control chip.

5. The drive circuit of the battery management system according to claim 4, wherein, In normal working state, the MOS tube Q6 is opened, and the freewheeling circuit does not work.

6. The drive circuit of the battery management system according to claim 5, wherein, When the hardware overcurrent occurs, the freewheeling circuit receives the high level signal of the OC_CTRL port of the master control chip, the MOS tube Q6 is closed, and the diode D1 works to protect the MOSFET module circuit; when it is needed to open the MOSFET module circuit, the freewheeling circuit receives the high level signal transmitted by the Diode_CTRL port of the master control chip to protect the driving circuit.

7. The drive circuit of the battery management system according to claim 2, wherein When the battery appears to feed, before the master control chip enters the Sleep hibernation mode, the master control chip controls the MOSFET module circuit to be opened, and transmits low level signal to the Sleep_MOS_Lock port of the latch SR1, and the Latch_Lock port of the latch SR1 outputs high level signal; after the master control chip enters the hibernation mode, the output signal of the Latch_Lock port of the latch SR1 is latched as high level signal, the first driving chip HSD1 and the second driving chip HSD2 output low level signal to the MOSFET module circuit, and the MOSFET module circuit keeps the open state.

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