A method for obtaining power network layout based on directed acyclic graph topology unfolding

Abstract

The application provides a method for obtaining power network layout based on directed acyclic graph topology unfolding, comprising the following steps: step 1, separating unconnected components; step 2, adding a virtual node before each source end, and adding the out-degree of the virtual node to the source end to form a directed acyclic graph with a single starting point; step 3, determining the node serial number, and rearranging the node out-degree according to the node serial number; step 4, performing topology sorting on the directed acyclic graph to obtain a topology sorting list; and step 5, obtaining the layout from the topology sorting. The application introduces a deep analysis method based on directed acyclic graph topology, and innovatively adjusts the out-degree of the directed acyclic graph to generate an optimized topology sorting.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power network simulation, in particular to a method for obtaining power network layout based on topological expansion of directed acyclic graph. BACKGROUND

[0002] In the complex field of power network simulation, the accurate setting of power network model is always the key link to ensure the effectiveness of simulation results. As a highly abstracted physical system, such model focuses on the logical topology of electrical connection, excluding physical implementation details such as PCB material properties, copper foil layout and via structure, so as to focus on the analysis and optimization of electrical performance.

[0003] Although existing technologies, such as Chinese patent CN103500237A, have significantly advanced the process of automatic mapping of distribution network, through logical layout analysis, model segmentation and stripping, and comprehensive layout algorithms (including force-directed, hybrid, dynamic interaction and improved grid routing algorithm), the automatic optimization and clear presentation of distribution network model have been realized. However, in the face of highly integrated application scenarios such as large server boards, the extreme complexity and high-density layout requirements of the power supply circuit pose a serious challenge to existing technologies.

[0004] Specifically, the power network design on large server boards is often complex, and under traditional methods, if the power model and its line layout are not carefully planned and optimized, it is easy to cause the lines to intersect with each other, forming a "labyrinth" in vision, greatly increasing the difficulty of understanding and analysis for engineers. In addition, such disordered layout also hinders engineers' intuitive evaluation of line power distribution and voltage drop performance, thereby affecting the reliability and efficiency of the overall design. SUMMARY

[0005] The purpose of the present application is to provide a layout that avoids intersection as much as possible from a power circuit with complete topological structure, so that the trend of the circuit can be displayed intuitively.

[0006] In order to achieve the above purpose, the present application provides a method for obtaining power network layout based on topological expansion of directed acyclic graph, comprising:

[0007] Step 1, separate unconnected components: according to connectivity, separate the unconnected components in the power circuit to form a plurality of independent directed acyclic graphs, and determine the starting point and the ending point of each independent directed acyclic graph; wherein the starting point is the source end in the power circuit, and the ending point is the load end in the power circuit;

[0008] Step 2, add a virtual node before each source end, and increase the out-degree of the virtual node to the source end to form a directed acyclic graph with a single starting point;

[0009] Step 3, determine node sequence number, rearrange node out-degree according to node sequence number;

[0010] Step 4, topological sort of directed acyclic graph, get topological sort list;

[0011] Step 5, get layout from topological sort: traverse topological sort list, generate power network layout according to sibling, parent-child and parallel relationship between nodes.

[0012] In one embodiment, in step 3, the node sequence number is determined as follows:

[0013] Take the virtual node as the starting point, and determine the node sequence number through the connectivity of each node to the terminal.

[0014] In one embodiment, in step 3, the node sequence number is determined as follows:

[0015] Step 31, select the starting route: select the route in which all nodes have an in-degree of 1 and all nodes in the route are not marked as the starting route, and the route in which each node has only one edge pointing to it is the route in which all nodes have an in-degree of 1.

[0016] Step 32, process the starting route: mark the nodes on the starting route and assign a sequence number to the terminal on the starting route, and all unmarked sequence number endpoints connected to the terminal are assigned the same sequence number as the terminal.

[0017] Step 33, find and process new links:

[0018] Access the nodes on the starting route from the terminal to the source, find nodes with out-degree, and take the found nodes with out-degree as the starting point to repeat the process of steps 31 and 32.

[0019] Step 34, repeat step 33 to continuously find and process new links until all nodes in the directed acyclic graph are accessed and marked with a sequence number.

[0020] In one embodiment, in step 31, if there are multiple routes in which all nodes have an in-degree of 1, then take the route with the smallest sum of all node out-degrees.

[0021] In one embodiment, if there are still multiple routes after taking the route with the smallest sum of all node out-degrees, then take any one of these routes.

[0022] In one embodiment, step 5 includes:

[0023] Step 51, create an endpoint data structure, which includes: component name, row / column information;

[0024] wherein the endpoint is a node containing row / column information, the endpoint name is the node name, and the component name is the name of an external device placed on a PCB, each component generates a node, and the row / column information is used to locate the position of each endpoint on the power network layout;

[0025] In step 52, an endpoint set data structure is created, which contains an endpoint list, a maximum number of components in a child endpoint set, a maximum number of rows in an endpoint set, and a minimum number of rows in an endpoint set.

[0026] The endpoint list is used to store all endpoints in the endpoint set. The maximum and minimum numbers of rows in the endpoint set are the maximum and minimum row information of the endpoints in the endpoint set. A child endpoint set has a parent-child relationship with an endpoint set. The maximum number of components in the child endpoint set is the maximum number of rows of the endpoints in the child endpoint set.

[0027] In step 53, a node position matrix and an endpoint set list are created. The node position matrix is used to record the positions of the nodes. If a position has no node, the node position matrix is empty. The endpoint set list is used to record the order between endpoints.

[0028] The node position is the position of the node on the power network layout.

[0029] In step 54, a common variable row and col are created, which represent the current row and column, respectively. The common variables row and col are both initialized to 0.

[0030] In step 55, the topological sorting list obtained in step 4 is traversed, and nodes are obtained in order. Each node is processed in topological order.

[0031] In step 56, step 55 is repeated until all nodes in the topological sorting list are used.

[0032] In step 57, the row / column information of all endpoints is completed, and the corresponding positions of all nodes are found in the node position matrix.

[0033] In one embodiment, the processing of each node in topological order in step 55 includes the following steps:

[0034] In step 551, if the endpoint set list is empty, then:

[0035] A new endpoint is created, and the node is stored in the new endpoint. The row and col of the node stored in the new endpoint are assigned as the current row and col.

[0036] A new endpoint set is created, and the new endpoint is stored in the new endpoint set.

[0037] Record the endpoint set, and add the endpoint set to a new endpoint set list;

[0038] If the endpoint set list is not empty, go to step 5521:

[0039] Step 5521, determine whether the node in the tail endpoint set is a predecessor node of the current node;

[0040] If the node in the tail endpoint set is a predecessor node, go to step 55211:

[0041] Step 55211, create a new endpoint set, and create a new endpoint, store the node in the new endpoint, store the new endpoint in the new endpoint set, and assign values to the row and column of the endpoint set;

[0042] Record the endpoint set, and add the endpoint set to a new endpoint set list;

[0043] If the node in the tail endpoint set is not a predecessor node, go to step 55212:

[0044] Step 55212, determine whether the node in the tail endpoint set is a parallel node;

[0045] If it is a parallel node, then: create a new endpoint, store the parallel node in the new endpoint, assign the column number col and the row number row+1 to the new endpoint, update row, store the node in the node position matrix, store the new endpoint in the tail endpoint set, which is the last element of the endpoint set list, and the endpoint set list follows the stack principle of first-in last-out;

[0046] If it is not a parallel node, then: pop the tail element from the endpoint set list, update the endpoint set to the tail element of the new endpoint set list, and re-execute step 55212 to determine whether the node in the updated tail endpoint set is a parallel node.

[0047] In one embodiment, in step 55211, assigning values to the row and column of the endpoint set includes:

[0048] If the maximum number of rows of components contained in the sub-endpoint of the previous endpoint set exists, assign the row of the endpoint set as the maximum number of rows of components contained in the sub-endpoint of the previous endpoint set plus 1, and store the node in the endpoint in the node position matrix;

[0049] If the previous endpoint set does not have a sub-endpoint, assign the row as the minimum row number of the endpoint of the previous endpoint set, and store the node in the endpoint in the node position matrix.

[0050] The method for obtaining power network layout based on directed acyclic graph topology expansion proposed by the application has the following significant beneficial effects compared to traditional technologies:

[0051] 1. High practicality and stability: Unlike traditional methods that rely on genetic algorithms to determine positions by passing numerical values through nodes, the method of the application does not require setting and adjusting any "seed" parameters. In traditional genetic algorithms, these "seeds" are used as numerical markers during traversal and backtracking processes, and their selection and adjustment are not only complex but also lack universality in different cases, often requiring multiple trials. The method of the application, which is based directly on the topology of DAG for sorting and expansion, effectively avoids this cumbersome process, ensuring the practicality and stability of the method, and can stably output high-quality power network layouts in different application scenarios.

[0052] 2. Wide applicability and reusability: The application discards the layout method that relies on the physical properties of the model and instead takes the topological structure of the graph as the core. This change makes the method no longer limited by the physical properties of specific models (such as PCB materials, sizes, shapes, etc.), enabling it to be applied flexibly to any power network layout task with similar topological structures across different fields and scenarios. This feature greatly enhances the reusability and universality of the method.

[0053] 3. Optimized layout effect: For complex power supply circuit designs on large server boards, the sorting method proposed by the application can minimize line crossing through detailed topological analysis and sorting expansion. Compared to traditional methods that do not undergo topological optimization and adjustment, the application significantly improves the layout clarity and aesthetics of the power network, providing engineers with a more intuitive and easily assessable circuit layout scheme. At the same time, this optimized layout also helps to improve the electrical performance of the circuit, such as reducing voltage drop and improving power transmission efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 The figure is a flowchart of the method for obtaining power network layout based on directed acyclic graph topology expansion according to an embodiment of the application.

[0055] Figure 2 The figure is a schematic diagram of adding a virtual node and increasing the out-degree of the virtual node to the source end according to an embodiment of the application.

[0056] Figure 3 The figure is a directed acyclic graph after adding a virtual node and increasing the out-degree of the virtual node to the source end according to an embodiment of the application.

[0057] Figure 4 The figure reveals the starting line of the directed acyclic graph according to an embodiment of the application.

[0058] Figure 5A new link after starting a route in a directed acyclic graph in an embodiment of the present application is disclosed.

[0059] Figure 6 A diagram for all nodes in a directed acyclic graph being numbered in an embodiment of the present application.

[0060] Figure 7 A diagram for an end point set and a relationship between an end point and a node / component.

[0061] Figure 8 A specific flowchart for step 5 in a method for obtaining a power network layout based on a topology expansion of a directed acyclic graph in an embodiment of the present application.

[0062] Figure 9 A power network layout obtained by a method for obtaining a power network layout based on a topology expansion of a directed acyclic graph not using the present application.

[0063] Figure 10 A power network layout obtained by a method for obtaining a power network layout based on a topology expansion of a directed acyclic graph using the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present application clearer and more apparent, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0065] In view of the above background, the present application is committed to make a breakthrough on the basis of the prior art, by introducing a depth analysis method based on directed acyclic graph (DAG) topology, and innovatively adjusting the out-degree of DAG to generate an optimized topology sorting. This sorting strategy not only can effectively guide the layout expansion process of the power network, but also can maximize the reduction or even avoid the line crossing phenomenon, ensuring the clear display and efficient analysis of the power network. Finally, the present research aims to provide a stable and reliable power network layout solution for complex application scenarios such as large server boards, significantly improving the design quality and engineering efficiency.

[0066] As shown in Figure 1 , the present application proposes a method for obtaining a power network layout based on a topology expansion of a directed acyclic graph, comprising:

[0067] Step 1, according to connectivity, separate the unconnected components in the power circuit to form a plurality of independent directed acyclic graphs, and determine the starting point and the ending point of each independent directed acyclic graph. Wherein, the starting point is the source end in the power circuit, and the ending point is the load end in the power circuit.

[0068] Step 2, add a virtual node before each source end and increase the out-degree of the virtual node to the source end, forming a directed acyclic graph with a single starting point, see Figure 2 .

[0069] It should be understood that increasing the out-degree of the virtual node to the source end is to increase the number of edges from the virtual node pointing to the source end. This step can also be understood as establishing an edge between the source end node and the virtual node, which points from the virtual node to the source end.

[0070] Step 3, determine the node sequence number, rearrange the node out-degree according to the node sequence number.

[0071] Specifically, the sequence number of the target node for each node's out-degree is rearranged in order of size. This out-degree order will directly affect the order of the topological sort, thus affecting the final layout effect. Through this process, the nodes are assigned a sequence number that reflects their relative position in the "dependency relationship" in the graph. At the same time, according to these sequence numbers, the out-degree list of the nodes (i.e., the information of which nodes each node points to) can be reorganized or sorted, so that these information can be more efficiently utilized in subsequent processing.

[0072] Step 4, topological sorting of the directed acyclic graph to obtain a topological sorting list.

[0073] Step 3 provides the necessary preprocessing and preparation for the topological sorting of Step 4, including the assignment of node sequence numbers and the rearrangement of out-degree lists. These preprocessing steps ensure that the topological sorting algorithm can be efficiently executed and correctly generate a linear sequence reflecting the dependency relationships of nodes in the graph. Without the preprocessing of Step 3, the topological sorting of Step 4 may become more complex, inefficient, and even unable to execute correctly in some cases.

[0074] Step 5, traverse the topological sorting list and generate the power supply network layout according to the sibling, parent-child and parallel relationships between nodes.

[0075] Further, in Step 3, determining the node sequence number includes:

[0076] Starting from the virtual node, the node sequence number is determined through the connectivity of each node to the load end.

[0077] Specifically, in Step 3, determining the node sequence number includes the following steps:

[0078] Step 31, select a starting route: select a route where the in-degree of each node in the route is 1 and all nodes in the route are unmarked as the starting route, where the in-degree of each node in the route is 1.

[0079] Figure 3 A specific embodiment is shown as follows:Figure 3 As shown, the routes that meet the selection condition in step 31 of the starting route are:

[0080] VituralNode->G1->L13->R37->U11;

[0081] VituralNode->G1->L14->R89->U12;

[0082] VituralNode->G1->L16->R90->U14;

[0083] VituralNode->G1->L15->R88->U13;

[0084] VituralNode->G1->L11->R85->U19;

[0085] VituralNode->G1->L12->R86->U10.

[0086] Therefore, step 31 of selecting the starting route further comprises: if there are multiple routes with the in-degree of the nodes being 1, then taking the route with the minimum sum of the out-degree of all nodes in the multiple routes with the in-degree of the nodes being 1.

[0087] Further, if there are still multiple routes after taking the route with the minimum sum of the out-degree of all nodes in the multiple routes with the in-degree of the nodes being 1, then taking any one of the routes.

[0088] Step 32, processing the starting route: marking the nodes on the starting route, and assigning a serial number to the sink node on the starting route (starting from 1, the serial number of U11 is 1), and the serial numbers of all the unmarked serial number endpoints connected to the sink node are assigned the same serial number as the sink node, see Figure 4 .

[0089] It should be understood that the nodes marked in the present application are the nodes marked with gray in Figure 4 , and the nodes not marked with gray are the nodes not marked. Usually, red is also selected to represent that the node has been used. The color of the node is just a mark, which is a common method of graph processing.

[0090] Step 33, finding and processing new links:

[0091] Accessing the nodes on the starting route from the sink node to the source node, finding the nodes with out-degree, and taking the found nodes with out-degree as the starting point to repeat the process of step 31 and step 32. For example, Figure 4As shown, the access U11, R87 nodes have no out-degree, L13 node exists out-degree. Then take L13 node as the starting point, return to execute step 31, get new link: L13->Q28->L18->J5, see Figure 5 . And execute step 32 on the new link, mark J5 as serial number 2, and mark the connection point serial number (that is, all the serial numbers of the unmarked serial number endpoints connected to the load terminal are marked with the same serial number as the load terminal).

[0092] Step 34, repeat step 33 to continuously discover and process new links until all nodes in the directed acyclic graph are accessed and marked with serial numbers, see Figure 6 .

[0093] Further, step 5 is described in detail.

[0094] Step 5 includes:

[0095] Step 51, create an endpoint data structure, which includes: component name, row / column information.

[0096] Wherein, the endpoint is a node containing row / column information, the endpoint can be understood as (node+row / column information), and the endpoint name is the node name. The component name is the name of the external device placed on the PCB, and each component generates a node. The row / column information is used to locate the position information of each endpoint on the layout of the power network.

[0097] It should be understood that the component can be considered simply as a node. Generally, positions are reserved on the PCB for external devices, which are referred to as assemblies. In this application, the node is a reserved position (Component) on the PCB, which includes all corresponding pins within the position and its range. Simply put, the assembly (Assembly) is placed on these positions (Component). The row / column information is the position information of the endpoint in the layout, and the directed acyclic graph is only a basic structure, which only describes the connection relationship among the nodes and does not have position information. We can give each endpoint position / index information in the form of a matrix.

[0098] Step 52, create an endpoint set data structure, which includes: endpoint list, maximum number of components contained in the sub-endpoint set, maximum number of rows in the endpoint set, minimum number of rows in the endpoint set.

[0099] As Figure 7As shown in the table, each endpoint set contains multiple endpoints, and the endpoint list is used to store all endpoints in the endpoint set. The maximum row number of the endpoint set and the minimum row number of the endpoint set are the maximum and minimum row information of the endpoints contained in the endpoint set. The child endpoint set has a parent-child relationship with an endpoint set, and the maximum component row number of the child endpoint set is the maximum row number of the endpoint in the child endpoint set. In a popular way, the child endpoint set is the son endpoint having a parent-child relationship with the endpoint set, which is called a child node in topology. The parent-child relationship is explained as follows: the current flows from the parent endpoint to the child endpoint.

[0100] Step 53, creating a node position matrix and an endpoint set list. The node position matrix is used to record the node position, and if a position has no node, the node position matrix is empty. The endpoint set list is used to record the order between endpoints.

[0101] Wherein, the node position is the position of the node on the layout of the power network.

[0102] Step 54, creating common variables row and col, row and col represent the current row and column respectively, and the common variables row and col are initialized to 0, that is, (row, col) is initialized to (0, 0)

[0103] Step 55, traversing the topological sorting list obtained in step 4, obtaining nodes in order, and processing each node in topological order.

[0104] Step 56, repeating step 55 until all nodes in the topological sorting list are used.

[0105] Step 57, completing the row / column information of all endpoints to find the corresponding position of all nodes in the node position matrix. Once the row / column information (i.e. the position information) of a given node is given, we can quickly locate the exact position of the node in the "node position matrix".

[0106] In step 4, we obtain a node list by topological sorting of a "directed acyclic graph" (here, topological sorting is a method in topology). Step 55 obtains nodes in the order of the node list, and generates endpoints and endpoint sets according to the rules. One endpoint corresponds to one node, and additional row and column information is added to the node. In this application, the endpoint can also be understood as adding row and column information to the node. Specifically, step 55 processes each node in topological order, including the following steps:

[0107] Step 551, if the endpoint set list is empty, then:

[0108] Creating a new endpoint and storing the node in the new endpoint, and assigning the row and column of the node stored in the new endpoint to the current row and column row, col;

[0109] create a new endpoint set, and store the new endpoint into the new endpoint set;

[0110] record the endpoint set, and add the endpoint set into the new endpoint set list;

[0111] Step 552, if the endpoint set list is not empty, go to step 5521:

[0112] Step 5521, judge whether the node in the tail endpoint set is the predecessor node of the current node; the predecessor node is the previous node of the current node which has been visited;

[0113] If the node in the tail endpoint set is the predecessor node, go to step 55211:

[0114] Step 55211, create a new endpoint set, and create a new endpoint, store the node into the new endpoint, store the new endpoint into the new endpoint set, and assign values to the row and column of the endpoint set;

[0115] record the endpoint set, and add the endpoint set into the new endpoint set list;

[0116] If the node in the tail endpoint set is not the predecessor node, go to step 55212:

[0117] Step 55212, judge whether the node in the tail endpoint set is a parallel node;

[0118] If it is a parallel node, then: create a new endpoint, store the parallel node into the new endpoint, assign the column number of the new endpoint as col, and the row number as row+1, update row, store the node into the node position matrix, store the new endpoint into the tail endpoint set, the tail endpoint set is the last element of the endpoint set list, and the endpoint set list follows the stack principle of first-in last-out;

[0119] If it is not a parallel node, then:

[0120] push out the tail element of the endpoint set list, which means removing an element from the end of the endpoint set list, and the tail element is a tail endpoint set;

[0121] update the endpoint set (i.e. the endpoint set which is judged as not empty in step 552) as the tail element of the new endpoint set list after pushing out the tail element;

[0122] re-execute step 55212 to judge whether the node in the updated tail endpoint set is a parallel node.

[0123] The tail element is pushed out: if a stack (first-in last-out) stores elements A->B->C->D, four elements, the operation of removing (last-in first-out, pop) D is to push out, which can also be called out of stack.

[0124] Further, in step 55211, the row and column of the endpoint set are assigned values, including:

[0125] If the maximum number of components contained in the sub-endpoint of the previous endpoint set exists, the row of the endpoint set is assigned a value of the maximum number of components contained in the sub-endpoint of the previous endpoint set plus 1, and the nodes in the endpoint are stored in the node position matrix;

[0126] If the previous endpoint set does not have a sub-endpoint, the row is assigned a value of the minimum row number of the endpoint of the previous endpoint set, and the nodes in the endpoint are stored in the node position matrix.

[0127] It should be understood that, unless otherwise explained, "row / column" and "row and column" in this application can mean row and column, or row or column.

[0128] Taking Figure 6 and Figure 8 as examples, step 5 is exemplified.

[0129] VituralNode G1 L13 R87 U11 Q28 L14 Q18 R89 U12 L16 Q20 R90 U14 L15Q31L18 J5 R88 U13 L11 R85 U9 Q25 L12 Q16 L19 J7 R86 U10 as Figure 6 in the topological sorting.

[0130] VituralNod e , for the case where the endpoint set list is empty.

[0131] VituralNode->G1 / / create a new endpoint, for the case where the endpoint set list is empty.

[0132] VituralNode->G1->L13 / / as above, for the case where the endpoint set list is not empty, and the node in the tail endpoint set is a predecessor node.

[0133] VituralNode->G1->L13->R87 / / as above, for the case where the endpoint set list is not empty, and the node in the tail endpoint set is a predecessor node.

[0134] VituralNode->G1->L13->R87->U11 / / as above, for the case where the endpoint set list is not empty, and the node in the tail endpoint set is a predecessor node.

[0135] VituralNode -> G1 -> L13 -> R87 -> U11 / / 3_2 roll back to L13

[0136] VituralNode -> G1 -> L13 -> R87 -> U11 / / 3_2 roll back to L13

[0137] -> Q28 -> L18 -> J5 / / create new endpoint

[0138] VituralNode -> G1 -> L13 -> R87 -> U11 / / 3_2 roll back to L13

[0139] -> Q28 -> L18 -> J5 / / create new endpoint

[0140] -> L14 / / 3_2 roll back to G1

[0141] For the case of non-empty endpoint set list, and the tail endpoint set node is not a predecessor node and is not a parallel node, the final rollback is transferred to the G1 node. This step is the same, L14 is not the successor node of J5, L18, Q28, L13, and G1 is, so J5, L18, Q28, L13 are pushed out in turn, and L14 is added after G1.

[0142] VituralNode -> G1 -> L13 -> R87 -> U11 / / 3_2 roll back to L13

[0143] -> Q28 -> L18 -> J5 / / create new endpoint

[0144] -> L14 -> Q13

[0145] At this time, for the case of non-empty endpoint set list, and the tail endpoint set node is a predecessor node.

[0146] There are no parallel endpoints in this case, so no demonstration is made.

[0147] The graph layout obtained by not taking the virtual node as the starting point and determining the endpoint sequence number through the connectivity of each endpoint to the load end is as follows Figure 9As shown, there are many intersections between the lines Figure 9 After optimization by the technical solution, the layout of the obtained power network is as shown in Figure 10 It can be seen that in the newly obtained power network layout, the connected lines of the same terminal are different from before, and the power network layout maximally reduces the intersection of lines.

[0148] It should be understood that the construction step is to access all power components and find different power components with the same power network, and each power component generates a node, and the same power network between them will generate a connection. Figure 9 and Figure 10 The block represents the power component, and the connection line represents the same power network between the power components.

[0149] The method for obtaining a power network layout based on a directed acyclic graph topology expansion proposed by the present application has the following significant beneficial effects compared to traditional technologies:

[0150] 1. High practicality and stability: Unlike the method of determining the position by passing values through nodes using genetic algorithms, the method of the present application does not need to set and adjust any "seed" parameters. In traditional genetic algorithms, these "seeds" are used as value markers in the traversal and backtracking process, and their selection and adjustment are not only complex but also lack universality in different cases, often requiring multiple trials. The present application directly sorts and expands based on the topology of DAG, effectively avoiding this tedious process and ensuring the practicality and stability of the method, which can stably output high-quality power network layouts in different application scenarios.

[0151] 2. Wide applicability and reusability: The present application discards the layout method that relies on the physical properties of the model and instead takes the topological structure of the graph as the core. This change makes the method no longer limited by the physical properties of specific models (such as PCB materials, sizes, shapes, etc.), so it can be applied to any power network layout task with similar topological structures across different fields and scenarios. This feature greatly improves the reusability and universality of the method.

[0152] 3. Optimized layout effect: For complex power supply circuit designs on large server boards, the sorting method proposed by the present application can maximize the reduction of line intersections through fine topological analysis and sorting expansion. Compared to traditional methods that do not undergo topological optimization and adjustment, the present application significantly improves the layout clarity and aesthetics of the power network, providing engineers with a more intuitive and easy-to-evaluate circuit layout scheme. At the same time, this optimized layout also helps to improve the electrical performance of the circuit, such as reducing voltage drop and improving power transmission efficiency.

[0153] Although the above-described methods are illustrated and described as a series of acts for simplicity, it is to be understood that the methods are not limited by the order of acts, as some acts can occur in different orders or concurrently with other acts from that depicted and described herein. In one or more embodiments, the methods can include additional acts not disclosed and described herein.

[0154] The above-described embodiments are merely intended to further illustrate the present application, but are not intended to limit the present application in other forms, and the present application can have other various embodiments. Those skilled in the art can make various corresponding modifications and changes according to the present application without departing from the spirit and essence of the present application, and these corresponding modifications and changes should fall within the protection scope of the present application.

Claims

1. A method for obtaining power network layout based on topology expansion of a directed acyclic graph, characterized in that, include: Step 1, Separate disconnected components: Based on connectivity, separate the disconnected components in the power supply circuit to form multiple independent directed acyclic graphs, and determine the start and end points of each independent directed acyclic graph; where the start point is the source terminal in the power supply circuit, and the end point is the carrier terminal in the power supply circuit. Step 2: Add a virtual node before each source end and increase the out-degree of the virtual node to the source end to form a directed acyclic graph with a single starting point. Step 3: Determine the node sequence number and rearrange the out-degree of the nodes according to the node sequence number. The node sequence number is determined by starting from the virtual node and determining the node sequence number through the connectivity of each node to the carrier. Step 4: Perform a topological sort on the directed acyclic graph to obtain a topological sort list; Step 5, Obtain the layout from the topology sort: Traverse the topology sort list and generate the power network layout based on the sibling, parent-child, and parallel relationships between nodes.

2. The method for obtaining power network layout based on topology expansion of a directed acyclic graph according to claim 1, characterized in that, Step 3, determining the node sequence number, includes the following steps: Step 31, Select the starting route: Take the route with all nodes having an in-degree of 1 and all nodes in the route being unmarked as the starting route. The route with all nodes having an in-degree of 1 means that each node in the route has only one edge pointing to it. Step 32, Process the starting route: Mark the nodes on the starting route and assign a serial number to the carrier on the starting route. All unmarked endpoints connected to the carrier are marked with the same serial number as the carrier. Step 33, Find and process new links: From the carrier end, access the nodes on the starting route from the source end, find the nodes with out-degree, and repeat the process of steps 31 and 32 starting from the found nodes with out-degree. Step 34: Repeat step 33 to continuously discover and process new links until all nodes in the directed acyclic graph have been visited and marked with an index.

3. The method for obtaining power network layout based on topology expansion of a directed acyclic graph according to claim 2, characterized in that, In step 31, when selecting the starting route: if there are multiple routes with all nodes having an in-degree of 1, then select the route with the smallest sum of all nodes' out-degrees among these routes with all nodes having an in-degree of 1.

4. The method for obtaining power network layout based on topology expansion of a directed acyclic graph according to claim 3, characterized in that, If, among these multiple lines where the in-degree of each node is 1, the line with the smallest sum of the out-degrees of all nodes still results in multiple lines, then any one of these lines can be chosen.

5. The method for obtaining power network layout based on topology expansion of a directed acyclic graph according to claim 1, characterized in that, Step 5 includes: Step 51: Create an endpoint data structure, which includes: component name and row / column information; In this context, an endpoint is a node containing row / column information, the endpoint name is the node name, the component name is the name of the external device placed on the PCB, each component generates a node, and the row / column information is used to locate the position information of each endpoint on the power network layout; Step 52: Create an endpoint set data structure, which includes: an endpoint list, the maximum number of rows in the components of a sub-endpoint set, the maximum number of rows in the endpoint set, and the minimum number of rows in the endpoint set. Each endpoint set contains multiple endpoints. The endpoint list is used to store all endpoints in the endpoint set. The maximum number of rows and the minimum number of rows in the endpoint set are the maximum and minimum row information of the endpoints contained in the endpoint set. A sub-endpoint set has a parent-child relationship with an endpoint set. The maximum number of rows of components in a sub-endpoint set is the maximum number of rows of endpoints in the sub-endpoint set. Step 53: Create a node position matrix and an endpoint set list. The node position matrix is ​​used to record node positions. If a position has no node, the node position matrix is ​​empty. The endpoint set list is used to record the order between endpoints. Wherein, the node position refers to the position of the node on the power network layout; Step 54: Create public variables row and col, where row and col represent the current row and column, respectively, and initialize both public variables row and col to 0; Step 55: Traverse the topological sort list obtained in Step 4, obtain the nodes in order, and process each node according to the topological sort. Step 56: Repeat step 55 until all nodes in the topological sort list have been used; Step 57: Complete the row / column information for all endpoints to find the corresponding position of all nodes in the node position matrix.

6. The method for obtaining power network layout based on topology expansion of a directed acyclic graph according to claim 5, characterized in that, Step 55, which processes each node according to its topology, includes the following steps: Step 551, if the endpoint set list is empty, then: Create a new endpoint, store the node in the new endpoint, and assign the row and column of the node stored in the new endpoint to the current row and column. Create a new endpoint set and store the new endpoints in the new endpoint set; Record the endpoint set and add it to the new endpoint set list; Step 552: If the endpoint set list is not empty, proceed to step 5521: Step 5521: Determine whether the nodes in the tail endpoint set are the predecessor nodes of the current node; If the nodes in the tail endpoint set are predecessor nodes, then proceed to step 55211: Step 55211: Create a new endpoint set and create new endpoints. Store the nodes in the new endpoints and store the new endpoints in the new endpoint set. Assign values ​​to the rows and columns of the endpoint set. Record the endpoint set and add it to the new endpoint set list; If the nodes in the tail endpoint set are not the predecessor nodes, proceed to step 55212: Step 55212: Determine whether the nodes in the tail endpoint set are parallel nodes; If it is a parallel node, then: create a new endpoint, store the parallel node in the new endpoint, assign the column number of the new endpoint to col, assign the row number to row+1, update row, store the node in the node position matrix, and store the new endpoint in the tail endpoint set. The tail endpoint set is the last element of the endpoint set list, and the endpoint set list follows the first-in-last-out stack principle. If it is not a parallel node, then: the endpoint set list is delimited by the tail element, the endpoint set is updated to the tail element of the new endpoint set list, and step 55212 is re-executed to determine whether it is a parallel node for the nodes in the updated tail endpoint set.

7. The method for obtaining power network layout based on topology expansion of a directed acyclic graph according to claim 6, characterized in that, In step 55211, values ​​are assigned to the rows and columns of the endpoint set, including: If the maximum number of rows of components contained in the child endpoints of the previous endpoint set exists, then the number of rows in the endpoint set is assigned the value of the maximum number of rows of components contained in the child endpoints of the previous endpoint set plus 1, and the nodes in the endpoints are stored in the node position matrix. If the previous endpoint set does not have child endpoints, the row is assigned the minimum row number of the endpoints in the previous endpoint set, and the nodes in the endpoint are stored in the node position matrix.

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