Current-aperture vertical electron transistors and methods of making the same

Abstract

The application belongs to the field of semiconductor devices, and provides a current aperture vertical electron transistor and a preparation method thereof. The current aperture vertical electron transistor comprises a substrate, a drain located on the lower surface of the substrate, an N-type drift region located on the upper surface of the substrate, and a first layer and a second layer of current blocking layers located on both sides of the N-type drift region and adjacent to the N-type drift region, a channel region located on the N-type drift region and at least a part of the second layer of current blocking layers, a barrier layer and a P-type layer located on the channel region, a source located on the second layer of current blocking layers and adjacent to the channel region, the barrier layer and the P-type layer, a gate located on the P-type layer, and a passivation layer located between the source and the gate. The current aperture vertical electron transistor and the preparation method thereof improve the energy band structure, increase the threshold voltage, enhance the gate control ability, improve the transconductance, optimize the electric field distribution, increase the breakdown voltage, reduce the on-resistance and improve the output characteristics.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor devices, and particularly relates to a current aperture vertical electron transistor and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) as a semiconductor material, has the characteristics of wide band gap and high electron mobility, is widely used in the manufacture of high-frequency, high-power electronic devices. Its excellent performance makes GaN devices in 5G communication, LED lighting, power electronics, etc. Field of excellent, has great application potential. With the continuous progress of technology, GaN material is becoming an important basis for the next generation of electronic devices.

[0003] Lateral structure AlGaN / GaN HEMT is the main development direction of gallium nitride devices today, but it is not conducive to device miniaturization and packaging. In view of the shortcomings of AlGaN / GaN lateral devices, the current aperture vertical electron transistor (CAVET) applies a source-drain electric field in the vertical direction, reducing the device's demand for a large area in the lateral direction, conforming to the development trend of chip miniaturization, and reducing packaging difficulty and cost.

[0004] The gallium nitride-based CAVET device modulates the electric field distribution in the buffer layer by adopting a super-junction structure, and obtains a uniform electric field, thereby improving the breakdown voltage.

[0005] Traditional gallium nitride-based CAVET devices are depletion type, that is, in the actual application process, a negative voltage must be continuously applied to the gate to realize device turn-off, which will lead to increased system cost and reduced reliability. The gallium nitride-based enhancement-mode CAVET device is closed when the gate voltage is zero, and is only turned on when a positive gate voltage is applied, thereby reducing the complexity of gate driving.

[0006] Increasing the threshold voltage means that these devices are less likely to be mis-triggered or affected when facing electromagnetic interference, thereby improving the stability and anti-interference ability of the system, having a fault protection function, and being more suitable for different working environments and needs. Therefore, it is of great significance to increase the threshold voltage of the gallium nitride-based enhancement-mode CAVET device.

[0007] Reducing the on-resistance means that in the on-state of the device, the current can be transmitted more effectively, reducing energy loss, which helps to improve the stability and reliability of the CAVET device, prolong the service life of the CAVET device, and also improve the switching speed and working frequency of the CAVET device, making the CAVET device more suitable for high-frequency and high-speed application scenarios. Therefore, it is of great significance to reduce the on-resistance of the CAVET device. SUMMARY

[0008] To solve at least one aspect of the above problems and defects in the prior art, embodiments of the present application provide a novel current aperture vertical electron transistor (CAVET) and a preparation method thereof, wherein the current aperture vertical electron transistor and the preparation method thereof improve the energy band structure, increase the threshold voltage; enhance the gate control ability, increase the transconductance; optimize the electric field distribution, increase the breakdown voltage; reduce the on-resistance, and improve the output characteristics.

[0009] The current aperture vertical electron transistor (CAVET) and the preparation method thereof provided by the embodiments of the present application have at least one or part of at least one of the following advantages:

[0010] 1) Based on the addition of a P-type cap layer under the gate, a P-type gate groove is formed by etching the barrier layer and filled with the P-type cap layer, which compensates for the decrease in transconductance caused by the addition of the P-type cap layer, and better realizes the enhancement function, that is, a larger positive threshold voltage is obtained;

[0011] 2) By locating the passivation layer between the source and the gate on a part of the end surface of the barrier layer where the P-type gate groove is not set, that is, increasing the length of the protruding part of the source towards the gate, the contact area between the source and the barrier layer is increased, the electron concentration of the contact interface is increased, the channel electron concentration is increased, the device transconductance and breakdown voltage are improved, the output current density loss caused by etching the barrier layer is compensated, the on-resistance is reduced, and the output characteristics are improved;

[0012] 3) By performing concentration stratified doping on the plurality of N column drift layers of the N column, that is, the doping concentration distributed in sequence from the upper surface of the substrate decreases in sequence, the output current density loss caused by etching the barrier layer is further compensated, the on-resistance is reduced, and the output characteristics are improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] These and / or other aspects and advantages of the present application will become apparent and readily understood from the following description, taken in connection with the accompanying drawings, in which:

[0014] Figure 1 A structural schematic diagram of a current aperture vertical electron transistor according to an embodiment of the present application;

[0015] Figures 2 to 16 A flowchart schematic diagram of a preparation method of a current aperture vertical electron transistor according to another embodiment of the present application;

[0016] Figure 17 A transfer characteristic curve diagram of the current aperture vertical electron transistor of Comparative Example 1, Example 1, Example 2 and Example 3 is shown;

[0017] Figure 18 The breakdown characteristic curves of the current aperture vertical electron transistors of Comparative Example 1 and Examples 1, 2 and 3 are shown.

[0018] Figure 19 A comparison graph showing the breakdown voltage versus on-resistance of the current aperture vertical electronic transistors of Comparative Example 1 and Examples 1, 2, and 3 is presented.

[0019] Figure 20 The output characteristic curves of the current aperture vertical electronic transistors of Examples 4 and 2 are shown.

[0020] Figure 21 The diagram shows a comparison of the gate leakage current of the current aperture vertical electronic transistors of Comparative Example 2, Example 5, and Example 6 at Vds = 0V;

[0021] Figure 22 The output characteristic curves of the current aperture vertical electronic transistors in Comparative Example 2, Examples 5, and 6 are shown when Vg = 4V.

[0022] Figure 23 The transconductance diagrams of the current aperture vertical electronic transistors of Comparative Example 2, Example 5, and Example 6 are shown when Vds = 5V. Specific implementation methods

[0023] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0024] See Figure 1 This diagram illustrates a schematic structure of a current aperture vertical electron transistor 100 according to an embodiment of the present invention, wherein the current aperture vertical electron transistor is a group III nitride semiconductor-based heterojunction device. In the following description, the arrangement and position of each component of the current aperture vertical electron transistor 100 will be described based on substrate 110.

[0025] Specifically, the current aperture vertical electron transistor 100 includes the following components: substrate 110, drain 121, N-type drift region 130, first current blocking layer 140, second current blocking layer 150, channel layer 160, barrier layer 170, P-type layer 180, passivation layer 190, drain 121, source 122, gate 123, etc.

[0026] In one embodiment, the substrate 110 is made of GaN, and has a thickness of 0.6 μm to 1.2 μm and a doping concentration of 5 x 1018cm"3to 5 x 1020cm"3. Preferably, the substrate 110 has a thickness of 1 μm and a doping concentration of 5 x 1018cm"3. 17 cm -3 ~ 5 x 1020cm"3. 18 cm -3 Preferably, the substrate 110 has a thickness of 1 μm and a doping concentration of 5 x 1018cm"3. 18 cm -3 Alternatively, the substrate 110 can be made of silicon (Si), silicon carbide (SiC), sapphire or other suitable materials.

[0027] Specifically, the drain 121 is located on the lower surface of the substrate 110 and forms an ohmic contact with the substrate 110. That is, the drain 121 is disposed on the surface of the substrate 110 that faces away from the N-type drift region 130 and the first current blocking layer 140. Figure 1

[0028] Further, the N-type drift region 130 is located on the upper surface of the substrate 110, and the first current blocking layer 140 is located on both sides of the N-type drift region 130 and is adjacent to the N-type drift region 130. The material of the N-type drift region 130 can be GaN or SiC, and the second current blocking layer 150 has a thickness of 0.2 μm to 1 μm and can be made of p-type doped GaN with a doping concentration of 5 x 1018cm"3to 5 x 1020cm"3, or can be made of an insulating material such as SiO2, Si3N4, Al2O3, AlN. 17 cm -3 ~ 5 x 1020cm"3. 18 cm -3 Figure 1

[0029] The second current blocking layer 150 is located on the first current blocking layer 140 and is adjacent to the N-type drift region 130. The second current blocking layer 150 has a thickness of 0.2 μm to 1 μm and can be made of p-type doped GaN with a doping concentration of 5 x 1018cm"3to 5 x 1020cm"3, or can be made of an insulating material such as SiO2, Si3N4, Al2O3, AlN. 17 cm -3 ~ 5 x 1020cm"3. 18 cm -3

[0030] The channel layer 160 is located on the N-type drift region 130 and at least a portion of the second current blocking layer 150. Specifically, the channel layer 160 can be made of unintentionally doped GaN or undoped GaN, and has a thickness of 100 nm to 200 nm. As shown in FIG. 1, the length of the channel layer 160 is set to cover the entire N-type drift region, but only covers a portion of the second current blocking layer 150. Figure 1 Figure 1 ​​​​​A portion of the second current blocking layer 150 on both sides of the channel layer 160, the specific length of which can be set according to actual needs. The material used to fabricate the channel layer 160 can be GaN.

[0031] Barrier layer 170 and p-type layer 180 are located on channel layer 160. Barrier layer 170 has a thickness of 10 nm to 25 nm and can be made of AlGaN, with an Al content between 20% and 30%. P-type layer 180 has a thickness of 100 nm to 250 nm and a doping concentration of 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The material used can be either GaN or AlGaN. The barrier layer 170 is selected as AlGaN material and is used to form a two-dimensional electron gas within the channel layer 160.

[0032] Additionally, the source 122 is located on the second current blocking layer 150 and adjacent to the channel layer 160, the barrier layer 170 and the P-type layer 180; the gate 123 is located on the P-type layer 180; and the passivation layer 190 is located between the source 122 and the gate 123.

[0033] In some embodiments, the metal used to fabricate the gate 123 includes aluminum (Al), titanium (Ti), nickel (Ni), tungsten (W), silver (Ag), cobalt (Co), and gold (Au). Similarly, the metals used to fabricate the drain electrode 121 and the source electrode 122 can be selected and configured as needed. The gate 123 is disposed on the side of the P-type layer 180 opposite to the barrier layer 170, and the gate 123 forms a Schottky contact with the P-type layer 180.

[0034] The source electrode 122 is disposed at both ends of the channel layer 160 and connected to the channel layer 160.

[0035] In some embodiments, it may also be as follows Figure 9 As shown, a P-type gate groove 171 is etched in the middle of the barrier layer 170. Specifically, the depth of the P-type gate groove 171 is 2nm to 6nm, and it is filled by the P-type layer 180. It should be noted that the P-type gate groove 171 cannot penetrate the barrier layer 170, that is, the depth of the P-type gate groove 171 is less than the depth of the barrier layer 170.

[0036] In this invention, based on the addition of a P-type layer 180 under the gate 123, a P-type gate recess 171 is formed by etching the barrier layer 170 and filled by the P-type layer 180. This compensates for the transconductance decrease caused by the addition of the P-type layer 180 and better realizes the enhancement mode function, that is, obtains a larger forward threshold voltage.

[0037] In some examples, the passivation layer 190 is located on a portion of the end surface of the barrier layer 170 where the P-type gate recess 171 is not provided.

[0038] By placing the passivation layer 190 between the source 122 and the gate 123 on a portion of the end surface of the barrier layer 110 where the P-type gate recess 171 is not provided, that is, increasing the length T2 of the source protrusion 124 of the source 122 toward the gate 123, the contact area between the source 122 and the barrier layer 170 is increased, the electron concentration at the contact interface is increased, the channel electron concentration is increased, the transconductance and breakdown voltage of the device are improved, the output current density loss caused by etching the barrier layer is compensated, the on-resistance is reduced, and the output characteristics are improved.

[0039] In other embodiments of the present invention, the N-type drift region 130 may be configured as a plurality of N-pillar drift layers with different doping concentrations.

[0040] For example, the N-type drift region 130 includes at least two N-type drift layers with decreasing doping concentrations, sequentially distributed from the upper surface of the substrate. Figure 1 The diagram shows five N-type drift layers 131-135. Of course, those skilled in the art can choose the number of N-type drift layers according to actual needs.

[0041] Preferably, the thickness of the at least two N-type drift layers is the same. That is, the thickness of the five N-type drift layers 131-135 shown in the figure is the same, but they can also be set to have different thicknesses.

[0042] In one example, the N-type drift region 130 includes five N-type drift layers 131-135 with different doping concentrations. The total thickness of the N-type drift region is 2 μm to 15 μm, and the doping concentration decreases sequentially from bottom to top on the upper surface of the substrate. The doping concentration of the N-type drift layers 131-135 is 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 .

[0043] In some embodiments, the N-type drift layers 131-135 are selected from N-type doped GaN, with a total thickness of 2 μm to 15 μm, wherein the doping concentration is 1 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The thickness decreases sequentially from bottom to top, preferably 10 μm, and the doping concentration ranges from 5 × 10⁻⁶. 16 cm -3 It begins to decrease upwards.

[0044] The concentration stratified doping is performed on the plurality of N-type drift layers of the N-type drift region, that is, the doping concentration distributed in sequence from the upper surface of the substrate decreases in sequence, further compensating for the output current density loss caused by etching the barrier layer, reducing the on-resistance, and improving the output characteristics.

[0045] Referring to Figures 2 to 16 A flowchart of a method for fabricating a current aperture vertical electron transistor according to another embodiment of the present application is shown.

[0046] As shown, the method includes:

[0047] Step S1: providing a substrate (110);

[0048] Step S2: sequentially hetero-epitaxially growing five N-type doped layers (131-135) with decreasing doping concentration upwards on the substrate (110), the five N-type doped layers (131-135) forming an N-type drift region (130), wherein the thickness of the five N-type doped layers (131-135) is in the range of 0.4 μm to 2 μm, and the doping concentration is in the range of 1×10 16 cm -3 to 1×10 17 cm -3 ;

[0049] Step S3: sequentially growing a first current blocking layer (140) and a second current blocking layer (150) from bottom to top at both ends of the N-type drift region (130); the thickness of the first current blocking layer (140) is in the range of 1.8 μm to 14 μm, and the doping concentration is in the range of 1×10 16 cm -3 to 8×10 16 cm -3 ; the thickness of the second current blocking layer (150) is in the range of 0.2 μm to 1 μm, and the doping concentration is in the range of 5×10 17 cm -3 to 5×10 18 cm -3 ;

[0050] Step S6: growing a channel layer (160) with a length of 100 nm to 200 nm on a part of the second current blocking layer (150) and on the N-type drift region (130);

[0051] Step S7: growing a barrier layer (170) on the channel layer (160), the thickness of the barrier layer (170) being between 10 nm and 25 nm;

[0052] Step S8: Forming a P-type gate recess (171) with a depth of 2nm-6nm in the middle of the barrier layer (170);

[0053] Step S9: Growing a P-type layer (180) with a thickness of 100nm-250nm to fill the P-type gate recess (171), the material of the P-type layer (180) is GaN or AlGaN, and the doping concentration is 5x1018cm-2-5x1019cm-2. 17 cm -3 -5x1019cm 18 -2. -3 ;

[0054] Step S10: Depositing a passivation layer (190) on the P-type layer (180) and the part of the surface of the barrier layer (170) beyond the P-type layer (180) on both sides;

[0055] Step S11: Etching the passivation layer (190), the barrier layer (170), and the channel layer (160) to form an opening penetrating to the second layer current blocking layer (150), and filling the opening with a metal to form an ohmic contact source (122);

[0056] Step S12: Depositing a metal combination on the lower surface of the substrate (110) to form a drain (121) after heat treatment;

[0057] Step S13: Etching away part of the passivation layer (190) on the P-type layer (180) to form a gate opening region, and depositing a metal in the gate opening region to form a gate (123).

[0058] The preparation method of the current aperture vertical electron transistor will be described in detail below with reference to the specific Figures 2 to 16 flowchart of the preparation method of the current aperture vertical electron transistor.

[0059] Referring to Figure 2 In step S1, a substrate 110 is provided, for example, a substrate composed of silicon, silicon carbide, or aluminum oxide (or referred to as sapphire). The substrate 110 is cleaned, and the substrate 110 is placed in an organic solvent (such as acetone, isopropanol, ethanol, etc.) for cleaning. The cleaning process can be accelerated by ultrasonic vibration under the action of the organic solvent, in which the organic solvent can effectively remove organic contaminants, grease, and residues on the surface, and ultrasonic cleaning can effectively clean the surface of small structures and cracks. The surface of the substrate 110 is cleaned with an acidic solution (such as concentrated hydrochloric acid, nitric acid, etc.) and an alkaline solution (such as sodium hydroxide solution), respectively. For example, the substrate 110 is rinsed with deionized water to remove residual solvents and chemical cleaning agents during the cleaning process. Finally, the surface is completely dried by nitrogen blowing or vacuum drying.

[0060] Referring to Figure 3In step S2, five N-type drift layers 131-135 with a thickness of 0.4 μm each are grown on the substrate 110

[0061] ~5 μm, and a doping concentration of 1 x 1018cm-3 16 cm -3 ~1 x 1018cm-3 17 cm -3 N-type drift layers 131-135 with a thickness decreasing in sequence from top to bottom. Preferably, in one example, each N-type drift layer has a thickness of 2 μm, and a doping concentration of 1 x 1018cm-3 16 cm -3 starting from the top, and a material of GaN or SiC is used. Techniques for hetero-epitaxial growth such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase deposition (HVPE), molecule beam epitaxy (MBE), but not limited to, are used.

[0062] Referring to Figure 4 In step S3, two current blocking layer regions are etched at both ends of the N-type drift layers 131-135 by a patterning process, and preferably, each current blocking layer region has a width of 3.5 μm. The patterning process is, for example, a photolithography (etching) process, which is a general term for stripping or removing materials by solution, reaction ion or other mechanical means, such as ion beam etching (IBE), deep reactive ion etching (DRIE), reactive ion etching (RIE), focused ion beam etching (FIB), inductively coupled plasma etching (ICP).

[0063] Referring to Figure 5 In step S4, a first layer of current blocking layer 140 is grown in the two current blocking layer regions, and before the growth of the first layer of current blocking layer 140, an ultraviolet chemical treatment is performed to remove surface contaminants, shield the N-type drift region 131-135, and grow a first layer of current blocking layer 140 (P-type GaN) with a thickness of 1.8 μm ~ 14 μm and a doping concentration of 1 x 1018cm-3~8 x 1018cm-3. Preferably, in one example, the first layer of current blocking layer 140 has a thickness of 9.4 μm and a doping concentration of 2 x 1018cm-3. 16 cm -3 ~8 x 1018cm-3 16 cm -3 ~8 x 1018cm-3 16 cm -3In some embodiments, a p-type AlGaN material can be grown as the first current-blocking layer. Techniques for heteroepitaxial growth include, but are not limited to, selective region growth (SAG), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase deposition (HVPE), and molecular beam epitaxy (MBE).

[0064] See Figure 6 In step S5: a second current blocking layer 150 is grown above the first current blocking layer 140. The second current blocking layer 150 can be selected with a thickness of 0.2 μm to 1 μm and a doping concentration of 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The p-type GaN. Preferably, in one example, the thickness is 0.6 μm and the doping concentration is 1 × 10⁻⁶. 18 cm -3 In some embodiments, the second current blocking layer 150 may be selected from insulating materials such as SiO2, Si3N4, Al2O3, and AlN. The growth techniques for the second current blocking layer 150 include, but are not limited to, selective region growth (SAG), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase deposition (HVPE), and molecular beam epitaxy (MBE).

[0065] See Figure 7 In step S6: a channel layer 160 of 100 nm to 200 nm is grown on the second current blocking layer 150 and the N-type drift region 130. The growth material is GaN that is neither intentionally nor unintentionally doped, that is, it can be undoped GaN. Preferably, its thickness is 150 nm. The growth techniques for the channel layer 160 include, but are not limited to, selective region growth (SAG), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase deposition (HVPE), and molecular beam epitaxy (MBE).

[0066] See Figure 8In step S7: an N-type AlGaN barrier layer 170 is grown on the channel layer 160. The thickness of the barrier layer 170 is between 10 nm and 25 nm, and the Al content is between 20% and 30%. Preferably, in one embodiment, the thickness of the barrier layer 170 is 20 nm, and the Al content is 23%. The epitaxial growth techniques for the barrier layer 170 include, but are not limited to, selective region growth (SAG), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase deposition (HVPE), and molecular beam epitaxy (MBE).

[0067] See Figure 9 In step S8: A P-type gate groove 171 with a thickness of 2nm to 6nm is formed in the middle of the AlGaN barrier layer 170 using a patterning fabrication process. Preferably, the depth of the P-type gate groove 171 is 4nm. Patterning fabrication processes, such as photolithography (etching) processes, are a general term for the stripping and removal of materials through solutions, reactive ions, or other mechanical methods, such as ion beam etching (IBE), deep silicon etching (DRIE), reactive ion etching (RIE), focused ion beam etching (FIB), and inductively coupled plasma etching (ICP).

[0068] See Figure 10 In step S9: A P-type layer 180 with a thickness of 100nm to 250nm is grown to fill the P-type gate groove 171 of the barrier layer 100. The P-type layer 180 can be GaN or AlGaN, and is formed by ion implantation to a doping concentration of 5×10⁻⁶. 17 cm -3 ~5×10 18 cm -3 Formation. Preferably, in one embodiment, the p-type layer 180 is made of GaN, has a thickness of 200 nm, and a doping concentration of 1 × 10⁻⁶. 18 cm -3 The growth techniques for the P-type layer 180 include, but are not limited to, selective region growth (SAG), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase deposition (HVPE), and molecular beam epitaxy (MBE).

[0069] See Figure 11In step S10, a passivation layer is deposited on the barrier layer 170 and the P-type layer 180. The passivation layer can be made of SiO2, Si3N4, Al2O3, or AlN. The passivation layer can be formed by atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like, but is not limited thereto. The portion of the passivation layer covering the P-type layer 180 can have a trapezoidal cross-sectional shape.

[0070] Referring to Figure 12 In step S11, the passivation layer, the barrier layer 170, and the channel layer 180 are etched based on a patterning process to form an opening extending to the current blocking layer 150 and form left and right source opening regions. The lithography (etching) process of the patterning process can be ion beam etching (IBE), deep reactive ion etching (DRIE), reactive ion etching (RIE), focused ion beam etching (FIB), or inductively coupled plasma etching (ICP), for example.

[0071] Referring to Figure 13 In step S12, the source opening region is filled with metal, and then heat treatment is performed in an N2 environment to form an ohmic contact source 122.

[0072] Referring to Figures 14-16 In step S13, a metal combination is deposited on the back of the substrate 110 to form a drain 121 after heat treatment, and a portion of the passivation layer on the P-type layer 180 is etched to form a gate opening region. A metal, which can be selected from aluminum (Al), titanium (Ti), nickel (Ni), tungsten (W), silver (Ag), cobalt (Co), and gold (Au), is deposited in the gate opening region. The metal is placed in an evaporation device, and the thickness and uniformity of the gate thin film can be controlled by controlling the evaporation time and temperature. The gate is formed, and then ultrasonic cleaning is performed using an organic solvent (such as acetone, isopropyl alcohol, ethanol, or the like) in combination with an ultrasonic cleaning machine, and finally the device is dried with nitrogen gas. Thus, the current aperture vertical electron transistor 100 described in the embodiments of the present application is obtained.

[0073] Embodiment 1

[0074] In embodiment 1, the substrate 110 is N-type GaN with a thickness of 1 μm and a doping concentration of 1×1018cm-3. The N-type drift regions 109-113 are disposed on the substrate 110. The N-type drift regions 131-135 are N-type doped GaN with a thickness of 10 μm and a doping concentration of 5×1018cm-3. 18 cm -3 The N-type drift regions 109-113 are disposed on the substrate 110. The N-type drift regions 131-135 are N-type doped GaN with a thickness of 10 μm and a doping concentration of 5×1018cm-3. 16 cm -3The current blocking layer 140 is P-type GaN with a thickness of 9.4 μm and a doping concentration of 2 x 1018cm-3. The current blocking layer 150 is P-type GaN with a thickness of 0.6 μm and a doping concentration of 1 x 1018cm-3. The channel layer 160 is unintentionally doped GaN with a thickness of 150 nm. The barrier layer 170 is N-type AlGaN with an Al composition of 0.23, a thickness of 20 nm, and a doping concentration of 1.5 x 1018cm-3. The P-type layer 180 is P-type GaN with a thickness of 200 nm and a doping concentration of 1 x 1018cm-3. The passivation layer 190 is Si3N4 with a thickness of 225 nm. The depth of the P-type gate recess 171 is T1, which is 2 nm in this embodiment. 16 cm -3 18 cm -3 17 cm -3 18 cm -3 The depth of the P-type gate recess 171 is T1, which is 2 nm in this embodiment.

[0075] Example 2

[0076] The T1 in Example 1 is modified to 4 nm, and the rest of the parameter settings are the same as those in Example 1, and thus will not be repeated.

[0077] Example 3

[0078] The T1 in Example 1 is modified to 6 nm, and the rest of the parameter settings are the same as those in Example 1, and thus will not be repeated.

[0079] Comparative Example 1

[0080] The T1 in Example 1 is modified to 0 nm, and the rest of the parameter settings are the same as those in Example 1, and thus will not be repeated.

[0081] Figure 17 The figure is the transfer characteristic curve of the current aperture vertical electron transistor of Comparative Example 1 and Examples 1, 2, and 3. It can be clearly seen from the figure that as the recess depth increases, the threshold voltage of the device also increases. This is because after etching the barrier layer, the thickness of the barrier layer decreases, and the concentration of the two-dimensional electron gas generated under the gate decreases, resulting in an increase in the threshold voltage.

[0082] Figure 18 The figure is the breakdown characteristic curve of the current aperture vertical electron transistor of Comparative Example 1 and Examples 1, 2, and 3. It can be found from the figure that as the recess depth increases, the breakdown voltage also increases.

[0083] Figure 19 ​​​The comparison chart of the breakdown voltage and on-resistance of the current-aperture vertical electron transistor of Comparative Example 1 and Examples 1, 2 and 3 can be found from the figure that when the groove depth is 2 nm or 4 nm, the device has lower on-resistance and higher breakdown voltage.

[0084] Example 4

[0085] The N-type drift region doping concentration in Example 2 is unified to 1 x 1015cm-3, and the rest of the parameter settings are the same as those of Example 2, and thus are not repeated. 16 cm -3

[0086] Figure 20 The output characteristic curve of the current-aperture vertical electron transistor of Example 4 and Example 2 is shown in the figure, and the on-resistance can be obtained by calculating the slope of the linear region of the output curve. It can be found from the figure that the on-resistance of the device using the drift region layered doping structure is lower than that of the device without layered doping structure, because the doping concentration gradient increases from top to bottom in the drift region, which leads to the width of the space charge region formed by the drift region and the second current blocking layer to be small, that is, the current path is wide, so that the on-resistance is reduced.

[0087] Example 5

[0088] The source of Example 2 is protruded towards the gate direction, and the length of the protruded part is T2. In this example, T2 is 0.4 μm, and the rest of the parameter settings are the same as those of Example 2, and thus are not repeated.

[0089] Example 6

[0090] T2 in Example 5 is modified to 0.8 μm, and the rest of the parameter settings are the same as those of Example 5, and thus are not repeated.

[0091] Comparative Example 2

[0092] T2 in Example 5 is modified to 0 μm, and the rest of the parameter settings are the same as those of Example 5, and thus are not repeated.

[0093] Figure 21 The gate leakage current comparison chart of the current-aperture vertical electron transistor of Comparative Example 2 and Examples 5 and 6 at Vds=0 V can be found from the figure that when T2 is 0.4 μm, the device obtains the lowest gate leakage current, which is-19 order of magnitude, which is one order of magnitude lower than that when T2 is 0 μm and 0.8 μm.

[0094] Figure 22 The V g ​=4V, the output characteristic curves of the current aperture vertical electron transistors of Comparative Example 2, Example 5, and Example 6 are shown. T2 is the length of the source protrusion. It can be seen from the figure that as T2 increases, the on-resistance of the device increases and the output saturation current increases. According to the metal-semiconductor contact principle in semiconductor physics, when the work function of the metal is less than that of the semiconductor, electrons will flow from the metal to the semiconductor, forming a negative space charge region on the semiconductor surface. Therefore, as the contact area between the source and the barrier layer increases, electrons flow from the source to the barrier layer, resulting in an increase in the electron concentration at the contact interface and an increase in the channel electron concentration.

[0095] Figure 23 For V ds At 5V, the transconductance diagrams of the current aperture vertical electronic transistors in Comparative Example 2, Example 5, and Example 6 show that the transconductance of the device is greatly improved after the source protrusion improvement.

[0096] The embodiments of the present invention provide a current aperture vertical electron transistor (CAVET) and a method for fabricating the same, which have at least one or a portion of the following advantages:

[0097] 1) Based on the addition of a P-type layer under the gate, a P-type gate groove is formed by etching the barrier layer and filled by the P-type layer, which makes up for the transconductance drop caused by the addition of the P-type layer and better realizes the enhancement mode function, that is, a larger positive threshold voltage is obtained.

[0098] 2) By placing the passivation layer between the source and the gate on a portion of the end surface of the barrier layer where the P-type gate groove is not located, that is, by increasing the length of the protrusion of the source towards the gate, the contact area between the source and the barrier layer is increased, the electron concentration at the contact interface is increased, the channel electron concentration is increased, the transconductance and breakdown voltage of the device are improved, the output current density loss caused by etching the barrier layer is compensated, the on-resistance is reduced, and the output characteristics are improved.

[0099] 3) By performing concentration-layered doping in multiple N-type drift layers in the N-type drift region, that is, the doping concentration is distributed sequentially from the upper surface of the substrate, the output current density loss caused by the etching barrier layer is further compensated, the on-resistance is reduced, and the output characteristics are improved.

[0100] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A current-aperture vertical electron transistor, characterized by, The current-aperture vertical electron transistor comprises: a substrate (110); a drain (121) located on the lower surface of the substrate (110); an N-type drift region (130) located on the upper surface of the substrate (110) and a first layer of current-blocking layer (140) located on both sides of the N-type drift region (130) and adjacent to the N-type drift region (130); a second layer of current-blocking layer (150) located on the first layer of current-blocking layer (140) and adjacent to the N-type drift region (130); a channel layer (160) located on the N-type drift region (130) and at least a part of the second layer of current-blocking layer (150); a barrier layer (170) located on the channel layer (160); a P-type gate recess (171) is etched in the middle of the barrier layer (170); the barrier layer (170) further comprises a barrier layer protruding portion located on both sides of the P-type gate recess (171), a P-type layer (180) located on the barrier layer (170); a source (122) located on the second layer of current-blocking layer (150) and adjacent to the channel layer (160) and the barrier layer (170); a gate (123) located on the P-type layer (180); a passivation layer (190) located between the source (122) and the gate (123) and adjacent to the source (122), the gate (123), and the P-type layer (180), the passivation layer (190) is located on a part of the upper surface of the protruding portion of the barrier layer (170), and a source protruding portion (124) of the source (122) at least partially covers the remaining part of the upper surface of the barrier layer protruding portion (172).

2. The current-aperture vertical electron transistor according to claim 1, wherein the depth of the P-type gate recess (171) is 2 nm to 6 nm and is filled by the P-type layer (180).

3. The current-aperture vertical electron transistor according to claim 2, wherein the depth of the P-type gate recess (171) is less than the depth of the barrier layer (170).

4. The current-aperture vertical electron transistor according to claim 1, wherein the N-type drift region (130) comprises at least two N-type drift layers with decreasing doping concentrations in sequence from the upper surface of the substrate.

5. The current-aperture vertical electron transistor according to claim 4, wherein the thicknesses of the at least two N-type drift layers are the same.

6. The current-aperture vertical electron transistor according to claim 5, wherein The N-type drift region (130) includes 5 N-type drift layers (131-135) with different doping concentrations, the total thickness of the N-type drift region (130) is 2-15 μm, the doping concentration of the N-type drift layers (131-135) is 1 x 1016-1 x 1018 cm-3. 16 cm -3 ~1 x 1018 17 cm -3 .

7. The current-aperture vertical electron transistor according to claim 6, wherein the thickness of the barrier layer (170) is 10 nm to 25 nm, and the material of the barrier layer (170) is AlGaN, wherein the proportion of Al component is between 20% and 30%; The thickness of the P-type layer (180) is 100 nm to 250 nm, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The material of the P-type layer (180) includes GaN or AlGaN; the material of the channel layer (160) is unintentionally doped GaN, and the thickness is 100 nm to 200 nm. The preparation material of the first layer current blocking layer (140) includes GaN or AlGaN, the thickness is 1.8 μm-14.4 μm, the doping concentration is 1×10 16 cm -3 -8×10 16 cm -3 ; The preparation material of the second layer current blocking layer (150) includes any one or any combination of p-type doped GaN, SiO2, Si3N4, Al2O3 and AlN, with a thickness of 0.2 μm to 1 μm and a doping concentration of 5 x 1018 cm-3 to 5 x 1020 cm-3. 17 cm -3 ~ 5 x 1020 cm-3. 18 cm -3 .

8. A preparation method of a current-aperture vertical electron transistor, the preparation method comprising: step S1: providing a substrate (110); Step S2: sequentially hetero-epitaxially growing five N-type doped layers (131-135) with decreasing upward doped concentration on the substrate (110), the five N-type doped layers (131-135) constituting an N-type drift region (130), wherein the thickness of the five N-type doped layers (131-135) is in the range of 0.4 μm to 3 μm, and the doped concentration is in the range of 1 x 1018cm-3 to 1 x 1019cm-3. 16 cm -3 ~1 x 1018cm 17 cm -3 -3. Step S3: growing a first current blocking layer (140) and a second current blocking layer (150) on the N-type drift region (130) in sequence from bottom to top; the thickness of the first current blocking layer (140) is in the range of 1.8 μm to 14.4 μm, the doping concentration is in the range of 1×10 16 cm -3 ~8×10 16 cm -3 ; the thickness of the second current blocking layer (150) is in the range of 0.2 μm to 1 μm, the doping concentration is in the range of 5×10 17 cm -3 ~5×10 18 cm -3 ; Step S6: growing a channel layer (160) with a length of 100nm-200nm on a part of the second layer current blocking layer (150) and on the N-type drift region (130); Step S7: growing a barrier layer (170) on the channel layer (160), the thickness of the barrier layer (170) being between 10nm-25nm; Step S8: forming a P-type gate recess (171) with a depth of 2nm-6nm in the middle of the barrier layer (170); the barrier layer (170) further comprises barrier layer protrusions on both sides of the P-type gate recess (171); Step S9: growing a P-type layer (180) with a thickness of 100-250 nm to fill the P-type gate recess (171), the P-type layer (180) being made of GaN or AlGaN, and having a doping concentration of 5x1018-5x1019cm-3. 17 cm -3 -5x1019cm-3. 18 cm -3 ; Step S10: depositing a passivation layer (190) on the P-type layer (180) and on a part of the surface of the barrier layer (170) beyond the P-type layer (180) on both sides; Step S11: etching the passivation layer (190), the barrier layer (170), and the channel layer (160) to form an opening that penetrates to the second layer current blocking layer (150), and filling the opening with a metal to form an ohmic contact source electrode (122), the passivation layer (190) being on a part of the upper surface of the protrusions of the barrier layer (170), and a source electrode protrusion (124) of the source electrode (122) at least partially covering the remaining part of the upper surface of the barrier layer protrusions (172); Step S12: depositing a metal combination on the lower surface of the substrate (110) to form a drain electrode (121) after heat treatment; Step S13: etching away part of the passivation layer (190) on the P-type layer (180) to form a gate opening region, and depositing a metal in the gate opening region to form a gate electrode (123).

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