A schottky barrier diode and a method of manufacturing the same

Abstract

This application relates to the field of diode technology, and more specifically, to a Schottky barrier diode and its fabrication method, by setting an n + ‑GaN layer, n ‑ -GaN layer and p + The GaN layer near the cathode metal electrode forms a sloping wall. This sloping wall structure reduces the electric field congestion effect near the anode metal electrode, thereby increasing the breakdown voltage of the Schottky barrier diode. Furthermore, the Schottky barrier diode adopts a quasi-vertical structure design, avoiding the disadvantages of large chip area and low forward current density of lateral structures. At the same time, it combines the advantages of high current and high breakdown voltage of quasi-vertical structures, achieving the advantages of low power consumption and high power of the Schottky barrier diode, making it suitable for high-frequency rectification applications.

Description

Technical Field

[0001] This application relates to the field of diode technology, and more specifically, to a Schottky barrier diode and its fabrication method. Background Technology

[0002] Silicon-based devices boast mature and stable technology, low cost, and high reliability, making them a key component of low-cost home appliances and highly integrated devices. However, the performance of traditional silicon-based diodes is increasingly approaching the physical limits of silicon, making significant performance improvements difficult. To meet ever-growing performance demands, third-generation semiconductor devices, represented by GaN, are becoming increasingly popular due to their wider bandgap, higher thermal conductivity, and larger critical breakdown field. Currently, diode structures mainly fall into two categories: PIN (P-type-Intrinsic-N-type) diodes utilizing a PN junction barrier, and Schottky barrier diodes utilizing a Schottky barrier. Schottky barrier diodes, formed by direct contact between metal and semiconductor, conduct most charge carriers compared to PIN diodes, exhibiting a lower barrier height. This results in lower on-state voltage and on-resistance, higher switching frequency, and excellent reverse recovery characteristics, making them more suitable for high-frequency and high-power applications. However, the breakdown voltage of existing Si / GaN Schottky barrier diodes is far below the theoretical limit, leading to potential failure in some high-power applications.

[0003] Therefore, it is of great significance to develop a Schottky barrier diode that can withstand high power and high current and has strong breakdown performance.

[0004] There is currently no effective technical solution to the above problems. Summary of the Invention

[0005] The purpose of this application is to provide a Schottky barrier diode and its fabrication method, which effectively improves the breakdown voltage of the Schottky barrier diode.

[0006] In a first aspect, this application provides a Schottky barrier diode, comprising a substrate, an AlN nucleation layer, a UID-GaN layer, an n-GaN layer, and an n... + -GaN layer, n - -GaN layer, p + -GaN layer, anode metal electrode and cathode metal electrode;

[0007] The substrate, the AlN nucleation layer, the UID-GaN layer, and the n-GaN layer are stacked sequentially from bottom to top;

[0008] The cathode metal electrode is disposed on top of the n-GaN layer and located on one side of the n-GaN layer;

[0009] The n + -GaN layer and the n - -GaN layers are stacked sequentially from bottom to top on the top of the n-GaN layer on the side away from the cathode metal electrode;

[0010] The anode metal electrode is disposed at the n - - The top of the GaN layer is located away from the side of the cathode metal electrode;

[0011] The p + -GaN layer is disposed on the n - - The top of the GaN layer is located on the side closest to the cathode metal electrode;

[0012] The n + -GaN layer, the n - -GaN layer and the p + - The GaN layer near the cathode metal electrode forms an inclined wall, and the distance between the inclined wall and the cathode metal electrode gradually increases from bottom to top.

[0013] The above settings effectively improve the breakdown voltage of the Schottky barrier diode.

[0014] Optionally, the n + - The thickness of the GaN layer is 100nm-200nm.

[0015] The above settings not only help improve the stability of the material and carrier lifetime, but also reduce macroscopic defects and improve the overall reliability of the Schottky barrier diode.

[0016] Optionally, the p + - The thickness of the GaN layer is 100nm-200nm.

[0017] Optionally, the n - - The thickness of the GaN layer is 200nm-300nm.

[0018] Optionally, the p + The dopant of the GaN layer is Mg, and the p + The doping concentration of Mg in the GaN layer is 1×10⁻⁶. 16 cm 3 .

[0019] Optionally, the n - The dopant of the GaN layer is Mg, and the n - The doping concentration of Mg in the GaN layer is 3 × 10⁻⁶.20 cm 3 .

[0020] Optionally, the n + The dopant of the GaN layer is Mg, and the n + The doping concentration of Mg in the GaN layer is 3 × 10⁻⁶. 16 cm 3 .

[0021] Secondly, this application provides a method for fabricating a Schottky barrier diode, used to fabricate the Schottky barrier diode described in any of the preceding claims, comprising the steps of:

[0022] A1. The AlN nucleation layer, the UID-GaN layer, the n-GaN layer, and the n-GaN layer are grown sequentially from bottom to top on a silicon substrate using organometallic chemical vapor deposition. + -GaN layer, the n - -GaN layer and the p + -GaN layer;

[0023] A2. The cathode metal electrode is fabricated on the n-GaN layer using an etching method;

[0024] A3. For each of the n... + -GaN layer, the n - -GaN layer and the p + - The GaN layer is etched along the side of the cathode metal electrode to form the inclined wall;

[0025] A4. Based on the etching method, in the n - The anode metal electrode is fabricated on a GaN layer.

[0026] Optionally, step A2 includes:

[0027] The fabrication area of ​​the cathode metal electrode was etched on the n-GaN layer using photolithography, and then the process was carried out under a vacuum degree ≤10. -3 In an environment of Pa, an electron beam with an energy of 3kV is used to perform Ti-Al-Ni-Au alloy evaporation based on electron beam evaporation. Then, acetone is used for photoresist stripping and annealing is performed in an N2 atmosphere to form the cathode metal electrode in the preparation area of ​​the cathode metal electrode.

[0028] Optionally, step A4 includes:

[0029] Using photolithography on the n - The fabrication area of ​​the anode metal electrode is etched on the GaN layer, and then the vacuum degree is ≤10 -3In an environment of Pa, an electron beam with an energy of 3kV is used to perform Ni-Au alloy evaporation based on electron beam evaporation, and then acetone is used for photoresist stripping to form the anode metal electrode in the fabrication area of ​​the anode metal electrode.

[0030] Beneficial effects: This application provides a Schottky barrier diode and its fabrication method, which, by setting an n + -GaN layer, n - -GaN layer and p + The GaN layer near the cathode metal electrode forms a sloping wall. This sloping wall structure reduces the electric field congestion effect near the anode metal electrode, thereby increasing the breakdown voltage of the Schottky barrier diode. Furthermore, the Schottky barrier diode adopts a quasi-vertical structure design, avoiding the disadvantages of large chip area and low forward current density of lateral structures. At the same time, it combines the advantages of high current and high breakdown voltage of quasi-vertical structures, achieving the advantages of low power consumption and high power of the Schottky barrier diode, making it suitable for high-frequency rectification applications. Attached Figure Description

[0031] Figure 1 A schematic diagram of the overall structure of the Schottky barrier diode provided in this application.

[0032] Figure 2 This is a schematic diagram of another structure of the Schottky barrier diode provided in this application.

[0033] Figure 3 A flowchart illustrating the fabrication method of the Schottky barrier diode provided in this application.

[0034] Labeling Explanation: 01, Substrate; 02, AlN Nucleation Layer; 03, UID-GaN Layer; 04, n-GaN Layer; 05, Cathode Metal Electrode; 06, n + -GaN layer; 07, n - -GaN layer; 08, p + -GaN layer; 09, anode metal electrode. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0036] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] In a first aspect, this application provides a Schottky barrier diode, comprising a substrate 01, an AlN nucleation layer 02, a UID-GaN layer 03, an n-GaN layer 04, and an n-GaN layer 05. + -GaN layer 06, n - -GaN layer 07, p + -GaN layer 08, anode metal electrode 09 and cathode metal electrode 05;

[0038] Substrate 01, AlN nucleation layer 02, UID-GaN layer 03 and n-GaN layer 04 are stacked sequentially from bottom to top;

[0039] The cathode metal electrode 05 is disposed on top of the n-GaN layer 04 and located on one side of the n-GaN layer 04;

[0040] n + -GaN layer 06 and n - -GaN layer 07 is stacked sequentially from bottom to top on the top of n-GaN layer 04 on the side away from the cathode metal electrode 05;

[0041] Anode metal electrode 09 is set at n - - The top of the GaN layer 07 is on the side away from the cathode metal electrode 05;

[0042] p + -GaN layer 08 is set in n - - The top of the GaN layer 07 is located on the side closest to the cathode metal electrode 05;

[0043] n + -GaN layer 06, n --GaN layer 07 and p + -The GaN layer 08 forms an inclined wall on the side near the cathode metal electrode 05, and the distance between the inclined wall and the cathode metal electrode 05 gradually increases from bottom to top.

[0044] Specifically, this application sets by n + -GaN layer 06, n - -GaN layer 07 and p + The GaN layer 08 forms a sloping wall on the side near the cathode metal electrode 05. This sloping wall structure reduces the electric field congestion effect near the anode metal electrode 09, thereby increasing the breakdown voltage of the Schottky barrier diode. Furthermore, the Schottky barrier diode adopts a quasi-vertical structure design, avoiding the disadvantages of large chip area and low forward current density of lateral structures. It also combines the advantages of high current and high breakdown voltage of quasi-vertical structures, achieving the advantages of low power consumption and high power of the Schottky barrier diode, making it suitable for high-frequency rectification applications.

[0045] In some implementations, n + The thickness of the GaN layer 06 is 100nm-200nm.

[0046] Specifically, by optimizing n + The thickness of the GaN layer 06 not only helps improve the stability and carrier lifetime of the material, but also reduces macroscopic defects and improves the overall reliability of the Schottky barrier diode. In this application, n + The thickness of the GaN layer 06 is preferably 100nm-200nm.

[0047] In some implementations, p + The thickness of the GaN layer 08 is 100nm-200nm.

[0048] Specifically, by optimizing p + The thickness of the GaN layer (08) enables high breakdown voltage and stable electrical characteristics, thereby improving p-values. + - The best performance of GaN layer 08.

[0049] In some implementations, n - The thickness of the GaN layer 07 is 200nm-300nm.

[0050] Specifically, by optimizing n - The thickness of the GaN layer 07 not only helps to improve the stability and carrier lifetime of the material, but also reduces macroscopic defects and improves the overall reliability of the Schottky barrier diode.

[0051] In some implementations, p + The dopant for the GaN layer 08 is Mg, p+ The Mg doping concentration in the GaN layer 08 is 1×10⁻⁸. 16 cm 3 .

[0052] Specifically, since excessive Mg doping leads to a self-compensation effect, the hole concentration first rises to a maximum and then drops sharply. Therefore, the optimal hole concentration and resistivity can be achieved by optimizing the Mg flow rate. In this case, the effective activation of Mg impurities can be ensured by controlling the annealing conditions.

[0053] In some implementations, n - The dopant for the GaN layer 07 is Mg,n - The Mg doping concentration in the GaN layer 07 is 3 × 10⁻⁶. 20 cm 3 .

[0054] Specifically, by optimizing the Mg doping concentration to balance material properties and device characteristics, therefore, n - The preferred Mg doping concentration in the GaN layer 07 is 3 × 10⁻⁶. 20 cm 3 .

[0055] In some implementations, n + The dopant for the GaN layer 06 is Mg,n + The Mg doping concentration in the GaN layer 06 is 3 × 10⁻⁶. 16 cm 3 .

[0056] Specifically, by optimizing the Mg doping concentration to improve electronic and optical properties, and by optimizing its growth behavior and morphology control, therefore, n + The preferred Mg doping concentration in the GaN layer 06 is 3 × 10⁻⁶. 16 cm 3 .

[0057] In some embodiments, the dopant of the n-GaN layer O4 is Mg, and the doping concentration of Mg in the n-GaN layer O4 is 3 × 10⁻⁶. 18 cm 3 .

[0058] Specifically, by optimizing the Mg doping concentration, not only are the electronic and optical properties of the material improved, but the hole injection efficiency and mobility are also enhanced. Therefore, the preferred Mg doping concentration in the n-GaN layer O4 is 3 × 10⁻⁶. 18 cm 3 .

[0059] Secondly, this application provides a method for fabricating a Schottky barrier diode, used to fabricate the Schottky barrier diode described in any of the preceding claims, comprising the following steps:

[0060] A1. An AlN nucleation layer 02, a UID-GaN layer 03, an n-GaN layer 04, and an n-GaN layer 05 are sequentially grown from bottom to top on a silicon substrate 01 using organometallic chemical vapor deposition (OMD). + -GaN layer 06, n - -GaN layer 07 and p + -GaN layer 08;

[0061] A2. A cathode metal electrode 05 is fabricated on an n-GaN layer 04 using an etching method;

[0062] A3. For n respectively + -GaN layer 06, n - -GaN layer 07 and p + - The GaN layer 08 is etched on the side near the cathode metal electrode 05 to form a sloping wall;

[0063] A4. Based on etching methods, in n - - An anode metal electrode 09 is fabricated on a GaN layer 07.

[0064] Specifically, such as Figure 3 As shown, the Schottky barrier diode described above can be fabricated using the above-mentioned method, wherein, for n + -GaN layer 06, n - -GaN layer 07 and p + - The GaN layer 08 is etched to form a sloping wall near the cathode metal electrode 05. This sloping wall structure reduces the electric field congestion effect near the anode metal electrode 09, thereby improving the breakdown voltage of the Schottky barrier diode. Furthermore, the Schottky barrier diode adopts a quasi-vertical structure design, avoiding the disadvantages of large chip area and low forward current density of lateral structures. At the same time, it combines the advantages of high current and high breakdown voltage of quasi-vertical structures, achieving the advantages of low power consumption and high power of the Schottky barrier diode, making it suitable for high-frequency rectification applications.

[0065] The etching method in step A3 is existing technology and is not specifically limited here.

[0066] In practical applications, the above methods can be used to prepare AlN nucleation layers with a thickness of 200 nm (02), UID-GaN layers with a thickness of 100 nm (03), n-GaN layers with a thickness of 400 nm (04), and n-GaN layers with a thickness of 150 nm (05). + -GaN layer 06, n with a thickness of 220nm - -GaN layer 07 and p with a thickness of 150nm +- A GaN layer 08 is formed, and a cathode metal electrode 05 and an anode metal electrode 09, each with a width of 5 μm, are formed, wherein the horizontal spacing between the cathode metal electrode 05 and the anode metal electrode 09 is 20 μm.

[0067] In other embodiments, if the preparation of the inclined plane cannot be completed due to limitations in equipment, processes, or other conditions, therefore, for n + -GaN layer 06, n - -GaN layer 07 and p + -The GaN layer 08 near the cathode metal electrode 05 can adopt a stepped structure, that is, n + -GaN layer 06, n - -GaN layer 07 and p + -The distance between the GaN layer 08 and the cathode metal electrode 05 gradually increases from bottom to top (e.g., ...). Figure 2 As shown, in terms of effect, this stepped structure can also reduce the electric field crowding effect near the anode metal electrode 09 and improve the breakdown voltage of the Schottky barrier diode. Although the stepped structure is slightly inferior to the inclined wall structure, the stepped structure is cheaper to produce than the inclined wall structure.

[0068] In some implementations, step A2 includes:

[0069] The fabrication area of ​​the cathode metal electrode 05 was etched on the n-GaN layer 04 using photolithography, and then the process was carried out under a vacuum degree ≤10. -3 In an environment of Pa, an electron beam with an energy of 3kV is used to perform Ti-Al-Ni-Au alloy evaporation based on electron beam evaporation. Then, acetone is used for photoresist stripping and annealing is performed in an N2 atmosphere to form the cathode metal electrode 05 in the preparation area.

[0070] Specifically, the cathode metal electrode 05 can be prepared on the n-GaN layer 04 using the above method.

[0071] In some implementations, step A4 includes:

[0072] Using photolithography in n - - The fabrication area for the anode metal electrode 09 is etched on the GaN layer 07, and then the vacuum degree ≤10 -3 In an environment of Pa, an electron beam with an energy of 3kV is used to perform Ni-Au alloy evaporation based on electron beam evaporation, and then acetone is used for photoresist stripping to form the anode metal electrode 09 in the fabrication area.

[0073] Specifically, using the method described above, it is possible to achieve the following in n - - An anode metal electrode 09 was prepared on a GaN layer 07.

[0074] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0075] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A Schottky barrier diode, characterized in that, Includes substrate (01), AlN nucleation layer (02), UID-GaN layer (03), n-GaN layer (04), n + -GaN layer (06), n - -GaN layer (07), p + -GaN layer (08), anode metal electrode (09) and cathode metal electrode (05); The substrate (01), the AlN nucleation layer (02), the UID-GaN layer (03), and the n-GaN layer (04) are stacked sequentially from bottom to top; The cathode metal electrode (05) is disposed on top of the n-GaN layer (04) and located on one side of the n-GaN layer (04); The n + -GaN layer (06) and the n - -GaN layers are stacked sequentially from bottom to top on the top of the n-GaN layer (04) on the side away from the cathode metal electrode (05); The anode metal electrode (09) is disposed on the n - - The top of the GaN layer (07) is on the side away from the cathode metal electrode (05); The p + -GaN layer (08) is disposed in the n - - The top of the GaN layer (07) is located on the side close to the cathode metal electrode (05); The n + -GaN layer (06), the n - -GaN layer (07) and the p + - The GaN layer (08) forms an inclined wall on the side near the cathode metal electrode (05), and the distance between the inclined wall and the cathode metal electrode (05) gradually increases from bottom to top.

2. The Schottky barrier diode according to claim 1, characterized in that, The n + - The thickness of the GaN layer (06) is 100nm-200nm.

3. The Schottky barrier diode according to claim 1, characterized in that, The p + - The thickness of the GaN layer (08) is 100nm-200nm.

4. The Schottky barrier diode according to claim 1, characterized in that, The n - - The thickness of the GaN layer (07) is 200nm-300nm.

5. The Schottky barrier diode according to claim 1, characterized in that, The p + The dopant of the GaN layer (08) is Mg, and the p + The doping concentration of Mg in the GaN layer (08) is 1×10⁻⁶. 16 cm -3 .

6. The Schottky barrier diode according to claim 1, characterized in that, The n - The dopant of the GaN layer (07) is Mg, and the n - The doping concentration of Mg in the GaN layer (07) is 3 × 10⁻⁶. 20 cm -3 .

7. The Schottky barrier diode according to claim 1, characterized in that, The n + The dopant of the GaN layer (06) is Mg, and the n + The doping concentration of Mg in the GaN layer (06) is 3 × 10⁻⁶. 16 cm -3 .

8. A method for fabricating a Schottky barrier diode, characterized in that, The method for preparing the Schottky barrier diode according to any one of claims 1-7 includes the following steps: A1. The AlN nucleation layer (02), the UID-GaN layer (03), the n-GaN layer (04), and the n-GaN layer (05) are sequentially grown from bottom to top on a silicon substrate (01) using organometallic chemical vapor deposition. + -GaN layer (06), the n - -GaN layer (07) and the p + -GaN layer (08); A2. The cathode metal electrode (05) is fabricated on the n-GaN layer (04) based on an etching method. A3. For each of the n... + -GaN layer (06), the n - -GaN layer (07) and the p + - The GaN layer (08) is etched near the side of the cathode metal electrode (05) to form the inclined wall; A4. Based on the etching method, in the n - The anode metal electrode (09) is prepared on the GaN layer (07).

9. The method for fabricating a Schottky barrier diode according to claim 8, characterized in that, Step A2 includes: The fabrication area of ​​the cathode metal electrode (05) was etched on the n-GaN layer (04) using photolithography, and then the process was carried out under a vacuum degree ≤10. -3 In an environment of Pa, an electron beam with an energy of 3kV is used to perform Ti-Al-Ni-Au alloy evaporation based on electron beam evaporation. Then, acetone is used for photoresist stripping and annealing is performed in an N2 atmosphere to form the cathode metal electrode (05) in the preparation area of ​​the cathode metal electrode (05).

10. The method for fabricating a Schottky barrier diode according to claim 8, characterized in that, Step A4 includes: Using photolithography on the n - - The fabrication area of ​​the anode metal electrode (09) is etched on the GaN layer (07), and then the vacuum degree is ≤10 -3 In an environment of Pa, an electron beam with an energy of 3kV is used to perform Ni-Au alloy evaporation based on electron beam evaporation, and then acetone is used for photoresist stripping to form the anode metal electrode (09) in the preparation area of ​​the anode metal electrode (09).

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