A synchronous device for receiving and transmitting broadband spread spectrum signals

Abstract

The present invention provides a receiving and transmitting synchronization device for a broadband spread spectrum signal, wherein each sampling point of a quadruple sampling signal corresponds to a timestamp provided by a local timestamp counter; a frame detection and capture unit then determines whether the measured frame interval of four consecutive frames of quadruple sampling signals meets the requirements, and a timing synchronization unit extracts the best sampling point from the received quadruple sampling signal; a data packaging unit reassembles the extracted best sampling points into a single sampling data packet and transmits it to a host computer; the host computer predicts the time when the transmitting end sends a response signal based on the timestamp of the sampling point where the frame header is located obtained by analysis; thus, the present invention uses a local timestamp counter independent of transmission and reception, and connects the time streams of the receiving end and the transmitting end in series through the timestamp, so that the timestamp is synchronized in the entire process of signal reception and transmission, and can accurately control the synchronization of reception and transmission, thereby reducing the resource consumption of FPGA.

Description

Technical Field

[0001] The present invention belongs to the technical field of spread spectrum communication, and in particular relates to a receiving and sending synchronization device for broadband spread spectrum signals. Background Art

[0002] In a spread-spectrum communication system, the transmitter first performs a spreading code correlation operation on the original narrowband signal. The receiver then exploits the autocorrelation characteristics of the spreading code used by the original narrowband signal, compresses the spread-spectrum signal spectrum using appropriate despreading techniques, and recovers the transmitted signal using filtering techniques. Unrelated signals such as noise and interference are only expanded once by the spreading code at the receiver into a wideband random signal, making them easily filtered out by designing corresponding narrowband filters. However, the parallel filtering, frame detection, and capture operations involved in the receiver processing consume significant FPGA resources. Furthermore, in certain scenarios with strict requirements on the timing of frame transmission and reception, it is generally difficult to establish a time synchronization relationship between the receiver and transmitter, or establishing time synchronization requires significant algorithmic complexity and resource overhead. Summary of the Invention

[0003] To solve the above problems, the present invention provides a device for synchronizing the reception and transmission of broadband spread spectrum signals, which has timestamp synchronization in the entire process of signal reception and transmission, thereby accurately controlling the synchronization of reception and transmission, and can receive and send user data of more parallel channels with the same FPGA on-chip resource consumption.

[0004] A receiving and transmitting synchronization device for a broadband spread spectrum signal comprises a receiving end, a host computer, a transmitting end, and a local timestamp counter; wherein the receiving end comprises a first pre-processing module, a frame detection and capture unit, a timing synchronization unit, and a data packaging unit;

[0005] The first preprocessing module converts each frame of continuous broadband spread spectrum signals into discrete quadruple-sampled signals, wherein each sampling point in the quadruple-sampled signal corresponds to a timestamp provided by a local timestamp counter; each frame of the quadruple-sampled signal includes multiple chips, each chip includes four sampling points, and data obtained by sampling each designated frequency point of the broadband spread spectrum signal four times is used as the signal of the four sampling points of the same chip;

[0006] The frame detection and capture unit is used to determine whether the difference between the measured frame interval and the set frame interval between adjacent frames in four consecutive frames of quadruple sampling signals is within a set threshold range. If so, it indicates that the broadband spread spectrum signal is successfully captured, and outputs the quadruple sampling signals of the last frame and subsequent frames in the four frames of quadruple sampling signals to the timing synchronization unit;

[0007] The timing synchronization unit is used to extract the best sampling point from each chip of the received quadruple sampling signal;

[0008] The data packaging unit is used to reorganize the extracted optimal sampling points into single sampling data packets and send them to the host computer;

[0009] The host computer is used to parse the single sampling data packet and predict the time when the sending end sends the response signal in response to the single sampling data packet based on the timestamp of the sampling point where the frame header is located, thereby achieving time synchronization between the receiving end and the sending end.

[0010] Furthermore, the frame detection and capture unit includes a sliding correlation module with a length of 256, an accumulative addition tree decision module, a capture protection decision module, and a counter;

[0011] The sliding correlation module is composed of two shift registers with a length of 1024 and two scrambling code register groups with a length of 256, wherein the shift register is responsible for storing 1024 sampling points to be correlated, and the scrambling code register group stores the first 256 scrambling codes corresponding to the scrambling code number; the quadruple sampling signal of each frame is divided into an I branch signal DinI and a Q branch signal DinQ, and DinI and DinQ are respectively input into the two shift registers as sampling point data to wait for sliding correlation with the scrambling codes in the scrambling code register group, wherein the sampling point data in the two shift registers are respectively downsampled by 4 times to obtain 256 sampling point data, and the two groups of 256 sampling point data are respectively correlated with the 256 scrambling codes in the scrambling code register group and complex multiplication operations are performed to obtain 256 I branch correlation values ​​and 256 Q branch correlation values ​​respectively;

[0012] The cumulative addition tree decision module accumulates the obtained two groups of I branch correlation values ​​and Q branch correlation values ​​respectively using nine-level addition operations, wherein, in the accumulation of each group of branch correlation values, the addition of each level in the first eight levels adopts the principle of adding the head and tail data in pairs, and after the eighth level addition, the two groups of branches respectively complete the accumulation of 256 correlation values, and the ninth level squares the cumulative sum of the two-way correlation values ​​output by the eighth level and then sums them to obtain 1 correlation cumulative value; finally, the correlation cumulative value is compared with the decision threshold configured by the host computer, if the correlation cumulative value is not greater than the decision threshold, the decision result is that the correlation peak of the broadband spread spectrum signal is not captured, and the next frame of quadruple sampling signal is received to continue capturing; if the correlation cumulative value is greater than the decision threshold, the decision result is that the correlation peak of the broadband spread spectrum signal is captured, and the value of the counter corresponding to the current correlation peak value is used as the frame header position of the current frame quadruple sampling signal; wherein the value of the counter is the sampling point sequence number;

[0013] After obtaining the frame header positions of four consecutive frames of quadruple sampling signals, the capture protection judgment module performs a differential operation according to the frame header positions to obtain the differences between the four frame header positions, and uses the three differences as the measured frame intervals. If the differences between the three measured frame intervals and the set frame interval are all within the set threshold range, it is judged that the broadband spread spectrum signal is captured successfully, and the last frame and the subsequent quadruple sampling signals in the four frames of quadruple sampling signals and their corresponding frame header positions are output to the timing synchronization unit; if the differences between the three measured frame intervals and the set frame interval do not meet the set threshold, the next frame of quadruple sampling signal is received to continue capturing.

[0014] Furthermore, the timing synchronization unit includes an NCO module, a Farrow interpolation filter with a variable sampling rate ratio, a lead-lag module, a local scrambling code generation and buffering module, a descrambling module, an error calculation module, an unlocking judgment module, and a loop filtering module;

[0015] The method for the timing synchronization unit to extract the best sampling point from each chip of the received quadruple sampling signal is as follows:

[0016] The NCO module calculates the frequency control word W according to the loop filter module. k Controls the fractional multiple interval μ required for the subsequent Farrow interpolation filter k ; The Farrow interpolation filter is based on the changing μ k Interpolate the received quadruple sampling signal to obtain the interpolated output sampling data Data Farrow ; The lead-lag module outputs the Data Farrow Delay the current branch and the delayed branch by 1 and 2 sampling points respectively, and at the same time, the Data output by the Farrow interpolation filter is Farrow directly treat it as an advanced branch, and send the current branch, the lagging branch, and the advanced branch to the descrambling module; the descrambling module reads the scrambling code generated by the local scrambling code and stored in the cache module, and performs complex correlation operations on the read scrambling code with the sampled data of the advanced branch, the current branch, and the lagging branch to complete the descrambling, and at the same time outputs the descrambling value of the current branch as the optimal sampling point of each code chip of the current quadruple sampling signal to the data packaging unit;

[0017] The error calculation module accumulates the descrambling values ​​of the three branches after descrambling in groups of 512, and then sums the squares of the three branches according to the I and Q paths:

[0018]

[0019] peak1=(peakI1) 2+(peakQ1) 2

[0020] Among them, peakI1 is the in-phase component of the accumulated sum of the leading branch, peakQ1 is the orthogonal component of the accumulated sum of the leading branch, EarlyI i is the in-phase component of the i-th descrambling value of the leading branch, EarlyQ i is the orthogonal component of the i-th descrambling value of the leading branch, ScramI i is the in-phase component of the scrambling code corresponding to the i-th descrambling value, ScramQ i is the orthogonal component of the scrambling code corresponding to the i-th descrambling value, and peak1 is the square sum corresponding to the leading branch;

[0021]

[0022] peak2=(peakI2) 2 +(peakQ2) 2

[0023] Among them, peakI2 is the in-phase component of the current branch accumulation, peakQ2 is the orthogonal component of the current branch accumulation, PresentI i is the in-phase component of the ith descrambled value of the current branch, PresentQ i is the orthogonal component of the i-th descrambling value of the current branch, and peak2 is the square sum corresponding to the current branch;

[0024]

[0025] peak3=(peakI3) 2 +(peakQ3) 2

[0026] Among them, peakI3 is the in-phase component of the accumulated sum of the lag branch, peakQ3 is the orthogonal component of the accumulated sum of the lag branch, DelayI i is the in-phase component of the ith descrambling value of the lag branch, DelayQ i is the orthogonal component of the ith descrambled value of the lag branch, and peak3 is the square sum corresponding to the lag branch;

[0027] Calculate the timing error based on peak1 and peak3:

[0028] error=(peak1-peak3) / (peak1+peak3)

[0029] The lock-out judgment module is used to compare the calculated peak1, peak2, and peak3. If peak2 is always the maximum value among the three, it is determined that the timing synchronization loop in the timing synchronization unit is in a locked state.

[0030] The loop filtering module performs second-order loop filtering on the timing error error. The second-order loop filtering process is shown as follows:

[0031] W k =W k-1 -C1·(error k -error k-1 )-C2·error k

[0032] Among them, C1 and C2 are the second-order loop filter coefficients, W k is the frequency control word used by the quadruple sampling signal of the current frame, W k-1 The frequency control word used by the previous frame of quadruple sampling signal, error k is the timing error corresponding to the quadruple sampling signal of the current frame, errork -1 The timing error corresponding to the previous frame of quadruple sampling signal is updated by continuously iteratively updating the frequency control word W. k The value of W k Update μ k , and then control the output of the Farrow interpolation filter to obtain the optimal sampling point.

[0033] Furthermore, according to W k Update μ k The specific method is:

[0034] Judge n k-1 +W k <1 is true, where n k-1 To determine whether to update μ k The auxiliary variable corresponding to the previous frame of quadruple sampling signal, if n k-1 +W k <1 holds true, then μ of the current frame k Remain unchanged, and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k , and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update; if n k-1 +W k <1 does not hold, then update μ according to the formula k =(1-n k-1 ) / W k, and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k -1, and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update.

[0035] Furthermore, the data packetization unit includes a frame header counter, a packet header identifier preparation module, two RAMs, and a control logic module;

[0036] The method in which the data packaging unit reconstructs the extracted optimal sampling points into a single sampling signal is as follows:

[0037] The frame header counter counts and accumulates according to the frame header position marked on each frame of the quadruple sampling signal corresponding to each group of optimal sampling points received; the two RAMs perform a ping-pong operation, alternating between the odd and even values ​​of the frame header counters to store complete groups of optimal sampling points; the control logic module includes two parts: RAM read enable control logic and state machine control logic; the RAM read enable control logic determines whether the RAM is fully written with a group of optimal sampling points by identifying the write addresses of the two RAMs, thereby ensuring that data fragmentation and data overflow will not occur when accessing the optimal sampling points. The data in a RAM will be read only when and only when a RAM is fully stored with a group of optimal sampling points; the state machine control logic changes the state by determining the RAM read address. Before the first sampling point of each group of optimal sampling points is uploaded to the host computer, packet header information needs to be inserted before the sampling point, where the packet header information includes a start feature word, a timestamp, a packet sequence number, a data type, a carrier number, a channel number, a frame sequence number, a frame header position, and a correlation peak value; finally, the completed single-sampled data packet is output and transmitted to the host computer via the PCIe interface.

[0038] Furthermore, the first pre-processing module at the receiving end includes an AD conversion unit, an orthogonal down-conversion and parallel filtering unit, an accumulative down-sampling filtering unit, a frequency point selection unit, a low-pass filtering unit, a Farrow filtering unit, and a low-pass matched filtering unit;

[0039] The broadband spread spectrum signal is converted into a discrete signal by an AD conversion unit, and then filtered by an orthogonal down-conversion and parallel filtering unit and an accumulative down-sampling filtering unit. Then, a frequency selection unit selects a quadruple sampling signal of a specified frequency from the discrete signal after filtering. The quadruple sampling signal of the specified frequency is finally filtered by a low-pass filtering unit, a Farrow filtering unit, and a low-pass matched filtering unit before being output to a frame detection and capture unit.

[0040] Furthermore, the transmitting end includes a global enabling unit, a PCIE interface FIFO, a data parsing unit, and a second pre-processing module;

[0041] The host computer packages the response signal according to a pre-agreed packet format; the data parsing unit is used to read the response data packet through the PCIE interface FIFO when the global enable unit outputs a valid enable signal; the data parsing unit is used to parse the response data packet and compare the timed transmission timestamp obtained by parsing with the local timestamp output by the local timestamp counter. When the local timestamp used to represent the theoretical transmission time of the response data packet is equal to the timed transmission timestamp used to represent the actual transmission time of the response data packet, the data parsing unit sends the response data packet to the second preprocessing module, and the second preprocessing module converts the response data packet into a broadband spread spectrum signal and transmits it externally.

[0042] Furthermore, the data parsing unit includes a PCIE read enable control logic subunit, a depacketizing subunit, a FIFO, and a timing sending control subunit;

[0043] The depacketizing subunit is used to perform serial-to-parallel conversion on the 128-bit 4-way I, Q parallel data response data packet read from the PCIe interface FIFO, and then identify the packet header information and the data to be processed according to the packet header start feature identifier, wherein the packet header information includes the start feature word, the timed transmission timestamp, the packet sequence number, the data type, the data length, and the end feature word; the timed transmission control subunit is used to compare the parsed timed transmission timestamp with the local timestamp output by the local timestamp counter, and when the local timestamp is equal to the timed transmission timestamp, the packet is sent to the local time stamp counter. , start FIFO read enable; the FIFO is used to store the data to be processed without the header information after the read enable is started; the PCIe read enable control logic subunit determines the amount of parsed data to be processed by detecting the depth of the data already stored in the FIFO. When the depth of the data already stored in the FIFO reaches 3 / 4 of the frame length, reading data from the PCIe interface FIFO is stopped. When the depth in the FIFO is less than 1 / 4 of the frame length, reading data continues, thereby ensuring that the data to be processed in the FIFO is dynamically maintained at 1 / 4 to 3 / 4 of the frame length.

[0044] Furthermore, the second pre-processing module includes a shaping filter unit, a third half-band filter unit I, a Farrow filter unit, a spectrum shift unit, a serial-to-parallel conversion unit, a third half-band filter unit II, and a DA conversion module;

[0045] The response data packet is filtered by the shaping filter unit, the third half-band filter unit I, and the Farrow filter unit in sequence, and then moved to the specified frequency point by the spectrum shifting unit;

[0046] The response data packet moved to the specified frequency point is serial-to-parallel converted by the serial-to-parallel conversion unit, filtered by the third half-band filter II, and then converted into a broadband spread spectrum signal by the DA conversion module and transmitted externally.

[0047] Beneficial effects:

[0048] 1. The present invention provides a device for synchronizing reception and transmission of broadband spread spectrum signals. The first pre-processing module converts each frame of continuous broadband spread spectrum signals into a discrete quadruple sampling signal. Each sampling point on the quadruple sampling signal corresponds to a timestamp provided by a local timestamp counter. The frame detection and capture unit then determines whether the difference between the measured frame interval and the set frame interval between adjacent frames in the four consecutive frames of quadruple sampling signals is within a set threshold range. The timing synchronization unit is used to extract the best sampling point from each code chip of the received quadruple sampling signal. The data packaging unit is used to reassemble the extracted best sampling points into a single The double-sampling data packet is sent to the host computer; the host computer is used to parse the single-sampling data packet, and predict the time when the sending end sends the response signal in response to the single-sampling data packet based on the timestamp of the sampling point where the frame header is located, so as to achieve time synchronization between the receiving end and the sending end; it can be seen that the present invention uses a local timestamp counter independent of the sending and receiving, and connects the time streams of the receiving end and the sending end in series through the timestamp, so that the timestamp is synchronized in the entire process of signal reception and transmission, and can accurately control the synchronization of reception and transmission, and thus can receive and send user data of multiple parallel channels under the same FPGA on-chip resource consumption.

[0049] 2. The present invention provides a synchronous device for receiving and sending broadband spread spectrum signals, including a receiving end AD that completes signal sampling and sequentially passes the sampled data through orthogonal down-conversion and parallel filtering, cumulative downsampling / filtering, frequency selection, low-pass filtering, Farrow sampling rate conversion, matched filtering, frame detection and capture, timing synchronization and descrambling, packet assembly and other modules to complete the processing of the signal on the downlink receiving side and upload it to the host computer through the PCIE interface; the transmitting end obtains the user data that the host computer needs to send through the PCIE, and sequentially passes the data through data analysis, shaping filtering, 3-times half-band filtering upsampling, Farrow sampling rate conversion, frequency selection, serial-to-parallel conversion, 3-times half-band filtering upsampling, DA and other modules to complete the processing of the uplink transmission signal. Timestamp synchronization is present in the entire process of signal reception and transmission, and the synchronization of reception and transmission can be accurately controlled.

[0050] 3. The present invention provides a synchronous device for receiving and transmitting broadband spread spectrum signals, which folds the data and performs multiplication and addition operations with the filter coefficients to achieve the equivalent of the convolution operation of the filter, thereby significantly reducing the consumption of FPGA resources. In addition, the frame detection and capture module adopts a solution with flexible and configurable correlation length and correlation operation bit number to further reduce the resources consumed by the FPGA to implement the correlation operation.

[0051] 4. The present invention provides a synchronous device for receiving and transmitting broadband spread spectrum signals. The transmitting end can complete the timing transmission function with an accuracy of 8 nanoseconds. If the timestamp is not compensated for accuracy when it is calculated in each module, the maximum accuracy that can be achieved under a 125M clock is theoretically 1ns.

[0052] 5. The present invention provides a device for synchronously receiving and transmitting a broadband spread spectrum signal, which uses a frequency control word W k Update μ k , and then control the Farrow interpolation filter to obtain the best sampling point, that is, the present invention uses a variable sampling rate ratio μ k This method enables the input and output signals to be accurately converted into fractional sampling rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a structural block diagram of a device for synchronizing reception and transmission of broadband spread spectrum signals according to the present invention;

[0054] Figure 2 This is a block diagram of the orthogonal down-conversion principle of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0055] Figure 3 This is a block diagram of the parallel filtering principle of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0056] Figure 4 This is a block diagram of the principle of cumulative downsampling / filtering of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0057] Figure 5 This is a block diagram of the frequency point selection principle of the receiving and transmitting synchronization device for broadband spread spectrum signals of the present invention;

[0058] Figure 6 This is a block diagram of the Farrow sampling rate conversion principle of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0059] Figure 7 This is a block diagram of the frame detection and capture principle of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0060] Figure 8 This is a block diagram of the timing synchronization and descrambling principle of the receiving and transmitting synchronization device for broadband spread spectrum signals of the present invention;

[0061] Figure 9 This is a block diagram of the principle of the packet assembly module of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0062] Figure 10 This is a structural block diagram of a device for synchronizing reception and transmission of broadband spread spectrum signals according to the present invention;

[0063] Figure 11 This is a structural block diagram of a data parsing module of a broadband spread spectrum signal receiving and transmitting synchronization device of the present invention;

[0064] Figure 12 This is a block diagram of the synchronous processing structure of receiving and sending timestamps of the broadband spread spectrum signal receiving and sending synchronization device of the present invention;

[0065] Figure 13 Schematic diagram of data and timestamp processing of the Farrow module of the broadband spread spectrum signal receiving and transmitting synchronization device of the present invention. DETAILED DESCRIPTION

[0066] In order to enable people skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0067] like Figure 1 As shown, a receiving and transmitting synchronization device for a broadband spread spectrum signal includes a receiving end, a host computer, a transmitting end, and a local timestamp counter; wherein the receiving end includes a first preprocessing module, a frame detection and capture unit, a timing synchronization unit, and a data packetization unit; the local timestamp counter is composed of a counter with an 8ns precision, and each sampling point corresponds to a timestamp value at the AD end, thereby completing the receiving and transmitting synchronization.

[0068] The first preprocessing module converts each frame of continuous broadband spread spectrum signals into discrete quadruple-sampled signals, wherein each sampling point of the quadruple-sampled signal corresponds to a timestamp provided by a local timestamp counter; each frame of the quadruple-sampled signal includes multiple chips, each chip includes four sampling points, and data obtained by sampling each designated frequency point on the broadband spread spectrum signal four times is used as the signal of the four sampling points of the same chip;

[0069] The frame detection and capture unit is used to determine whether the difference between the measured frame interval and the set frame interval between adjacent frames in four consecutive frames of quadruple sampling signals is within a set threshold range. If so, it indicates that the broadband spread spectrum signal is successfully captured, and outputs the quadruple sampling signals of the last frame and subsequent frames in the four frames of quadruple sampling signals to the timing synchronization unit;

[0070] The timing synchronization unit is used to extract the best sampling point from each chip of the received quadruple sampling signal;

[0071] The data packaging unit is used to reorganize the extracted optimal sampling points into single sampling data packets and send them to the host computer;

[0072] The host computer is used to parse the single sampling data packet and predict the time when the sending end sends the response signal in response to the single sampling data packet based on the timestamp of the sampling point where the frame header is located, thereby achieving time synchronization between the receiving end and the sending end.

[0073] Furthermore, the first pre-processing module at the receiving end includes an AD conversion unit, an orthogonal down-conversion and parallel filtering unit, an accumulative down-sampling filtering unit, a frequency point selection unit, a low-pass filtering unit, a Farrow filtering unit, and a low-pass matched filtering unit;

[0074] The broadband spread spectrum signal is converted into a discrete signal by an AD conversion unit, and then filtered by an orthogonal down-conversion and parallel filtering unit and an accumulative down-sampling filtering unit. Then, a frequency selection unit selects a quadruple sampling signal of a specified frequency from the discrete signal after filtering. The quadruple sampling signal of the specified frequency is finally filtered by a low-pass filtering unit, a Farrow filtering unit, and a low-pass matched filtering unit before being output to a frame detection and capture unit.

[0075] like Figure 2 As shown, in this embodiment, the orthogonal down-conversion module is composed of 16 address accumulators, 1 sine and cosine phase lookup table, and 16 multipliers. When the frequency control word is given, 16 parallel continuous addresses can be obtained as the address shift register continuously accumulates in a loop. The sine and cosine phase lookup table can generate 16 parallel sine and cosine signals with continuous phases according to the parallel continuous addresses. The multiplier completes the multiplication of the input data and the sine and cosine signals to generate the final output data. In other words, the parallel NCO generates 16 parallel sine and cosine signals of the specified frequency. The multiplier performs orthogonal down-conversion by multiplying the received 16 parallel AD sampling data with the signal generated by the parallel NCO to obtain I and Q data.

[0076] like Figure 3As shown, in this embodiment, the parallel filtering module is composed of 1 data shift register, 1 filter coefficient register, 16 multipliers and adders; the shift unit of the data shift register is 16, that is, 16 parallel data are input at a time; the filter coefficient register stores 32 symmetrical filter coefficients; the parallel filtering operation is achieved by fixing the data shift register and right-shifting the filter coefficient register to complete the multiplication and addition operation; since the filter coefficient is a symmetrical structure, the multiplication and addition operation is implemented by an addition tree, so in this embodiment, the data multiplied with the same filter coefficient is added in the first digit and then multiplied with the filter coefficient to reduce the consumption of FPGA resources; that is, the shift register and the multiplier complete the multiplication of the parallel signal and the filter coefficient; the accumulator implements the accumulation and output of the multiplied parallel data through the addition tree.

[0077] like Figure 4 As shown, in this embodiment, the cumulative downsampling / filtering module consists of two cumulative four-fold downsampling modules and one parallel filtering module, which can meet the 16-fold downsampling requirement of the receiving end containing a four-frequency signal; the parallel filtering module has a similar structure to the aforementioned parallel filtering module; two four-fold cumulative downsampling modules complete 64-fold downsampling of the signal;

[0078] like Figure 5 As shown, in this embodiment, the frequency selection module consists of a read-write register that interacts with the host computer, an NCO, four multipliers, and two adders; the NCO generates sin and cos signals of the corresponding frequency according to the frequency information configured by the host computer; the read-write register is a 32-bit register cascaded with the spectrum shift controller and the NCO to control the multiplier sign of the multiplier and the frequency of the sin and cos signals generated by the NCO; the NCO generates a serial sin and cos signal of the specified frequency; the multiplier performs spectrum shifting of the signal; the multiplier and adder perform complex multiplication operations of the signal with sin and cos as follows:

[0079] (DinI+j·DinQ)·ejωt=(DinI+j·DinQ)(cosωt+j·sinωt)

[0080] =(DinI·cosωt-DinQ·sinωt))+j·(DinI·sinωt+DinQ·cosωt)

[0081] like Figure 6 As shown, in this embodiment, the Farrow sampling rate conversion module includes an NCO and an interpolator; the NCO is used to calculate the decimal interpolation interval μ according to the sampling rate conversion ratio. k Control interpolator to interpolate, μ k The iterative update process is as follows:

[0082] Judge n k-1 +W k <1 is true, where n k-1 To determine whether to update μ k The auxiliary variable corresponding to the previous frame of quadruple sampling signal, if n k-1 +W k <1 holds true, then μ of the current frame k Remain unchanged, and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k , and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update; if n k-1 +W k <1 does not hold, then update μ according to the formula k =(1-n k-1 ) / W k , and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k -1, and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update.

[0083] Among them, W k To utilize μ k To update the frequency control word, the interpolator uses μ k Perform decimal multiple linear interpolation on the input data to complete the sampling rate conversion;

[0084] like Figure 7 As shown, in this embodiment, the data entering the frame detection and capture unit is 4 times the sampling data, that is, one chip corresponds to 4 sampling points; specifically, the frame detection and capture unit includes a sliding correlation module with a length of 256, an accumulation adder tree decision module, a capture protection decision module, and a counter;

[0085] The sliding correlation module is composed of two shift registers with a length of 1024 and two scrambling code register groups with a length of 256, wherein the shift register is responsible for storing 1024 sampling points to be correlated, and the scrambling code register group stores the first 256 scrambling codes corresponding to the scrambling code number; the quadruple sampling signal of each frame is divided into an I branch signal DinI and a Q branch signal DinQ, and DinI and DinQ are respectively input into the two shift registers as sampling point data to wait for sliding correlation with the scrambling codes in the scrambling code register group, wherein the sampling point data in the two shift registers are respectively downsampled by 4 times to obtain 256 sampling point data, and the two groups of 256 sampling point data are respectively correlated with the 256 scrambling codes in the register group to perform complex multiplication operations to obtain 256 I branch correlation values ​​and 256 Q branch correlation values ​​respectively;

[0086] The cumulative addition tree decision module accumulates the obtained two groups of I branch correlation values ​​and Q branch correlation values ​​respectively using nine-level addition operations, wherein, in the accumulation of each group of branch correlation values, the addition of each level in the first eight levels adopts the principle of adding the head and tail data in pairs, and after the eighth level addition, the two groups of branches respectively complete the accumulation of 256 correlation values, and the ninth level squares the cumulative sum of the two-way correlation values ​​output by the eighth level and then sums them to obtain 1 correlation cumulative value; finally, the correlation cumulative value is compared with the decision threshold configured by the host computer, if the correlation cumulative value is not greater than the decision threshold, the decision result is that the correlation peak of the broadband spread spectrum signal is not captured, and the next frame of quadruple sampling signal is received to continue capturing; if the correlation cumulative value is greater than the decision threshold, the decision result is that the correlation peak of the broadband spread spectrum signal is captured, and the value of the counter corresponding to the current correlation peak value is used as the frame header position of the current frame quadruple sampling signal; wherein the value of the counter is the sampling point sequence number;

[0087] After obtaining the frame header positions of four consecutive frames of quadruple sampling signals, the capture protection judgment module performs a differential operation according to the frame header positions to obtain the differences between the four frame header positions, and uses the three differences as the measured frame intervals. If the differences between the three measured frame intervals and the set frame interval are all less than the set threshold, it is judged that the broadband spread spectrum signal is successfully captured, and the last frame of the four quadruple sampling signals and its corresponding frame header position are output to the timing synchronization unit; if the differences between the three measured frame intervals and the set frame interval do not meet the set threshold, the next frame of the quadruple sampling signal is received to continue capturing.

[0088] That is, the local scrambling code generation module in the frame detection and capture unit generates a scrambling code corresponding to the scrambling code number using a circular shift register according to the information of the read-write register; the correlation calculation module performs 256 conjugate multiplication operations on the input I and Q signals and the locally generated scrambling code; the accumulation module accumulates the 256 accumulated correlation results through an addition tree; the capture protection module compares the correlation result with the decision threshold to determine whether the frame header is captured, and determines the frame header position based on the maximum position after the correlation result is greater than the threshold. When the interval between three consecutive captured frame header positions is greater than 1, the frame header position is determined. Capture is determined to be successful when the length of one frame is met; the capture failure judgment module consists of a counter and a reset module. The counter is reset each time a frame header is captured. If the frame header cannot be captured for three consecutive frames, that is, the counter value is greater than a certain threshold, it is determined that the capture has been lost, and the reset module is activated to reset the module and subsequent modules; the signal-to-noise ratio calculation module consists of an accumulator and a divider; the accumulator completes the accumulation of eight consecutive background noise correlation values ​​after the frame header is captured; the divider completes the division operation of the frame header correlation peak and the accumulated sum of the eight background noises to obtain the signal-to-noise ratio.

[0089] like Figure 8 As shown, in this embodiment, the data entering the timing synchronization module is 4 times the sampled data that is successfully captured and marked with the frame header position, so the timing synchronization module can align the sampled data with the locally generated scrambling code according to the frame header position mark; specifically, the timing synchronization unit includes an NCO module, a Farrow interpolation filter with a variable sampling rate ratio, a lead-lag module, a local scrambling code generation and cache module, a descrambling module, an error calculation module, an unlocking judgment module, and a loop filtering module; the scrambling code cache module includes a memory and an output controller;

[0090] The method for the timing synchronization unit to extract the best sampling point from each chip of the received quadruple sampling signal is as follows:

[0091] The NCO module calculates the frequency control word W according to the loop filter module. k Controls the fractional multiple interval μ required for the subsequent Farrow interpolation filter k ; The Farrow interpolation filter is based on the changing μ k Interpolate the received quadruple sampling signal to obtain the interpolated output sampling data Data Farrow ; The lead-lag module outputs the Data Farrow Delay the current branch and the delayed branch by 1 and 2 sampling points respectively, and at the same time, the Data output by the Farrow interpolation filter is Farrowdirectly treat it as an advanced branch, and send the current branch, the lagging branch, and the advanced branch to the descrambling module; the descrambling module reads the scrambling code generated by the local scrambling code and stored in the cache module, and performs complex correlation operations on the read scrambling code with the sampled data of the advanced branch, the current branch, and the lagging branch to complete the descrambling, and at the same time outputs the descrambling value of the current branch as the optimal sampling point of each code chip of the current quadruple sampling signal to the data packaging unit;

[0092] The error calculation module accumulates the descrambling values ​​of the three branches after descrambling in groups of 512, and then sums the squares of the three branches according to the I and Q paths:

[0093]

[0094] peak1=(peakI1) 2 +(peakQ1) 2

[0095] Among them, peakI1 is the in-phase component of the accumulated sum of the leading branch, peakQ1 is the orthogonal component of the accumulated sum of the leading branch, EarlyI i is the in-phase component of the i-th descrambling value of the leading branch, EarlyQ i is the orthogonal component of the i-th descrambling value of the leading branch, ScramI i is the in-phase component of the scrambling code corresponding to the i-th descrambling value, ScramQ i is the orthogonal component of the scrambling code corresponding to the i-th descrambling value, and peak1 is the square sum corresponding to the leading branch;

[0096]

[0097] peak2=(peakI2) 2 +(peakQ2) 2

[0098] Among them, peakI2 is the in-phase component of the current branch accumulation, peakQ2 is the orthogonal component of the current branch accumulation, PresentI i is the in-phase component of the ith descrambled value of the current branch, PresentQ i is the orthogonal component of the i-th descrambling value of the current branch, and peak2 is the square sum corresponding to the current branch;

[0099]

[0100] peak3=(peakI3) 2 +(peakQ3) 2

[0101] Among them, peakI3 is the in-phase component of the accumulated sum of the lag branch, peakQ3 is the orthogonal component of the accumulated sum of the lag branch, DelayI i is the in-phase component of the ith descrambling value of the lag branch, DelayQ i is the orthogonal component of the ith descrambled value of the lag branch, and peak3 is the square sum corresponding to the lag branch;

[0102] Calculate the timing error based on peak1 and peak3:

[0103] error=(peak1-peak3) / (peak1+peak3)

[0104] The lock-loss judgment module is used to compare the calculated peak1, peak2, and peak3. If peak2 is always the maximum value among the three, it is determined that the timing synchronization loop in the timing synchronization unit is in a locked state. Because the current branch and the local scrambling code are completely aligned when the timing loop is in a locked state and the error calculation is performed, while the leading and lagging branches have a half-chip deviation from the local scrambling code, the accumulated peak value will be smaller than the accumulated value peak2 of the current branch.

[0105] The loop filtering module performs second-order loop filtering on the timing error error. The second-order loop filtering process is shown as follows:

[0106] W k =W k-1 -C1·(error k -error k-1 )-C2error k

[0107] Among them, C1 and C2 are the second-order loop filter coefficients, W k is the frequency control word used by the quadruple sampling signal of the current frame, W k-1 The frequency control word used by the previous frame of quadruple sampling signal, error k is the timing error corresponding to the quadruple sampling signal of the current frame, error k-1 The timing error corresponding to the previous frame of quadruple sampling signal is updated by continuously iteratively updating the frequency control word W. k The value of W k Update μ k , and then control the output of the Farrow interpolation filter to obtain the optimal sampling point.

[0108] According to W k Update μ k The specific method is:

[0109] Judge n k-1 +Wk <1 is true, where n k-1 To determine whether to update μ k The auxiliary variable corresponding to the previous frame of quadruple sampling signal, if n k-1 +W k <1 holds true, then μ of the current frame k Remain unchanged, and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k , and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update; if n k-1 +W k <1 does not hold, then update μ according to the formula k =(1-n k-1 ) / W k , and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k -1, and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update.

[0110] like Figure 9 As shown, in this embodiment, the data entering the packetization module is single-sampled data with the frame header position marked and descrambled. Specifically, the data packetization unit includes a frame header counter, a packet header identifier preparation module, two RAMs, a FIFO, and a control logic module. The method by which the data packetization unit reconstructs the extracted optimal sampling points into a single-sampled signal is as follows:

[0111] The frame header counter counts and accumulates according to the frame header position marked on each frame of the quadruple sampling signal corresponding to each group of optimal sampling points received; the two RAMs perform a ping-pong operation, alternating between the odd and even values ​​of the frame header counters to store complete groups of optimal sampling points; the control logic module includes two parts: RAM read enable control logic and state machine control logic; the RAM read enable control logic determines whether the RAM is fully written with a group of optimal sampling points by identifying the write addresses of the two RAMs, thereby ensuring that data fragmentation and data overflow will not occur when accessing the optimal sampling points. The data in a RAM will be read only when and only when a RAM is fully stored with a group of optimal sampling points; the state machine control logic changes the state by determining the RAM read address. Before the first sampling point of each group of optimal sampling points is uploaded to the host computer, packet header information needs to be inserted before the sampling point, where the packet header information includes a start feature word, a timestamp, a packet sequence number, a data type, a carrier number, a channel number, a frame sequence number, a frame header position, and a correlation peak value; finally, the completed single-sampled data packet is output and transmitted to the host computer via the PCIe interface.

[0112] That is, the frame header counter records the number of frames input into the module; the two memories and the corresponding control logic complete the ping-pong caching of the data output by the timing synchronization and descrambling modules, and then add a packet header identifier to the cached data; the FIFO is responsible for performing arbitrary rate control on the data after the package is completed to meet the data read and write rate requirements of the PICie interface.

[0113] like Figure 10 As shown, the transmitting end includes a global enabling unit, a PCIE interface FIFO, a data parsing unit, and a second pre-processing module; the host computer packages the response signal according to a pre-agreed packet format; the data parsing unit is used to read the response data packet through the PCIE interface FIFO when the global enabling unit outputs a valid enabling signal; the data parsing unit is used to parse the response data packet and compare the timed sending timestamp obtained by parsing with the local timestamp output by the local timestamp counter. When the local timestamp used to represent the theoretical sending time of the response data packet is equal to the timed sending timestamp used to represent the actual sending time of the response data packet, the data parsing unit sends the response data packet to the second pre-processing module, and the second pre-processing module converts the response data packet into a broadband spread spectrum signal and transmits it externally.

[0114] like Figure 11As shown, in this embodiment, the host computer packages the data according to the pre-agreed packet format and stores the data packets in the FIFO through the PCIE interface. After the FPGA is enabled, the data is read from the FIFO through the read-write logic. Specifically, the data parsing unit includes a PCIE read enable control logic subunit, a depacketizing subunit, a FIFO, and a timed transmission control subunit.

[0115] The depacketizing subunit is used to perform serial-to-parallel conversion on the 128-bit 4-way I, Q parallel data response data packet read from the PCIe interface FIFO, and then identify the packet header information and the data to be processed according to the packet header start feature identifier, wherein the packet header information includes the start feature word, the timed transmission timestamp, the packet sequence number, the data type, the data length, and the end feature word; the timed transmission control subunit is used to compare the parsed timed transmission timestamp with the local timestamp output by the local timestamp counter, and when the local timestamp is equal to the timed transmission timestamp, the F is started. The IFO is read enabled to output data; the FIFO is used to store the data to be processed without the header information after the read enable is started; the PCIE read enable control logic subunit determines the amount of parsed data to be processed by detecting the depth of the data already stored in the FIFO. When the depth of the data already stored in the FIFO reaches 3 / 4 of the frame length, reading data from the PCIE interface FIFO is stopped; when the depth in the FIFO is less than 1 / 4 of the frame length, reading data continues, thereby ensuring that the data to be processed in the FIFO is dynamically maintained at 1 / 4 to 3 / 4 of the frame length.

[0116] It should be noted that the subsequent upsampling and filtering processing uses CIC and FIR IP cores, and finally the data is upsampled to 250M and sent out via DA. Specifically, the second pre-processing module includes a shaping filter unit, a third half-band filter unit I, a Farrow filter unit, a spectrum shift unit, a serial-to-parallel conversion unit, a third half-band filter unit II, and a DA conversion module.

[0117] The response data packet is filtered by the shaping filter unit, the third half-band filter unit I, and the Farrow filter unit in sequence, and then moved to the specified frequency point by the spectrum shifting unit;

[0118] The response data packet moved to the specified frequency point is serial-to-parallel converted by the serial-to-parallel conversion unit, filtered by the third half-band filter II, and then converted into a broadband spread spectrum signal by the DA conversion module and transmitted externally.

[0119] like Figure 12As shown, in this embodiment, the timestamp counter that is independent of the uplink and downlink signal processing links is enabled by the AD output data valid signal to ensure that each sampling point of the AD output has one and only one definite on-chip local timestamp corresponding to it. Since the on-chip clock frequency in this embodiment is 125MHz, the accuracy of the local timestamp is 8ns. The timestamp is strictly aligned with the data and is also input into the downlink processing module. Except for the Farrow module, the processing of the timestamp only needs to calculate the processing delay of each module on the data and perform equal delay processing on the timestamp; the processing of the timestamp by the Farrow module needs to treat the timestamp as a data sampling point for interpolation processing, because the interpolation of the data sampling point will change the on-chip time corresponding to the original sampling point, so the timestamp also needs to be updated to the interpolated time. Since the Farrow module uses linear interpolation, the timestamp can be linearly interpolated like the data, such as Figure 13 As shown. In addition, if resource overhead is not saved and the timestamp accuracy is retained, the Farrow module output timestamp accuracy is 1ns. After the timestamp enters the frame detection and capture module, as the capture continues, the capture module will record the frame header timestamp position and package it together with the descrambled sampling point of the frame and upload it to the host computer. The host computer can obtain the frame header time of the downlink capture by parsing the packet header information, and use this time to predict and guide the FPGA's uplink timing transmission, thereby completing the synchronization of uplink and downlink signals.

[0120] In summary, the workflow of the present invention is as follows:

[0121] The receiving end AD completes the sampling of the signal and sequentially passes the sampled data through orthogonal down-conversion and parallel filtering, cumulative down-sampling / filtering, frequency selection, low-pass filtering, Farrow sampling rate conversion, matched filtering, frame detection and capture, timing synchronization and descrambling, and the packet assembly module to complete the signal processing on the downlink receiving side and upload it to the host computer through the PCB interface;

[0122] The FPGA at the transmitting end obtains the user data that the host computer needs to send through PCB, and then processes the data through unpacking and data buffering, shaping filtering, 3-times half-band filtering upsampling I, Farrow sampling rate conversion, frequency selection, serial-to-parallel conversion, 3-times half-band filtering upsampling II, and DA module to complete the processing of the uplink transmission signal;

[0123] Among them, the unpacking and data caching module consists of a PCIe read-write control module, a unpacking module, a FIFO, and an NCO; the PCIe read-write control module completes the requirement of synchronous and timely transmission according to the timestamps of uplink and downlink synchronization; the unpacking module identifies the packet header identifier to obtain packet header information; the FIFO stores the unpacked data and reads it out at a fixed sampling rate; the NCO generates a fixed-rate read signal to complete data output.

[0124] It can be seen that compared with traditional broadband signal transceiver systems, the present invention can receive and send user data from more parallel channels with the same FPGA on-chip resource consumption; the transmitting end can complete the timing transmission function with an accuracy of 8 nanoseconds. If the timestamp is not compensated for accuracy when it is calculated in each module, the maximum accuracy that can be achieved at a 125M clock is theoretically 1ns.

[0125] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may of course make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A device for synchronizing reception and transmission of a broadband spread spectrum signal, characterized in that: It includes a receiving end, a host computer, a sending end, and a local timestamp counter; wherein the receiving end includes a first pre-processing module, a frame detection and capture unit, a timing synchronization unit, and a data packaging unit; The first preprocessing module converts each frame of continuous broadband spread spectrum signals into discrete quadruple-sampled signals, wherein each sampling point in the quadruple-sampled signal corresponds to a timestamp provided by a local timestamp counter; each frame of the quadruple-sampled signal includes multiple chips, each chip includes four sampling points, and data obtained by sampling each designated frequency point of the broadband spread spectrum signal four times is used as the signal of the four sampling points of the same chip; The frame detection and capture unit is used to determine whether the difference between the measured frame interval and the set frame interval between adjacent frames in four consecutive frames of quadruple sampling signals is within a set threshold range. If so, it indicates that the broadband spread spectrum signal is successfully captured, and outputs the quadruple sampling signals of the last frame and subsequent frames in the four frames of quadruple sampling signals to the timing synchronization unit; The timing synchronization unit is used to extract the best sampling point from each chip of the received quadruple sampling signal; The data packaging unit is used to reorganize the extracted optimal sampling points into single sampling data packets and send them to the host computer; The host computer is used to parse the single sampling data packet and predict the time when the sending end sends the response signal in response to the single sampling data packet based on the timestamp of the sampling point where the frame header is located, thereby achieving time synchronization between the receiving end and the sending end.

2. A broadband spread spectrum signal receiving and transmitting synchronization device as claimed in claim 1, characterized in that: The frame detection and capture unit includes a sliding correlation module with a length of 256, an accumulative addition tree decision module, a capture protection decision module, and a counter; The sliding correlation module is composed of two shift registers with a length of 1024 and two scrambling code register groups with a length of 256, wherein the shift register is responsible for storing 1024 sampling points to be correlated, and the scrambling code register group stores the first 256 scrambling codes corresponding to the scrambling code number; the quadruple sampling signal of each frame is divided into an I branch signal DinI and a Q branch signal DinQ, and DinI and DinQ are respectively input into the two shift registers as sampling point data to wait for sliding correlation with the scrambling codes in the scrambling code register group, wherein the sampling point data in the two shift registers are respectively downsampled by 4 times to obtain 256 sampling point data, and the two groups of 256 sampling point data are respectively correlated with the 256 scrambling codes in the scrambling code register group and complex multiplication operations are performed to obtain 256 I branch correlation values ​​and 256 Q branch correlation values ​​respectively; The cumulative addition tree decision module accumulates the obtained two groups of I branch correlation values ​​and Q branch correlation values ​​respectively using nine-level addition operations, wherein, in the accumulation of each group of branch correlation values, the addition of each level in the first eight levels adopts the principle of adding the head and tail data in pairs, and after the eighth level addition, the two groups of branches respectively complete the accumulation of 256 correlation values, and the ninth level squares the cumulative sum of the two-way correlation values ​​output by the eighth level and then sums them to obtain 1 correlation cumulative value; finally, the correlation cumulative value is compared with the decision threshold configured by the host computer, if the correlation cumulative value is not greater than the decision threshold, the decision result is that the correlation peak of the broadband spread spectrum signal is not captured, and the next frame of quadruple sampling signal is received to continue capturing; if the correlation cumulative value is greater than the decision threshold, the decision result is that the correlation peak of the broadband spread spectrum signal is captured, and the value of the counter corresponding to the current correlation peak value is used as the frame header position of the current frame quadruple sampling signal; wherein the value of the counter is the sampling point sequence number; After obtaining the frame header positions of four consecutive frames of quadruple sampling signals, the capture protection judgment module performs a differential operation according to the frame header positions to obtain the differences between the four frame header positions, and uses the three differences as the measured frame intervals. If the differences between the three measured frame intervals and the set frame interval are all within the set threshold range, it is judged that the broadband spread spectrum signal is captured successfully, and the last frame and the subsequent quadruple sampling signals in the four frames of quadruple sampling signals and their corresponding frame header positions are output to the timing synchronization unit; if the differences between the three measured frame intervals and the set frame interval do not meet the set threshold, the next frame of quadruple sampling signal is received to continue capturing.

3. The apparatus for synchronously transmitting and receiving a broadband spread spectrum signal according to claim 1, wherein: The timing synchronization unit includes an NCO module, a Farrow interpolation filter with a variable sampling rate ratio, a lead-lag module, a local scrambling code generation and buffering module, a descrambling module, an error calculation module, a loss of lock judgment module, and a loop filter module; The method for the timing synchronization unit to extract the best sampling point from each chip of the received quadruple sampling signal is as follows: The NCO module calculates the frequency control word W according to the loop filter module. k Controls the fractional multiple interval μ required for the subsequent Farrow interpolation filter k ; The Farrow interpolation filter is based on the changing μ k Interpolate the received quadruple sampling signal to obtain the interpolated output sampling data Data Farrow ; The lead-lag module outputs the Data Farrow Delay the current branch and the delayed branch by 1 and 2 sampling points respectively, and at the same time, the Data output by the Farrow interpolation filter is Farrow directly treat it as an advanced branch, and send the current branch, the lagging branch, and the advanced branch to the descrambling module; the descrambling module reads the scrambling code generated by the local scrambling code and stored in the cache module, and performs complex correlation operations on the read scrambling code with the sampled data of the advanced branch, the current branch, and the lagging branch to complete the descrambling, and at the same time outputs the descrambling value of the current branch as the optimal sampling point of each code chip of the current quadruple sampling signal to the data packaging unit; The error calculation module accumulates the descrambling values ​​of the three branches after descrambling in groups of 512, and then sums the squares of the three branches according to the I and Q paths: peak1=(PeakI1) 2 +(peakQ1) 2 Among them, peakI1 is the in-phase component of the accumulated sum of the leading branch, peakQ1 is the orthogonal component of the accumulated sum of the leading branch, EarlyI i is the in-phase component of the i-th descrambling value of the leading branch, EarlyQ i is the orthogonal component of the i-th descrambling value of the leading branch, ScramI i is the in-phase component of the scrambling code corresponding to the i-th descrambling value, ScramQ i is the orthogonal component of the scrambling code corresponding to the i-th descrambling value, and peak1 is the square sum corresponding to the leading branch; peak2=(peakI2) 2 +(peakQ2) 2 Among them, peakI2 is the in-phase component of the current branch accumulation, peakQ2 is the orthogonal component of the current branch accumulation, PresentI i is the in-phase component of the ith descrambled value of the current branch, PresentQ i is the orthogonal component of the i-th descrambling value of the current branch, and peak2 is the square sum corresponding to the current branch; peak3=(peakI3) 2 +(peakQ3) 2 Among them, peakI3 is the in-phase component of the accumulated sum of the lag branch, peakQ3 is the orthogonal component of the accumulated sum of the lag branch, DelayI i is the in-phase component of the ith descrambling value of the lag branch, DelayQ i is the orthogonal component of the ith descrambled value of the lag branch, and peak3 is the square sum corresponding to the lag branch; Calculate the timing error based on peak1 and peak3: error=(peak1-peak3) / (peak1+peak3) The lock-out judgment module is used to compare the calculated peak1, peak2, and peak3. If peak2 is always the maximum value among the three, it is determined that the timing synchronization loop in the timing synchronization unit is in a locked state. The loop filtering module performs second-order loop filtering on the timing error error. The second-order loop filtering process is shown as follows: W k =W k-1 -C1·(error k -error k-1 )-C2·error k Among them, C1 and C2 are the second-order loop filter coefficients, W k is the frequency control word used by the current frame quadruple sampling signal, W k-1 The frequency control word used by the previous frame of quadruple sampling signal, error k is the timing error corresponding to the quadruple sampling signal of the current frame, error k-1 The timing error corresponding to the previous frame of quadruple sampling signal is updated by continuously iteratively updating the frequency control word W. k The value of W k Update μ k , and then control the output of the Farrow interpolation filter to obtain the optimal sampling point.

4. The apparatus for synchronizing reception and transmission of a broadband spread spectrum signal according to claim 3, wherein: According to W k Update μ k The specific method is: Judge n k-1 +W k <1 is true, where n k-1 To determine whether to update μ k The auxiliary variable corresponding to the previous frame of quadruple sampling signal, if n k-1 +W k <1 holds true, then μ of the current frame k Remain unchanged, and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k , and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update; if n k-1 +W k <1 does not hold, then update μ according to the formula k =(1-n k-1 ) / W k , and calculate the auxiliary variable n corresponding to the next frame of quadruple sampling signal k =n k-1 +W k -1, and n k Used to determine the μ corresponding to the next frame of quadruple sampling signal k+1 Whether to update.

5. The apparatus for synchronously receiving and transmitting a broadband spread spectrum signal according to claim 1, wherein: The data packetization unit includes a frame header counter, a packet header identifier preparation module, two RAMs, and a control logic module; The method in which the data packaging unit reconstructs the extracted optimal sampling points into a single sampling signal is as follows: The frame header counter counts and accumulates the frame header positions marked on the quadruple sampling signals of each frame corresponding to each group of optimal sampling points received; the two RAMs perform a ping-pong operation to store the complete groups of optimal sampling points in alternating order according to the odd and even values ​​of the frame header counters; The control logic module includes two parts: RAM read enable control logic and state machine control logic. The RAM read enable control logic determines whether the RAM is fully written with a set of optimal sampling points by identifying the write addresses of two RAM blocks, thereby ensuring that data fragmentation and data overflow will not occur when accessing the optimal sampling points. The data of a RAM block will be read out only when the RAM block is fully filled with a set of optimal sampling points. The state machine control logic changes the state by determining the read address of the RAM. Before the first sampling point of each set of optimal sampling points is uploaded to the host computer, packet header information needs to be inserted before the sampling point, where the packet header information includes a start feature word, a timestamp, a packet sequence number, a data type, a carrier number, a channel number, a frame sequence number, a frame header position, and a correlation peak value. Finally, the single-sampled data packet after the package is completed is output and transmitted to the host computer through the PCIe interface.

6. The apparatus for synchronously transmitting and receiving a broadband spread spectrum signal according to claim 1, wherein: The first pre-processing module at the receiving end includes an AD conversion unit, an orthogonal down-conversion and parallel filtering unit, an accumulative down-sampling filtering unit, a frequency point selection unit, a low-pass filtering unit, a Farrow filtering unit, and a low-pass matched filtering unit; The broadband spread spectrum signal is converted into a discrete signal by an AD conversion unit, and then filtered by an orthogonal down-conversion and parallel filtering unit and an accumulative down-sampling filtering unit. Then, a frequency selection unit selects a quadruple sampling signal of a specified frequency from the discrete signal after filtering. The quadruple sampling signal of the specified frequency is finally filtered by a low-pass filtering unit, a Farrow filtering unit, and a low-pass matched filtering unit before being output to a frame detection and capture unit.

7. The apparatus for synchronously transmitting and receiving a broadband spread spectrum signal according to claim 1, wherein: The transmitting end includes a global enabling unit, a PCIE interface FIFO, a data parsing unit, and a second pre-processing module; The host computer packages the response signal according to a pre-agreed packet format; the data parsing unit is used to read the response data packet through the PCIE interface FIFO when the global enable unit outputs a valid enable signal; the data parsing unit is used to parse the response data packet and compare the timed transmission timestamp obtained by parsing with the local timestamp output by the local timestamp counter. When the local timestamp used to represent the theoretical transmission time of the response data packet is equal to the timed transmission timestamp used to represent the actual transmission time of the response data packet, the data parsing unit sends the response data packet to the second preprocessing module, and the second preprocessing module converts the response data packet into a broadband spread spectrum signal and transmits it externally.

8. The apparatus for synchronously receiving and transmitting a wideband spread spectrum signal according to claim 7, wherein: The data parsing unit includes a PCIE read enable control logic subunit, a depacketizing subunit, a FIFO, and a timing sending control subunit; The depacketizing subunit is used to perform serial-to-parallel conversion on the 128-bit 4-way I, Q parallel data response data packet read from the PCIe interface FIFO, and then identify the packet header information and the data to be processed according to the packet header start feature identifier, wherein the packet header information includes the start feature word, the timed transmission timestamp, the packet sequence number, the data type, the data length, and the end feature word; the timed transmission control subunit is used to compare the parsed timed transmission timestamp with the local timestamp output by the local timestamp counter, and when the local timestamp is equal to the timed transmission timestamp, the packet is sent to the local time stamp counter. , start FIFO read enable; the FIFO is used to store the data to be processed without the header information after the read enable is started; the PCIe read enable control logic subunit determines the amount of parsed data to be processed by detecting the depth of the data already stored in the FIFO. When the depth of the data already stored in the FIFO reaches 3 / 4 of the frame length, reading data from the PCIe interface FIFO is stopped. When the depth in the FIFO is less than 1 / 4 of the frame length, reading data continues, thereby ensuring that the data to be processed in the FIFO is dynamically maintained at 1 / 4 to 3 / 4 of the frame length.

9. The apparatus for synchronously receiving and transmitting a wideband spread spectrum signal according to claim 7, wherein: The second pre-processing module includes a shaping filter unit, a third half-band filter unit I, a Farrow filter unit, a spectrum shift unit, a serial-to-parallel conversion unit, a third half-band filter unit II, and a DA conversion module; The response data packet is filtered by the shaping filter unit, the third half-band filter unit I, and the Farrow filter unit in sequence, and then moved to the specified frequency point by the spectrum shifting unit; The response data packet moved to the specified frequency point is serial-to-parallel converted by the serial-to-parallel conversion unit, filtered by the third half-band filter II, and then converted into a broadband spread spectrum signal by the DA conversion module and transmitted externally.

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