Ramp generator, analog-to-digital converter and image sensor based on double-edge triggering

Abstract

The present application discloses a ramp generator, analog-to-digital converter and image sensor based on double-edge triggering, and relates to the field of signal processing. The ramp generator includes: a current device, including multiple current sub-devices, each of which receives a clock signal and is used to output a current signal, and the output ends of multiple current sub-devices are connected in parallel for superimposing current signals; a clock generating device, connected to the input ends of multiple current devices, for providing one or more groups of clock signals, and inputting the clock signals to the current device; a load resistor device, connected to the output ends of the current devices after parallel connection, for converting the superimposed current signal into a ramp voltage signal; wherein the current device contains at least one sub-device combination. Based on the above configuration, compared with the original ramp generator with a single clock signal, the parallel current signal undergoes multiple changes within the same clock cycle, which expands the slope or resolution of the ramp voltage signal.

Description

Technical Field

[0001] The invention belongs to the field of signal processing, and in particular relates to a ramp generator, an analog-to-digital converter and an image sensor based on double-edge triggering. Background Art

[0002] In existing image sensors, a linear ramp voltage waveform signal (Vramp, hereinafter referred to as ramp voltage signal) provided by a ramp generator is often used as a global reference signal of an analog-to-digital conversion circuit to convert an analog signal of a pixel into a digital code.

[0003] In order to meet the requirements of different working scenarios, it is often necessary to adjust the slope of the ramp voltage signal. For analog-to-digital conversion type ramp generators, the prior art often adjusts the slope of the ramp voltage signal by changing the frequency of the clock signal input to the counter.

[0004] Due to the limitation of process and structure, and the parasitic influence between devices and traces, the working frequency of the counter has a high-speed bottleneck, which limits the adjustment range of the slope of the ramp voltage signal. For example, when the delay time of the highest and lowest bits of the counter output exceeds half the clock cycle of the clock signal, it is impossible to make synchronous adjustments, resulting in bit errors in the output of the counter, affecting the normal working state of the ramp generator.

[0005] Therefore, a ramp generator is urgently needed to further expand the adjustment range of the slope of the ramp voltage signal. Summary of the invention

[0006] The present application proposes a ramp generator, an analog-to-digital converter and an image sensor based on double-edge triggering, which are used to expand the slope adjustment range of a ramp voltage signal.

[0007] To achieve the above objectives, this application proposes the following technical solutions:

[0008] In a first aspect of the present application, a ramp generator based on double-edge triggering is provided, comprising:

[0009] A current device, comprising a plurality of current sub-devices, each of which receives a clock signal and is used to output a current signal, and the output ends of the plurality of current sub-devices are connected in parallel to superimpose the current signals;

[0010] A clock generating device, connected to the input terminals of the plurality of current sub-devices, for providing one or more groups of clock signals and inputting the clock signals into the current sub-devices; wherein the clock frequencies of the plurality of groups of clock signals are the same but the phases are different;

[0011] A load resistor device, connected to the output ends of the current sub-devices connected in parallel, and used for converting the superimposed current signal into a ramp voltage signal;

[0012] Among them, the current device includes at least one sub-device combination, and the sub-device combination is composed of a first current sub-device and a second current sub-device that receive the same clock signal; the current sub-device is divided into a first current sub-device and a second current sub-device, the first current sub-device is triggered based on the rising edge of the clock signal; the second current sub-device is triggered based on the falling edge of the clock signal.

[0013] Optionally, when the clock generating device only provides one set of clock signals, the current device is composed of only one sub-device combination.

[0014] Optionally, when the current device is composed of a sub-devices, the number of clock signals with different phases is a, and the phase difference between two clock signals with adjacent phases is ; where a is a positive integer.

[0015] Optionally, when the current device is composed of a sub-device combination and (b-2a) first current sub-devices or second current sub-devices, the minimum phase difference between different clock signals is ; Wherein, b is a positive integer and b>2a.

[0016] Optionally, the first current sub-device includes:

[0017] A first ramp counter, connected to the output end of the clock generating device, for receiving a clock signal and triggering sampling based on a rising edge of the clock signal to generate a first digital signal;

[0018] A first decoder is connected to the output end of the first ramp counter, and is used to receive the first digital signal and perform digital conversion on it to transform it into a second digital signal;

[0019] a first current unit connected to the output end of the first decoder, configured to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust a value of the current signal based on the switch control signal;

[0020] The second current sub-device comprises:

[0021] A second ramp counter, connected to the output end of the clock generating device, for receiving a clock signal and triggering sampling based on a falling edge of the clock signal to generate a first digital signal;

[0022] A second decoder is connected to the output end of the second ramp counter, and is used to receive the first digital signal and perform digital conversion on the first digital signal to transform it into a second digital signal;

[0023] The second current unit is connected to the output end of the second decoder, and is used to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

[0024] Optionally, if the bit width of the first ramp counter or the second ramp counter is N bits, the first digital signal is a binary code of N bits, and the first decoder or the second decoder converts the first Nm bits of the binary code of the first digital signal into a thermometer code in a bit order from high to low, and the last m bits remain the binary code and are transformed into the second digital signal, where m is a preset value; the thermometer code includes a row selection thermometer code and a column selection thermometer code.

[0025] Optionally, the first current unit and the second current unit both include a D latch, and the input end of the D latch is connected to an AND or NOR logic gate circuit; wherein the second digital signal passes through the logic gate circuit and is input to the D latch, and the second digital signal output by the D latch is used as the switch control signal.

[0026] Optionally, in the first current sub-device, the D latch inside the first ramp counter is triggered based on a low level, and the D latch inside the first current unit is triggered based on a high level; in the second current sub-device, the D latch inside the second ramp counter is triggered based on a high level, and the D latch inside the second current unit is triggered based on a low level.

[0027] In a second aspect of the present application, an analog-to-digital converter is provided, comprising: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit comprising: a comparator, a column counter and a ramp generator as described in the first aspect, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; the input terminal of the column counter is connected to the output terminal of the comparator; if the total number of current devices is c, the operating frequency of the column counter is adjusted to c times the original operating frequency.

[0028] In the third aspect of the present application, an image sensor is provided, comprising: a pixel circuit, a digital logic circuit and an analog-to-digital converter as described in the second aspect, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; and the digital logic circuit is used to configure a flip point, a ramp excitation signal and a ramp initial value signal.

[0029] The beneficial effects of this application are as follows:

[0030] The present application provides a ramp generator, comprising: a current device, including multiple current sub-devices, each of which receives a clock signal and is used to output a current signal, and the output ends of the multiple current sub-devices are connected in parallel to superimpose the current signals; a clock generating device, connected to the input ends of the multiple current sub-devices, used to provide one or more groups of clock signals, and input the clock signals to the current sub-devices; wherein the clock frequencies of the multiple groups of clock signals are the same but the phases are different; a load resistor device, connected to the output ends of the current sub-devices after being connected in parallel, used to convert the superimposed current signals into ramp voltage signals.

[0031] Among them, the current device includes at least one sub-device combination, and the sub-device combination is composed of a first current sub-device and a second current sub-device that receive the same clock signal; the current sub-device is divided into a first current sub-device and a second current sub-device, the first current sub-device is triggered based on the rising edge of the clock signal; the second current sub-device is triggered based on the falling edge of the clock signal.

[0032] Based on the above settings, the ramp generator provided in the present application processes the clock signal by adopting current sub-devices triggered by different edges, and converts the current signals generated by the current sub-devices into ramp voltage signals after parallel connection. Compared with the original ramp generator with a single clock signal, the parallel current signal undergoes multiple changes within the same clock cycle, thereby expanding the slope or resolution of the ramp voltage signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0034] Figure 1 is a schematic structural diagram of a ramp generator provided by the present application;

[0035] Figure 2 It is a structural schematic diagram of a current device provided by the present application;

[0036] Figure 3 is a structural schematic diagram of a first ramp counter provided by the present application;

[0037] Figure 4 is a structural schematic diagram of a second ramp counter provided by the present application;

[0038] Figure 5 is a waveform diagram of a portion of a first digital signal provided by the present application;

[0039] Figure 6is a structural schematic diagram of another ramp generator provided by the present application;

[0040] Figure 7 is a structural schematic diagram of another ramp generator provided by the present application;

[0041] Figure 8 It is a structural schematic diagram of a clock generating device provided by the present application;

[0042] Fig. 9 is a structural schematic diagram of another ramp generator provided by the present application;

[0043] Fig.10 is a structural schematic diagram of another ramp generator provided by the present application;

[0044] Fig.11 is a schematic structural diagram of another current device provided by the present application;

[0045] Fig.12 It is a schematic diagram of a decoding and synchronous latching circuit provided by the present application;

[0046] Fig.13 is a structural schematic diagram of a current mirror switch provided by the present application;

[0047] Fig.14 is a schematic diagram of an original ramp voltage signal provided by the present application;

[0048] Fig.15 is a schematic diagram of an adjusted ramp voltage signal provided by the present application;

[0049] Fig.16 is a schematic diagram of another adjusted ramp voltage signal provided by the present application;

[0050] Fig.17 It is a structural schematic diagram of an analog-to-digital converter provided by the present application;

[0051] Fig.18 It is a structural schematic diagram of an image sensor circuit provided by the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0053] In CMOS image sensors, the linear ramp voltage signal is used as a global reference signal for the analog-to-digital conversion circuit to convert the analog signal from the photodiode pixel into a digital code.

[0054] The prior art often adjusts the slope of the ramp voltage signal by changing the frequency of the clock signal input to the counter. However, due to the limitations of the process and structure, and the parasitic effects between the devices and the wiring, the operating frequency of the counter has a high-speed bottleneck, which limits the maximum value of the slope of the ramp voltage signal. The slope of the ramp voltage signal represents the absolute value of the voltage change of the ramp voltage signal per unit time.

[0055] In order to solve the above problems, the present application provides a ramp generator based on double-edge triggering to further expand the adjustment range of the slope of the ramp voltage signal. The ramp generator provided by the present application includes:

[0056] A current device, comprising a plurality of current sub-devices, each of which receives a clock signal and is used to output a current signal, and the output ends of the plurality of current sub-devices are connected in parallel to superimpose the current signals;

[0057] A clock generating device, connected to the input terminals of the plurality of current sub-devices, for providing one or more groups of clock signals and inputting the clock signals into the current sub-devices; wherein the clock frequencies of the plurality of groups of clock signals are the same but the phases are different;

[0058] A load resistor device, connected to the output ends of the current sub-devices connected in parallel, and used for converting the superimposed current signal into a ramp voltage signal;

[0059] Among them, the current device includes at least one sub-device combination, and the sub-device combination is composed of a first current sub-device and a second current sub-device that receive the same clock signal; the current sub-device is divided into a first current sub-device and a second current sub-device, the first current sub-device is triggered based on the rising edge of the clock signal; the second current sub-device is triggered based on the falling edge of the clock signal.

[0060] Based on the above settings, the ramp generator provided in the present application processes the clock signal by adopting current sub-devices triggered by different edges, and converts the current signals generated by the current sub-devices into ramp voltage signals after parallel connection. Compared with the original ramp generator with a single clock signal, the parallel current signal undergoes multiple changes within the same clock cycle, thereby expanding the slope or resolution of the ramp voltage signal.

[0061] In some embodiments, when the clock generating device provides only one set of clock signals, the current device is composed of only one sub-device combination.

[0062] Specifically, Figure 1As shown, the ramp generator includes a clock generating device, a current device (consisting of a sub-device combination consisting of a first current sub-device and a second current sub-device) and a load resistance device. At this time, the clock generating device only needs to provide a clock signal CLK.

[0063] Since the edge triggering modes of the ramp generators in the first current sub-device and the second current sub-device are different (rising edge triggering and falling edge triggering respectively), within the same clock signal cycle, the ramp generators in the first current sub-device and the second current sub-device are triggered once respectively, and the phase difference is 180°, just like receiving two clock signals with a phase difference of 180° under the same triggering mode.

[0064] After the current signals generated by different current sub-devices are connected in parallel, they are converted into ramp voltage signals through the load resistance device. Therefore, compared with the original ramp generator with a single clock signal, the ramp generator provided in this embodiment has a current signal after parallel connection that changes twice in the same clock cycle, which can effectively increase the slope or resolution of the ramp voltage signal.

[0065] The resolution is the smallest change in the analog signal that the ADC can identify, usually expressed in bits. For example, an 8-bit ADC can identify 256 different signal levels, while a 12-bit ADC can identify 4096 signal levels.

[0066] Compared with the technical solution of using multiple clock signals to expand the slope range of the ramp voltage signal, the ramp generator provided in this embodiment only requires a single clock signal, which can effectively reduce the structural complexity of the clock generating device, and does not require multi-phase clock generating devices such as ring oscillators or phase interpolators, thereby improving the portability of the ramp generator.

[0067] At the same time, compared with the two clock signals with a phase difference of 180° provided by the multi-phase clock generating device, the phase difference of the ramp counter in this embodiment is consistent and more closely fits 180°, so that the holding time of the current signal generated based on the clock signal is the same, and the linearity of the final ramp voltage signal is more effectively reduced to eliminate the burrs of the ramp voltage signal to the greatest extent. Among them, linearity represents the deviation between the actual output ramp voltage signal and the ideal ramp voltage signal, also known as nonlinear error. The smaller the linearity, the lower the deviation, and the higher the degree of fitting straight line of the ramp voltage signal.

[0068] like Figure 2 As shown, each current sub-device includes:

[0069] The ramp counter is connected to the output end of the clock generating device, and is used to receive the clock signal and generate the first digital signal based on the triggering of the clock signal. The ramp counter is divided into two types: a first ramp counter and a second ramp counter.

[0070] The decoder is connected to the output end of the ramp counter and is used to receive the first digital signal and perform digital conversion on it to transform it into a second digital signal. The decoder is divided into two types: a first decoder and a second decoder.

[0071] A current unit is connected to the output end of the decoder, and is used to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust the value of the current signal based on the switch control signal. The current signal is generated and output by the current unit. The current unit is divided into two types: a first current unit and a second current unit.

[0072] The ramp counter includes a first ramp counter and a second ramp counter. The first ramp counter is arranged in the first current sub-device and triggers sampling based on the rising edge of the clock signal. The second ramp counter is arranged in the second current sub-device and triggers sampling based on the falling edge of the clock signal.

[0073] In one implementation, the internal structure of the first ramp counter is as follows: Figure 3 As shown, it includes N D flip-flops 1, and each D flip-flop 1 outputs Q inverted , as the input trigger signal of the next D flip-flop 1. Wherein, N represents the bit width of the counter, and D flip-flop 1 represents a D flip-flop based on rising edge triggering.

[0074] During the operation of the first counter and the first slope counter, if Figure 3 As shown, from left to right, the first D flip-flop 1 uses the clock signal CLK provided by the clock device as a trigger signal, and is triggered based on the rising edge of the clock signal, and outputs Q as the lowest bit q of the first digital signal <0> , and the output Q is inverted As the input trigger signal of the second D flip-flop 1. After that, the output Q of the second D flip-flop is used as the first digital signal (from low to high) and the second bit q <1> , As the input trigger signal of the third D flip-flop 1. Similarly, the output Q of each D flip-flop 1 is the value of the corresponding bit of the first digital signal. As the input trigger signal of the next D flip-flop 1.

[0075] The internal structure of the second ramp counter is as follows: Figure 4As shown, N D flip-flops 2 are included, and each D flip-flop 2 outputs Q as an input trigger signal of the next D flip-flop 2. The D flip-flop 2 represents a D flip-flop based on falling edge triggering.

[0076] During the operation of the second ramp counter, if Figure 4 As shown, from left to right, the first D flip-flop 2 uses the clock signal CLK provided by the clock device as a trigger signal, and is triggered based on the falling edge of the clock signal, and outputs Q as the lowest bit q of the first digital signal <0> , and the output Q is used as the input trigger signal of the second D flip-flop 2. Afterwards, the output Q of the second D flip-flop is used as the first digital signal (from low to high) and the second q <1> , and serves as the input trigger signal of the third D flip-flop 2. Similarly, the output Q of each D flip-flop 2 serves as the value of the corresponding bit of the first digital signal, and serves as the input trigger signal of the next D flip-flop 1.

[0077] Taking the ramp generator corresponding to Figure 1 as an example, the lowest bit q in the first digital signal <0> and (from low to high) the second q <1> As Figure 5 Specifically, Figure 5 CLK in the figure represents the clock signal provided by the clock sending device, and the rising edge triggers q <0> ,q <1> They represent the q output by the first counter and the first ramp counter respectively. <0> ,q <1> , while the falling edge triggers q <0> ,q <1> They represent the q output by the second counter and the second ramp counter respectively. <0> ,q <1> .

[0078] Reference Figure 3 , 4 The counter structure shown, combined with Figure 5 From the waveform shown, it can be seen that in the first digital signal, the phase difference between the first counter, the first ramp counter and the second ramp counter triggered at different bit numbers is the same, thereby avoiding errors in the ramp voltage signal provided by the ramp generator under different edge triggering modes.

[0079] In summary, the first current sub-device indicates that the ramp counter inside it belongs to the current device for rising edge triggered sampling, and the second current sub-device indicates that the ramp counter inside it belongs to the current device for falling edge triggered sampling. The combination of the first current sub-device and the second current sub-device receiving the same clock signal is referred to as a sub-device combination. It can be understood that the phase difference between the first current sub-device and the second current sub-device in any sub-device combination is 180°, that is, the clock phase difference corresponding to the internal ramp generator triggering sampling is 180°.

[0080] In addition, if the DDR counter is applied to the ramp generator, since the DDR counter itself is triggered twice based on the upper and lower edges of the first bit, the DFF (D flip-flop) can be used to trigger it later. Although the DDR counter can reach a double counting frequency, since the low bit cannot be turned off, only the high bit can be turned off, which will cause the range of the final generated ramp voltage signal to change, and cannot meet the functional requirements of the adjustable bit width of the counter in the ramp generator. The ramp generator provided in the present application uses two different groups of counters, which are triggered on the rising edge and the falling edge respectively, which can not only ensure a double counting rate, but also adjust the internal bit width of the counter, so that the slope and resolution of the ramp voltage signal can be adjusted more flexibly.

[0081] In some embodiments, when the current device is composed of a sub-devices, the number of clock signals with different phases is a, and the phase difference between two clock signals with adjacent phases is . Where a is a positive integer.

[0082] Combining the above single clock signal embodiment, it can be seen that the first current sub-device and the second current sub-device receiving the same clock signal have a phase difference of 180° at the triggering time. Therefore, when the clock generating device provides a (a>1) groups of clock signals with different phases (where a=1 corresponds to the embodiment shown in FIG. 1), and the minimum phase difference between different clock signals is When the phase difference between the first current sub-device and the second current sub-device adjacent to each other at the triggering moment is also .

[0083] Therefore, in the same clock cycle, the current signal in the ramp generator after parallel connection changes multiple times, which can effectively increase the slope or resolution of the ramp voltage signal, and the phase difference between the two current devices at adjacent triggering moments is the same, that is, both are , which can ensure that the delay time of the triggering moment between adjacent clock signals is the same, so that the holding time of the current signal generated based on the clock signal is the same, reducing the linearity of the final ramp voltage signal.

[0084] like Figure 6 As shown, the ramp generator includes 4 current sub-devices, and the 4 current sub-devices are respectively composed of 2 sub-device combinations, wherein one sub-device combination receives a clock signal CLK<0°> with a phase difference of 0° (compared to the standard clock signal), and the other sub-device combination receives a clock signal CLK<90°> with a phase difference of 90° (compared to the standard clock signal).

[0085] Since the first current sub-device and the second current sub-device receiving the same clock signal are respectively triggered by the rising edge and the falling edge, taking the first current sub-device receiving the clock signal CLK<0°> as a reference, the triggering phase difference of the first current sub-device receiving the clock signal CLK<90°> is 90°, the triggering phase difference of the second current sub-device receiving the clock signal CLK<0°> is 180° (i.e., equivalent to the first current sub-device receiving the clock signal CLK<180°>), and the triggering phase difference of the second current sub-device receiving the clock signal CLK<90°> is 270° (i.e., equivalent to the first current sub-device receiving the clock signal CLK<270°>). Therefore, in the same clock cycle, the current signal after the ramp generator is connected in parallel changes 4 times, based on which the slope or resolution of the ramp voltage signal can be effectively increased.

[0086] In some embodiments, when the current device is composed of a sub-device combination and b-2a first current sub-devices or second current sub-devices, the minimum phase difference between different clock signals is ; Wherein, b is a positive integer and b>2a.

[0087] As shown in FIG7, when the ramp generator includes a sub-device combination and two first current sub-devices, since the first current sub-device and the second current sub-device receiving the same clock signal are triggered by the rising edge and the falling edge respectively, taking the first current sub-device receiving the clock signal CLK<0°> as a reference, the triggering phase difference of the first current sub-device receiving the clock signal CLK<90°> is 90°, the triggering phase difference of the second current sub-device receiving the clock signal CLK<0°> is 180°, and the triggering phase difference of the first current sub-device receiving the clock signal CLK<270°> is 270°. Therefore, in the same clock cycle, the current signal of the ramp generator after parallel connection changes 4 times, based on which the slope or resolution of the ramp voltage signal can be effectively increased.

[0088] It can be seen that in the ramp generator provided by the present application, the current device can be composed of a sub-device combination and a first current device or a second current device, and the number of the device combination and the first current device or the second current device, the number of clock signals, and the phase difference of the connected clock signals can be adaptively adjusted to obtain a ramp generator with the same technical effect but different structure. For example, the current device shown in FIG7 can also be adjusted to a sub-device combination and two second current devices, or adjusted to a sub-device combination receiving a clock signal CLK<90°> and a first current device or a second current device receiving clock signals CLK<0°> and CLK<180°> respectively.

[0089] In addition, it can be understood that the phase difference of the clock signals received by different first current devices or second current devices is 180°.

[0090] In some embodiments, when the current device includes only the first current device or the second current device, and the number of the current devices is b, the number of different phase clock signals is the same as the number of the current devices, and the phase difference between adjacent phase clock signals is .

[0091] For example, when the clock generating device provides four groups of clock signals with different phases, compared with the reference clock signal, the phases of the four groups of clock signals are 0°, 90°, 180°, and 270°, respectively, and are transmitted to different first current devices or second current devices respectively. Similarly, compared with the original ramp generator with a single clock signal, the parallel current signal can also change multiple times in the same clock cycle, thereby effectively increasing the slope or resolution of the ramp voltage signal.

[0092] In one implementation, the clock generation device can generate clock signals with different phases through a ring oscillator. Specifically, the reference clock signal is inserted into the ring oscillator to form clock signals with different phases. A PLL is used in the ring oscillator. Then, the clock signals with different phases are sent to different current devices.

[0093] In one implementation, the clock generation device can also provide clock signals of different phases based on a combination of a delay circuit and a plurality of phase interpolators. When the clock generation device is a four-phase clock generation circuit that provides four sets of clock signals of different phases, as shown in FIG8 , it includes a delay circuit and four phase interpolators (PI01, PI02, PI03, and PI04). Among them, the delay circuit delays the input reference clock signal by a predetermined delay time tPD and outputs a delayed clock signal. The delay time tPD is 1 / 4 cycle of the reference clock signal, and then the delay circuit sends the delayed reference clock signal to the phase interpolators PI01, PI02, PI03, and PI04, respectively.

[0094] The phase interpolators PI01, PI02, PI03 and PI04 all have the same circuit. Each phase interpolator is a circuit with two inputs and one output, and outputs a signal at a time delayed by a predetermined delay time from the middle time of the phase difference between the two input signals.

[0095] As shown in FIG8 , the reference clock signal is delayed by about 1 / 4 cycle and input to the phase interpolator PI01. The phase interpolator PI01 generates the clock signal q0 as one of the four-phase clock signals with these signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The inversion signal of the reference clock signal and the signal obtained by delaying the reference clock signal by about 1 / 4 cycle are input to the phase interpolator PI02. The phase interpolator PI02 generates the clock signal q1 as one of the four-phase clock signals with these signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The inversion signal of the reference clock signal and the signal obtained by delaying the reference clock signal by about 1 / 4 cycle are input to the phase interpolator PI03. The phase interpolator PI03 generates the clock signal q2 as one of the four-phase clock signals with these signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit. The reference clock signal and the inversion signal of the signal obtained by delaying the reference clock signal by about 1 / 4 cycle are input to the phase interpolator PI04. The phase interpolator PI04 generates a clock signal q3 which is one of four-phase clock signals using these signals and outputs the generated clock signal to the outside of the four-phase clock generation circuit.

[0096] The phase interpolator generates four-phase clock signals whose phases are all shifted by 1 / 4 cycle using a reference clock signal and a signal obtained by delaying the reference clock signal by about 1 / 4 cycle, and outputs the four-phase clock signals.

[0097] In addition, by changing the number or combination of phase interpolators in the phase difference clock generating circuit in the example in Figure 8 (four-phase clock generating circuit), an 8-phase clock signal with each phase shifted by 1 / 8 cycle or a 16-phase clock signal with each phase shifted by 1 / 16 cycle can be generated.

[0098] Similarly, by changing the number, combination and weighting coefficient W of the phase interpolators of the phase difference clock generating circuit in the example (four-phase clock generating circuit) in Figure 8, a three-phase clock signal with each phase shifted by 1 / 3 of a cycle or a five-phase clock signal with each phase shifted by 1 / 5 of a cycle can be generated.

[0099] In some embodiments, if the bit width of the ramp counter is N bits, the first digital signal is a binary code of N bits, and the decoder converts the first Nm bits of the binary code of the first digital signal into a thermometer code along the bit sequence from high to low, and the last m bits remain in binary code and are transformed into the second digital signal, where m is a preset value; the thermometer code includes a row selection thermometer code and a column selection thermometer code.

[0100] Taking the ramp counter with a bit width of 10 bits and m equal to 6 as an example, the first digital signal is a 10-bit binary value, and the decoder converts the upper 6 bits of binary code into 3-bit row selection (selrow) thermometer code and 3-bit column selection (selcol) thermometer code, respectively, while the lower 4 bits remain in binary code (sellow), thereby forming a second digital signal and outputting it from the output end of the decoder. Based on the above processing, compared with the first digital signal, the second digital signal can effectively reduce the data volume of the digital signal and improve the efficiency of signal transmission.

[0101] In some embodiments, the current unit includes a D latch, and the input end of the D latch is connected to an AND or NAND logic gate circuit; wherein the second digital signal passes through the logic gate circuit and is input to the D latch, and the second digital signal output by the D latch is used as a switch control signal.

[0102] In some embodiments, the ramp counter also includes a D latch. In the first current sub-device, the D latch inside the first counter and the first ramp counter is set to be triggered based on a low level, and the D latch inside the current unit is set to be triggered based on a high level. In the second current sub-device, the D latch inside the second counter and the second ramp counter is set to be triggered based on a high level, and the D latch inside the current unit is set to be triggered based on a low level.

[0103] Through the above-mentioned adjustment of the triggering mode in different D latches, it can be made that in the same current device, different digital signals are output at the same time after passing through the D latch, thereby ensuring the accuracy of the time when the current signal is generated and avoiding different time intervals for outputting current signals in different current devices, thereby effectively improving the quality of the ramp voltage signal and reducing the linearity.

[0104] In some embodiments, the ramp generator further includes a reference current generating circuit and a PSRR (Power Supply Rejection Ratio) compensation device, wherein the reference current generating circuit provides a bias current for the current source of the ramp generator, and the PSRR compensation device is used to reduce the power supply ripple rejection ratio of the current source.

[0105] As shown in Figure 9, the ramp generator corresponding to a single clock signal provided in the present application includes a clock generating device that provides a single clock signal, a first current sub-device composed of a first counter, a first ramp counter, a decoding circuit (i.e., a decoder) and a current source array, a second current sub-device composed of a second counter, a second ramp counter, a decoding circuit and a current source array, a load resistor array (i.e., a load resistor device), a reference current generating circuit and a PSRR compensation device.

[0106] like Fig.10As shown, the present application provides a circuit schematic diagram based on a single clock signal ramp generator, including a clock generating device (providing a single clock signal CLK), a first counter first ramp counter triggered by a rising edge, a second counter second ramp counter triggered by a falling edge, two decoders, two current units and a load resistor device. Among them, the bit width of each ramp counter is N bits, and the switch control signal of the current unit adopts a low m bit binary code and a high Nm bit thermometer code.

[0107] To convert binary code to thermometer code, you only need to convert the high-bit binary code into row selection (selrow) and column selection (selcol) thermometer codes, and keep the low-bit binary code (sellow) for output. After decoding, different counters control two current mirror units of the same number, and (N+1) bit data can be obtained.

[0108] The existing ramp generator controls all current mirror arrays to switch in each clock cycle, thereby obtaining a change in output voltage. However, in the ramp generator with a single clock signal of the present application, the first counter only controls the switch of 1 / 2 group of current mirror arrays (i.e., current unit 1) after counting and decoding, but keeps the unit current mirror (i.e., the adjustment amount of the current signal under each trigger) unchanged.

[0109] In each clock cycle, the current mirror array controlled by each ramp counter is converted into the original 1 times RAMP voltage change value through the load resistor. Similarly, after 1 / 2 clock cycle, the current mirror array controlled by the second ramp counter of the second counter is also converted into the 1 times RAMP voltage change value through the load resistor. The above process completes the voltage conversion at different phase moments within one clock cycle.

[0110] Compared with the traditional ramp generator, the voltage change value during the two phases changes by 1 times of the original value, and after a clock cycle, they contribute to a voltage change value of 2 times, so that the slope of the ramp voltage signal increases by 2 times. This ensures that the voltage range of RAMP remains unchanged, but the amount of data of voltage change increases, that is, the resolution increases by 1 bit. Similarly, in one cycle, the corresponding counter triggers a ramp generator with 4 phase changes to obtain an additional 2 bits of resolution, and an 8-phase ramp generator can obtain an additional 3 bits of resolution, and so on.

[0111] like Fig.10As shown, the same group of clock signals are respectively input to two groups of ramp counters (i.e., the first counter, the first ramp counter and the second counter, the second ramp counter), wherein the D flip-flop constituting the first counter, the first ramp counter, is of the rising edge trigger type, and the D flip-flop constituting the second counter, the second ramp counter, is of the falling edge trigger type. Then, the ramp generators respectively control their respective current source modules (i.e., current units) through their respective decoding circuits (i.e., decoders), and finally the current source modules are connected in parallel to the load resistor device, thereby generating a ramp voltage signal.

[0112] Among them, when the two sets of decoding circuits beat the binary codes output by the two sets of counters, due to the different edge triggering modes of the two sets of counters, it is necessary to make adaptive adjustments to the level triggering mode. Specifically, when the N-bit output binary code (i.e., the first digital signal) of the first counter and the first slope counter triggered by the rising edge is synchronously beat through the D latch (D latch) in the decoder module (i.e., the decoder), the D latch adopts a low-level triggering mode. The binary code and the thermometer code also need to be translated into a current control signal in the current unit through the AND or NOR logic and then synchronized through the high-level triggered Dlatch.

[0113] The second counter and the second ramp counter triggered by the falling edge have N bit output binary codes. When the decoder module uses the D latch to synchronize the beat, the D latch uses the high level triggering method. The binary code and the thermometer code also need to be translated into the current control signal in the current cell module through the AND or NOR logic and then synchronized through the low level triggered D latch again. In this way, the current signal output by the current unit controlled by the switch control signal also has a phase difference of 180°.

[0114] In addition, currentcell <1> and currentcell <2> (That is, current unit 1 and current unit 2) are two groups of current source arrays controlled by different counters, and the magnitude of the current signal and the number of current mirror tubes need to be kept consistent.

[0115] like Fig.11As shown, a ramp generator composed of 4 current devices is taken as an example, that is, a DAC ramp (ramp generator) with a mixed structure of 4-bit binary and 4-bit thermometer code. The decoder converts the high 4-bit binary code output by the ramp counter into a 3-bit row selection thermometer control code and a 3-bit column selection thermometer control code. The 8-bit ramp generator provided in this application is equivalent to the original 10-bit ramp generator. Among them, x1...x16 respectively represent the number of current mirror tubes in the current unit, that is, current unit x1 (that is, indicating that there is 1 current mirror tube in the current unit), current unit x2 (that is, indicating that there are 2 current mirror tubes in the current unit), current unit x4, current unit x8, current unit x16 (that is, indicating that there are 16 current mirror tubes in the current unit), and the number of current unit x16 is reduced to 1 / 4.

[0116] Each counter corresponds to a current mirror array (i.e., current unit), the ramp counter <1> Generated clkarray, sell <1> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current units x1 respectively; clkarray, sell <2> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x2 modules respectively; clkarray, sell <3> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x4 modules respectively; clkarray, sell <4> , tiehi, tielo are connected to the clk, A, B, C ports in the first group of current unit x8 modules respectively; the first group of current unit x16 modules has 16 current mirror units, which connect clkarray, < 4>(sel_col<1:3>, tielo),< 4>tiehi,sel_row<(1 4,2 4,3 4)> and sel_row<(1 4,2 4,3 4)>,< 3> tielo, tiehi are connected to the clk, A, B, and C ports of Icell<16:1>. Similarly, the second, third, and fourth groups of counters are connected to the corresponding current mirror arrays according to the above method.

[0117] like Fig.12As shown, the row and column control codes are AND-OR-N logic inside the current unit module, and recompiled into the switch control signal of the current unit. However, since the delay path of these control signals cannot be kept completely consistent during the encoding and decoding process, the control signal needs to be passed through Dlatch (D latch) to synchronize the signals of different bits at the same clock rising edge. Finally, the time when the control signals sel and selb of different current units arrive at the current mirror switch can be kept consistent.

[0118] The structure of the current mirror switch is as follows: Fig.13 As shown in the figure, pbias represents the current tube bias voltage, pcas represents the common source and common gate tube bias voltage, sel represents the current turn-on signal, and selb represents the current turn-off signal.

[0119] If the clock signal frequency in the original ramp generator has been adjusted to the maximum value f (in Hz), the present application also provides an adjustment method for the ramp generator provided in the present application, which is used to increase the slope or resolution of the ramp voltage signal. The adjustment method includes the following steps:

[0120] Step 1: Obtain the total number c of current devices.

[0121] Step 2: Adjust the current signal to the original value at each trigger. , and keep the bit width of the ramp counter unchanged.

[0122] Based on the above processing, the adjustment amount of the current signal in the ramp generator at each trigger is adjusted to the original , so that the range of the original ramp voltage signal does not change, ensuring the applicability of the ramp generator in the present application, and can be directly applied to the usage scenario of the original ramp generator.

[0123] At the same time, although the bit width of the ramp counter remains unchanged, the total bit width of multiple ramp counters increases due to the adaptability of the number of ramp counters and the number of clock signals, thereby improving its resolution while ensuring that the range of the ramp voltage signal remains unchanged.

[0124] like Fig.14 As shown, the original ramp represents the ramp voltage signal generated by the original ramp generator, x1 represents the slope of the ramp voltage signal is 1, v represents the voltage value, and t represents the time length. Fig.15 As shown, Fig.15 Schematic diagram of a ramp voltage signal including the original ramp and this ramp, where this ramp represents the ramp voltage signal obtained based on the ramp generator provided by the present application and the above adjustment method, wherein the slope and voltage range of this ramp are the same as those of the original ramp, but its resolution is increased by 4 times.

[0125] In some embodiments, the adjustment method further comprises the following steps:

[0126] Step 3: Determine whether the total number of current devices c is 2 d ; Wherein, d is an integer greater than or equal to 1.

[0127] Step 4: If yes, reduce the bit width of the ramp counter by d bits, and keep the adjustment amount of the current signal unchanged in each trigger.

[0128] Based on the above processing, by reducing the bit width of the ramp counter by d bits, the resolution of the ramp generator provided in the present application can be effectively guaranteed not to change. At the same time, the adjustment amount of the current signal under each triggering remains unchanged, which can ensure that the voltage range of the ramp voltage signal does not change, thereby ensuring the applicability of the ramp generator in the present application.

[0129] In addition, in the process of generating a ramp voltage signal, the number of triggers that cause its current signal to change within the same clock cycle is c times that of the original ramp generator. Therefore, on the basis of the unchanged resolution and voltage range of the ramp voltage signal, its slope is further increased to c times the original.

[0130] like Fig.16 As shown, this ramp is a ramp voltage signal generated based on a four-phase clock signal. Compared with the original ramp, its voltage range and resolution have not changed, but its slope has increased four times.

[0131] Based on the same inventive concept, the present application also provides an analog-to-digital converter, the analog-to-digital converter includes: at least one column analog-to-digital conversion unit, the column analog-to-digital conversion unit includes: a comparator, a column counter and a ramp generator of the present application. The in-phase input of the comparator is connected to the output of the ramp generator; the input of the column counter is connected to the output of the comparator; if the total number of current devices is c, the operating frequency of the column counter is adjusted to c times the original operating frequency. In addition, due to the increase in the slope of the ramp voltage signal, the quantization time of the ramp generator is shortened, thereby reducing the power consumption of the analog-to-digital converter.

[0132] like Fig.17As shown, the present application provides an analog-to-digital converter for a readout circuit. Among them, the ramp generator generates a ramp voltage signal, and the ramp voltage signal is sampled to the in-phase input terminal of each column comparator through a capacitor, and the inverting input terminal of the comparator samples the pixel signal of each column (including signal Vin1, signal Vin2, etc.), wherein the ramp voltage signal will traverse the entire quantization voltage range and be compared with the pixel signal, and the column counter starts counting at the same time. When the ramp voltage signal>pixel signal, the comparator flips, and the column counter stops working. The counting result at this time is the digital code value after the pixel signal is quantized. It is worth noting that if the slope of the ramp voltage signal generated by the ramp generator provided in the present application increases by c times, the operating frequency of the column counter needs to be increased to c times the original operating frequency.

[0133] In actual work, the operating frequency of the column counter can be adjusted by increasing the frequency of the clock signal input to the column counter. Alternatively, the operating frequency of the column counter can also be increased based on a combination of multiple groups of counters with different triggering modes. Under a single clock signal, taking a column counter composed of two groups of counters triggered by the rising edge and the falling edge as an example, it can not only achieve a resolution higher than 1 bit at the same clock frequency, but also achieve a counting frequency twice at the same resolution. For example, the bit width of the column counter is 10 bits and the operating frequency is 1 GHz. At this time, the time from 1 to 1024 is 1024ns. For a bit width of 9 bits and an operating frequency of 1 GHz, the time to complete the counting is only 512ns, which is 1 / 2 of 10 bits. Through the two groups of counters triggered by the rising edge and the falling edge, 10 bits of data can be combined. That is, the present invention only needs to achieve 10-bit counting in 1 / 2 of the time, which improves the operating frequency and upper limit of the column counter.

[0134] like Fig.18 As shown, the existing CMOS image sensor circuit includes: a pixel array, a readout circuit, a functional logic unit, a control circuit and a status register. Among them, the pixel array is used to complete the photoelectric conversion and convert photons into electrons; the readout circuit is used to read the electrical signal converted by the pixel array; the functional logic unit is used to adjust the signal readout and transmission mode of the readout circuit; the status register is used to temporarily store the status of the readout circuit; the control circuit performs feedback adjustment on the pixel array by collecting the status of the readout circuit.

[0135] Based on the same inventive concept, the present application also provides an image sensor, which includes: a pixel circuit, a digital logic circuit and an analog-to-digital converter of the present application. The pixel circuit is connected to the inverting input terminal of the comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.

[0136] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A ramp generator based on double-edge triggering, characterized in that: include: A current device, comprising a plurality of current sub-devices, each of which receives a clock signal and is used to output a current signal, and the output ends of the plurality of current sub-devices are connected in parallel to superimpose the current signals; A clock generating device, connected to the input terminals of the plurality of current sub-devices, for providing one or more groups of clock signals and inputting the clock signals into the current sub-devices; wherein the clock frequencies of the plurality of groups of clock signals are the same but the phases are different; A load resistor device, connected to the output ends of the current sub-devices connected in parallel, and used for converting the superimposed current signal into a ramp voltage signal; Among them, the current device includes at least one sub-device combination, and the sub-device combination is composed of a first current sub-device and a second current sub-device that receive the same clock signal; the current sub-device is divided into a first current sub-device and a second current sub-device, the first current sub-device is triggered based on the rising edge of the clock signal; the second current sub-device is triggered based on the falling edge of the clock signal.

2. The ramp generator according to claim 1, characterized in that When the clock generating device only provides one set of clock signals, the current device is composed of only one sub-device combination.

3. The ramp generator according to claim 1, characterized in that: When the current device is composed of a sub-devices, the number of clock signals with different phases is a, and the phase difference between two clock signals with adjacent phases is ; where a is a positive integer.

4. The ramp generator according to claim 1, characterized in that: When the current device is composed of a sub-device combination and (b-2a) first current sub-devices or second current sub-devices, the minimum phase difference between different clock signals is ; Wherein, b is a positive integer and b>2a.

5. The ramp generator according to claim 1, characterized in that: The first current sub-device comprises: A first ramp counter, connected to the output end of the clock generating device, for receiving a clock signal and triggering sampling based on a rising edge of the clock signal to generate a first digital signal; A first decoder is connected to the output end of the first ramp counter, and is used to receive the first digital signal and perform digital conversion on it to transform it into a second digital signal; a first current unit connected to the output end of the first decoder, configured to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust a value of the current signal based on the switch control signal; The second current sub-device comprises: A second ramp counter, connected to the output end of the clock generating device, for receiving a clock signal and triggering sampling based on a falling edge of the clock signal to generate a first digital signal; A second decoder is connected to the output end of the second ramp counter, and is used to receive the first digital signal and perform digital conversion on the first digital signal to transform it into a second digital signal; The second current unit is connected to the output end of the second decoder, and is used to receive the second digital signal, convert the second digital signal into a switch control signal, and adjust the value of the current signal based on the switch control signal.

6. The ramp generator according to claim 5, characterized in that If the bit width of the first ramp counter or the second ramp counter is N bits, the first digital signal is a binary code of N bits, and the first decoder or the second decoder converts the first Nm bits of the binary code of the first digital signal into a thermometer code along the bit sequence from high to low, and the last m bits remain in the binary code and are transformed into the second digital signal, wherein m is a preset value; the thermometer code includes a row selection thermometer code and a column selection thermometer code.

7. The ramp generator according to claim 5, characterized in that The first current unit and the second current unit both include a D latch, and the input end of the D latch is connected to an AND or NOR logic gate circuit; wherein the second digital signal passes through the logic gate circuit and is input to the D latch, and the second digital signal output by the D latch is used as the switch control signal.

8. The ramp generator according to claim 7, characterized in that In the first current sub-device, the D latch inside the first ramp counter is triggered based on a low level, and the D latch inside the first current unit is triggered based on a high level; in the second current sub-device, the D latch inside the second ramp counter is triggered based on a high level, and the D latch inside the second current unit is triggered based on a low level.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter includes: at least one column analog-to-digital conversion unit, and the column analog-to-digital conversion unit includes: a comparator, a column counter and a ramp generator as described in any one of claims 1 to 8, wherein the non-inverting input terminal of the comparator is connected to the output terminal of the ramp generator; the input terminal of the column counter is connected to the output terminal of the comparator; if the total number of current devices is c, the operating frequency of the column counter is adjusted to c times the original operating frequency.

10. An image sensor, characterized in that: The image sensor comprises: a pixel circuit, a digital logic circuit and an analog-to-digital converter as claimed in claim 9, wherein: the pixel circuit is connected to the inverting input terminal of the comparator; the digital logic circuit is used to configure the flip point, the ramp excitation signal and the ramp initial value signal.

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