Low-dropout voltage regulator, trimming method thereof, electronic device and readable storage medium

Abstract

This invention discloses a low-dropout regulator and its tuning method, electronic device, and readable storage medium. The method includes: testing the low-dropout regulator and obtaining a first bandgap reference voltage and a first LDO output voltage; obtaining a tuning value and a reference tuning code based on the first bandgap reference voltage and a target bandgap reference voltage; obtaining an offset voltage and obtaining a second LDO output voltage based on the offset voltage, the first bandgap reference voltage, and the tuning value; obtaining a voltage divider tuning code based on the offset voltage, the target LDO output voltage, and the second LDO output voltage; and tuning the low-dropout regulator based on the reference tuning code and the voltage divider tuning code. This invention can obtain all tuning codes in one wafer test, and the second wafer test can be used for wafer screening, saving chip development time. The tuning method proposed in this invention considers the offset voltage of the chip in actual manufacturing and the influence of the bandgap reference circuit after tuning, improving the accuracy of the tuning algorithm and thus improving the output accuracy.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a low dropout voltage regulator and its adjustment method, electronic equipment, and readable storage medium. Background Technology

[0002] The chip development process includes circuit design, manufacturing, packaging, and testing. After chip manufacturing is completed, mass-produced chips need to be tested to verify their functionality, ensuring high quality and reliability. During the manufacturing process, due to process variations, chips of the same design may still exhibit significant performance differences. This necessitates testing and correction, which greatly helps improve product reliability and yield.

[0003] Traditional low-dropout regulator (LDO) metal fuse trimming uses a "CP1 read - trim1 - CP2 read - trim2 - CP3 read" method. CP1 (chip probing) reads the bandgap reference voltage VBG, and then uses a single-point calibration method to obtain the trim code (trim1) to adjust the temperature drift of the bandgap output voltage VBG_OUT. CP2 reads the LDO output voltage after trim1, and uses a trimming table to obtain the trim code (trim2) to adjust the absolute value of the LDO output voltage. CP3 reads the LDO output voltage after two trims to determine if the trimming was successful.

[0004] The disadvantages of using metal fuses for tuning in traditional low-dropout regulators are: 1. Complex circuit design, requiring a large wiring area; 2. Complex logic, requiring tuning under specific timing conditions; 3. Requires many CP pads (wafer test pads), and stress may affect chip performance.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a low-dropout regulator and its adjustment method, electronic device and readable storage medium, which can solve the problem of excessive adjustment times in traditional adjustment methods.

[0007] To achieve the above objectives, a specific embodiment of the present invention provides a low-dropout regulator adjustment method. The method is based on a low-dropout regulator, which includes a bandgap reference circuit, a voltage divider circuit, and an LDO circuit. The bandgap reference circuit generates a bandgap reference voltage and adjusts itself using a reference adjustment code to regulate the bandgap reference voltage. The voltage divider circuit is connected to the bandgap reference circuit to generate a bandgap reference voltage based on the bandgap reference voltage and adjusts itself using a voltage divider adjustment code to regulate the bandgap reference voltage. The LDO circuit is connected to the voltage divider circuit and generates an LDO output voltage based on the bandgap reference voltage. The method includes:

[0008] The low dropout regulator was tested for the first time, and the first bandgap reference voltage and the first LDO output voltage were obtained.

[0009] The adjustment value is obtained based on the first bandgap reference voltage and the target bandgap reference voltage, and the reference adjustment code corresponding to the adjustment value is obtained based on the adjustment value;

[0010] The offset voltage is obtained based on the first bandgap reference voltage and the first LDO output voltage, and the second LDO output voltage corresponding to the reference trimming code is obtained based on the offset voltage, the first bandgap reference voltage, and the trimming value.

[0011] The voltage divider adjustment code is obtained based on the offset voltage, the target LDO output voltage, and the second LDO output voltage. The reference adjustment code and the voltage divider adjustment code are used to adjust the low dropout regulator.

[0012] In one or more embodiments of the present invention, the step of "obtaining a trimming value based on a first bandgap reference voltage and a target bandgap reference voltage, and obtaining a reference trimming code corresponding to the trimming value based on the trimming value" includes:

[0013] Obtain the difference between the target bandgap reference voltage and the first bandgap reference voltage, and obtain the adjustment value based on the difference;

[0014] Obtain the base adjustment code corresponding to the adjustment value based on the adjustment value.

[0015] In one or more embodiments of the present invention, the step of "obtaining the offset voltage based on the first bandgap reference voltage and the first LDO output voltage" includes:

[0016] The offset voltage V os =V OUT-test -A×V BG-test ;

[0017] In the formula, V OUT-test V is the output voltage of the first LDO. BG-test is the first bandgap reference voltage, and A is the scaling factor between the first LDO output voltage and the first bandgap reference voltage.

[0018] In one or more embodiments of the present invention, the LDO circuit further includes an off-chip circuit, the off-chip circuit including a first feedback resistor and a second feedback resistor, the first end of the second feedback resistor is connected to the output terminal of the LDO circuit, the second end of the second feedback resistor is connected to the first end of the first feedback resistor, the bandgap reference circuit and the voltage divider circuit to form a floating ground port of the off-chip circuit and generate a floating ground voltage, and the second end of the first feedback resistor is connected to the ground potential.

[0019] The phrase "obtaining offset voltage based on the first bandgap reference voltage and the first LDO output voltage" includes:

[0020] The offset voltage V os =V OUT-test -A×V BG-test -V ADJ ;

[0021] In the formula, V OUT-test V is the output voltage of the first LDO. BG-test V is the first bandgap reference voltage, A is the proportionality coefficient between the first LDO output voltage and the first bandgap reference voltage, and V is the first bandgap reference voltage. ADJ This is the floating ground voltage.

[0022] In one or more embodiments of the present invention, the step of "obtaining the second LDO output voltage corresponding to the reference trimming code based on the offset voltage, the first bandgap reference voltage, and the trimming value" includes:

[0023] The second LDO output voltage V OUT_ch =A×(V) BG-test +V BG-TRIM )+V os ;

[0024] In the formula, A is the proportionality coefficient between the first LDO output voltage and the first bandgap reference voltage, and V BG-test V is the first bandgap reference voltage. BG-TRIM For adjustment value, V os This is the offset voltage.

[0025] In one or more embodiments of the present invention, the LDO circuit further includes an off-chip circuit, the off-chip circuit including a first feedback resistor and a second feedback resistor, the first end of the second feedback resistor is connected to the output terminal of the LDO circuit, the second end of the second feedback resistor is connected to the first end of the first feedback resistor, the bandgap reference circuit and the voltage divider circuit to form a floating ground port of the off-chip circuit and generate a floating ground voltage, and the second end of the first feedback resistor is connected to the ground potential.

[0026] The phrase "obtaining the second LDO output voltage corresponding to the reference trimming code based on the offset voltage, the first bandgap reference voltage, and the trimming value" includes:

[0027] The second LDO output voltage V OUT_ch =A×(V) BG-test +V BG-TRIM )+V os +V ADJ ;

[0028] In the formula, A is the proportionality coefficient between the first LDO output voltage and the first bandgap reference voltage, and V BG-test V is the first bandgap reference voltage. BG-TRIM For adjustment value, V ADJ For floating ground voltage, V os This is the offset voltage.

[0029] In one or more embodiments of the present invention, the step of "obtaining a voltage divider adjustment code based on the offset voltage, the target LDO output voltage, and the second LDO output voltage" includes:

[0030] The adjustment accuracy coefficient is obtained based on the target LDO output voltage, the second LDO output voltage, and the offset voltage. In the formula, V OUT_set V is the target LDO output voltage. OUT_ch V is the output voltage of the second LDO. os Offset voltage;

[0031] The corresponding voltage divider trimming code is obtained based on the trimming accuracy coefficient.

[0032] In one or more embodiments of the present invention, the method further includes: performing a second test on the adjusted low-dropout regulator and obtaining the corresponding third LDO output voltage, and screening low-dropout regulators based on the corresponding third LDO output voltage and the target LDO output voltage.

[0033] One embodiment of the present invention provides a low dropout regulator, which is used to generate a target LDO output voltage based on the low dropout regulator tuning method described above.

[0034] One embodiment of the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the low-dropout regulator tuning method as described in any embodiment.

[0035] An embodiment of the present invention also provides a computer-readable storage medium carrying computer-executable instructions, which, when executed by a processor, are used to implement the low-dropout regulator tuning method as described in any embodiment.

[0036] Compared with existing technologies, the low-dropout regulator, its adjustment method, electronic equipment, and readable storage medium of this invention obtain adjustment codes by means of the relationship between the bandgap reference test voltage, the bandgap reference adjustment voltage, the LDO target output voltage, and the LDO test output voltage. All adjustment codes can be obtained by performing one wafer test, and the second wafer test is sufficient for wafer screening, saving chip development time. The adjustment algorithm proposed in this invention considers the offset voltage of the chip in actual manufacturing and the influence of the bandgap reference circuit after adjustment, improving the accuracy of the adjustment algorithm and thus improving output precision. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart of the low-dropout regulator adjustment method in Embodiment 1 of the present invention.

[0039] Figure 2 This is a block diagram illustrating the principle of the low-dropout voltage regulator in Embodiment 1 of the present invention.

[0040] Figure 3 This is a block diagram illustrating the principle of the low-dropout regulator in Embodiment 2 of the present invention.

[0041] Figure 4 This is a hardware structure diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0043] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0044] Example 1

[0045] like Figure 1 As shown, a method for adjusting a low-dropout voltage regulator according to an embodiment of the present invention includes:

[0046] Step S1: Perform the first test on the low dropout regulator and obtain the first bandgap reference voltage V. BG-test and the first LDO output voltage V OUT-test .

[0047] Step S2, based on the first bandgap reference voltage V BG-test and the target bandgap reference voltage V BG-set Obtain the adjustment value V BG-TRIM And based on the adjustment value V BG-TRIM Obtain the adjustment value V BG-TRIM The corresponding baseline tuning code is code1.

[0048] Step S3, based on the first bandgap reference voltage V BG-test and the first LDO output voltage V OUT-test Obtain the offset voltage V OS And based on the offset voltage V OS First bandgap reference voltage V BG-test And the second LDO output voltage V corresponding to the reference trimming code code1 for obtaining the trimming value. OUT-ch .

[0049] Step S4, based on the offset voltage V OS Target LDO output voltage V OUT_set and the second LDO output voltage V OUT-ch Obtain the voltage divider adjustment code code2, the base adjustment code code1, and the voltage divider adjustment code code2 for adjusting the low dropout voltage regulator.

[0050] Step S5: Perform a second test on the adjusted low-dropout regulator and obtain the corresponding third LDO output voltage. Based on the corresponding third LDO output voltage and the target LDO output voltage V...OUT_set Screening and adjusting low-dropout regulators. It's understandable that screening can proceed after the second test, and the third LDO output voltage must meet the target LDO output voltage V. OUT_set If the demand is met, the corresponding low-dropout voltage regulator will be adjusted accordingly.

[0051] Furthermore, the low-dropout regulator adjustment method in this embodiment is based on, for example... Figure 2 The low-dropout regulator shown is implemented.

[0052] like Figure 2 As shown, it can be understood that the low-dropout regulator in the chip wafer testing process includes the chip body 10 and external circuitry 20. In this embodiment, the low-dropout regulator includes a bandgap reference circuit 11, a voltage divider circuit 12, and an LDO circuit. The bandgap reference circuit 11 is used to generate a bandgap reference voltage V. BG It adjusts itself using reference adjustment code 1 to regulate the bandgap reference voltage V. BG The voltage divider circuit 12 is connected to the bandgap reference circuit 11 to measure the bandgap reference voltage V. BG Voltage division is performed to generate a bandgap reference voltage V. BG-out The voltage divider circuit 12 adjusts itself using the voltage divider adjustment code 2 to regulate the bandgap reference voltage V. BG-out The LDO circuit is connected to voltage divider circuit 12 to form the output terminal VOUT of the LDO circuit, and is based on the bandgap reference voltage V. BG-out Generate LDO output voltage V OUT .

[0053] The bandgap reference circuit 11 includes a temperature drift control resistor R. TC By controlling the temperature drift resistor R TC Adjustments are made to regulate the bandgap reference voltage V. BG .

[0054] like Figure 2 As shown, in an optional embodiment, the voltage divider circuit 12 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the output terminal of the bandgap reference circuit 11, and the second end of the first resistor R1 is connected to the first end of the second resistor R2 to form the output terminal of the voltage divider circuit 12. The voltage divider circuit 12 generates a bandgap reference voltage V through its output terminal. BG-out The second terminal of the second resistor R2 is connected to the external circuit 20. The bandgap reference voltage V is adjusted by modifying the first resistor R1. BG-out This allows for the control of the LDO output voltage V. OUT The adjustment.

[0055] In one embodiment, the LDO circuit includes a first-stage voltage regulator circuit 13, a second-stage voltage regulator circuit 14, and off-chip circuitry 20. The first-stage voltage regulator circuit 13 includes a first amplifier AMP1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first MOSFET M1. The first input terminal of the first amplifier AMP1 is connected to a voltage divider circuit 12 to receive a bandgap reference voltage V. BG-out The second input terminal of the first amplifier AMP1 is connected to the second terminal of the fourth resistor R4 and the first terminal of the third resistor R3. The output terminal of the first amplifier AMP1 is connected to the control terminal of the first MOSFET M1. The first terminal of the first MOSFET M1 is connected to the power supply voltage VDD. The second terminal of the first MOSFET M1 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the first terminal of the fourth resistor R4 and the second-stage voltage regulator circuit 14 to generate a reference voltage V. REF .

[0056] The second-stage voltage regulator circuit 14 includes a second amplifier AMP2 and a second MOSFET M2. The first input terminal of the second amplifier AMP2 is connected to the first-stage voltage regulator circuit 13 to receive a reference voltage V. REF The second input terminal of the second amplifier AMP2 is connected to the second terminal of the second MOS transistor M2 and the external circuit 20 to form the output terminal VOUT of the LDO circuit. The output terminal of the second amplifier AMP2 is connected to the control terminal of the second MOS transistor M2. The first terminal of the second MOS transistor M2 is connected to the input voltage VIN.

[0057] like Figure 2 As shown, the off-chip circuit 20 includes a first feedback resistor R. FB1 Second feedback resistor R FB2 The equivalent series resistance ESR, load capacitance CL, and load current source Iload. Second feedback resistor R. FB2 The first terminal is connected to the output terminal VOUT of the LDO circuit, and the second feedback resistor R FB2 The second terminal is connected to the first feedback resistor R FB1 The first terminal is connected, and the first feedback resistor R FB1 The first terminal is connected to the second terminal of the third resistor R3 of the first-stage voltage regulator circuit 13 and the second terminal of the second resistor R2 of the voltage divider circuit 12, forming the floating ground terminal of the off-chip circuit. The first feedback resistor R FB1 The second terminal is connected to ground potential, and the first feedback resistor R FB1 Used to adjust the LDO output voltage V OUT The first terminal of the equivalent series resistance ESR is connected to the second feedback resistance R. FB2The first terminal is connected to the output terminal VOUT of the LDO circuit. The second terminal of the equivalent series resistance ESR is connected to the first terminal of the load capacitor CL. The second terminal of the load capacitor CL is connected to ground potential. The first terminal of the load current source Iload is connected to the second feedback resistor R. FB2 The first terminal is connected to the output terminal of the LDO circuit, and the load current source Iload is connected to ground potential. The current flows through the second feedback resistor R. FB2 The current is the chip-to-ground current I. ADJ Chip to ground current I ADJ This is a positive temperature coefficient current. It can be understood that the external circuit 20 generates a floating ground voltage V through its floating ground terminal. ADJ And floating ground voltage V ADJ =Chip-to-ground current I ADJ *Second feedback resistor R FB2

[0058] It is understandable that the second-stage voltage regulator circuit 14 is connected to the external circuit 20 to form a linear voltage regulator circuit structure, and the second feedback resistor R is adjusted. FB2 The output voltage V of the LDO can be adjusted by the resistance value. OUT .

[0059] In one embodiment, step S2 specifically includes: acquiring the target bandgap reference voltage V. BG-set With the first bandgap reference voltage V BG-test The difference V between BG-D And based on this difference V BG-D Obtain the adjustment value V BG-TRIM Based on the adjustment value V BG-TRIM Obtain the adjustment value V BG-TRIM The corresponding baseline tuning code is code1.

[0060] It is understandable that by adjusting the temperature drift control resistor R... TC Adjustments are made to regulate the bandgap reference voltage V. BG That is, by adjusting the temperature drift control resistor R TC The temperature drift curve of the LDO output voltage can be adjusted by the resistance value.

[0061] In one embodiment, the bandgap reference voltage V at 85°C is used. BG A voltage adjustment to 1.222V will yield an LDO output voltage V with near-zero temperature drift. OUT That is, the target bandgap reference voltage V. BG-set It is 1.222V.

[0062] Specifically, the target bandgap reference voltage V BG-set The target bandgap reference voltage V is 1.222V (at a temperature of 85℃). BG-setWith the first bandgap reference voltage V BG-test The difference V between BG-D For: V BG-D =1.222-V BG-test By consulting the tuning code table shown in Table 1, the difference V is obtained. BG-D The closest correction value V BG-TRIM And based on the adjustment value V BG-TRIM Obtain the corresponding baseline tuning code, code1.

[0063] For example, the target bandgap reference voltage V BG-set With the first bandgap reference voltage V BG-test The difference V between BG-D If the value is -15.0mV, then according to Table 1, the adjustment value V is... BG-TRIM It should be -15.8mV, and its corresponding reference adjustment code 1 is 110. That is, the temperature drift control resistor R is adjusted according to the reference adjustment code 1 of 110. TC Adjustments are performed. The adjusted bandgap reference voltage is the adjusted value V. BG-TRIM With the first bandgap reference voltage V BG-test The sum of these values, i.e., the adjusted bandgap reference voltage in this example, is 1221.2mV.

[0064] Table 1 Temperature Drift Control Resistor Trimming Table

[0065] Trim code1<2:0> <![CDATA[V BG-TRIM / mV]]> 111 0.0 110 -15.8 101 -29.1 100 -40.4 011 -50.2 010 -58.6 001 -66.1 000 -72.7

[0066] In this embodiment, the temperature drift control resistor R is adjusted using the reference adjustment code code1. TC After adjustment, the first bandgap reference voltage V output by the bandgap reference circuit BG-test This becomes a negative temperature coefficient voltage, thereby offsetting the positive temperature coefficient chip-to-ground current I. ADJ The effect of temperature drift was investigated, resulting in an LDO output voltage V with near-zero temperature drift. OUT This improves the output accuracy of the low-voltage regulator chip. It is understood that the trimming code table shown in Table 1 is only one possible implementation; those skilled in the art can use other reference trimming codes (code1 and trimming value V) according to the actual circuit structure and specifications. BG-TRIM The correspondence.

[0067] In one embodiment, in step S3, "based on the first bandgap reference voltage V" BG-test and the first LDO output voltage V OUT-test Obtain the offset voltage V OS Specifically, it includes:

[0068] Offset voltage V OS =VOUT-test -A×V BG-test -V ADJ .

[0069] In the formula, V OUT-test V is the output voltage of the first LDO. BG-test V is the first bandgap reference voltage, A is the proportionality coefficient between the first LDO output voltage and the first bandgap reference voltage, and V is the first bandgap reference voltage. ADJ Let A be the floating ground voltage. Further, A is the scaling factor between the first LDO output voltage and the first bandgap reference voltage, ignoring offset voltage and floating ground voltage.

[0070] like Figure 2 As shown, the offset voltage V in this application OS Including the offset voltage V of the first-stage voltage regulator circuit OS_BUF and the offset voltage V of the second-stage voltage regulator circuit OS_EA V OS =V OS_BUF +V OS_EA And V ADJ =I ADJ ×R FB1 I ADJ R is the chip's current to ground. FB1 R is the first feedback resistor used to regulate the LDO output voltage of the chip. FB1 .

[0071] It is understandable that the offset voltage V is ignored. os The first LDO output voltage V OUT-test With the first bandgap reference voltage V BG-test The proportionality coefficient between them is determined by the circuit structure, for example... Figure 2 The low dropout regulator chip shown has a first LDO output voltage V. OUT-test Offset voltage V of the first-stage voltage regulator circuit OS_BUF The offset voltage V of the second-stage voltage regulator circuit OS_EA and the chip's current to ground I ADJ The relationship is:

[0072]

[0073] Therefore, in such Figure 2 In the low-dropout regulator shown, the value of A is... The calculation method for the A value may differ for different circuit structures. Those skilled in the art can obtain the A value based on the internal resistor layout of the low dropout regulator chip when performing wafer testing, which will not be elaborated upon in this application.

[0074] In step S3, "based on offset voltage V" OS First bandgap reference voltage V BG-testAnd the second LDO output voltage V corresponding to the reference trimming code code1 for obtaining the trimming value. OUT-ch Specifically, this includes: the output voltage V of the second LDO. OUT_ch =A×(V) BG-test +V BG-TRIM )+V os +V ADJ .

[0075] In the formula, A is the output voltage V of the first LDO. OUT-test With the first bandgap reference voltage V BG-test The proportionality coefficient between them, V BG-TRIM For adjustment value, V ADJ For floating ground voltage, V os This is the offset voltage. It can be understood that the second LDO output voltage V... OUT-ch Represents the temperature drift control resistor R TC The LDO output voltage is adjusted using the reference adjustment code code1.

[0076] In one embodiment, step S4 "based on offset voltage V" OS Target LDO output voltage V OUT_set and the second LDO output voltage V OUT-ch Obtaining the voltage divider adjustment code "code2" specifically includes: based on the second LDO output voltage V OUT_ch Target LDO output voltage V OUT_set and offset voltage V os Obtain the adjustment accuracy coefficient K ACC And based on the second adjustment coefficient K ACC Obtain the corresponding voltage divider adjustment code (code2). Then, adjust the low-dropout regulator based on the baseline adjustment code (code1) and the voltage divider adjustment code (code2).

[0077] Adjustment accuracy coefficient In the formula V OUT_set V is the target LDO output voltage. OUT-ch V is the output voltage of the second LDO. os This is the offset voltage. The adjustment accuracy coefficient K is obtained by consulting the adjustment code table. ACC The closest output precision is used to obtain the voltage divider modifier code2 corresponding to that output precision.

[0078] In one embodiment, the relationship between the voltage divider trimming code 2 and the LDO output precision is shown in Table 2, the trimming code table. For example, the trimming precision coefficient K... ACCThe output accuracy is 99.3%, which is closest to 99% in the adjustment code table (Table 2). Therefore, in this embodiment, the voltage divider adjustment code 2 is 1110. Based on the voltage divider adjustment code 2 of 1110, the first resistor R1 can be adjusted to control the output accuracy of the low dropout regulator chip.

[0079] Table 2 VOUT Output Accuracy Trimming Table

[0080]

[0081]

[0082] Furthermore, step S4, "adjusting the low-dropout regulator based on the reference adjustment code 1 and the voltage divider adjustment code 2," includes:

[0083] The bandgap reference circuit includes a temperature drift control resistor R. TC The temperature drift control resistor R is adjusted using the reference tuning code 1. TC Adjustments are made to enable the bandgap reference circuit to output the target bandgap reference voltage V. BG-set .

[0084] The voltage divider circuit includes a first resistor R1. The first resistor R1 is adjusted using voltage divider adjustment code 2 to enable the low-voltage regulator to obtain the target LDO output voltage V. OUT_set .

[0085] This embodiment applies to low-voltage regulator chips that have a floating ground pin (ADJ PIN) but no feedback voltage pin (VFB PIN), such as a 3-pin low-voltage regulator chip. Figure 2 As shown, unlike traditional 4-pin low-voltage regulator chips, 3-pin low-voltage regulator chips do not have a feedback-free voltage pin (VFB PIN), but only an input voltage pin (VIN PIN), an output voltage pin (VOUT PIN), and a floating ground pin (ADJ PIN).

[0086] Example 2

[0087] like Figure 3 As shown, the adjustment method proposed in this invention is also applicable to traditional 4-pin low-voltage regulator chips. The difference between this embodiment and Embodiment 1 is that the voltage divider circuit 12 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the output terminal of the bandgap reference circuit 11, and the second end of the first resistor R1 is connected to the first end of the second resistor R2 to form the output terminal of the voltage divider circuit 12. The voltage divider circuit 12 generates a bandgap reference voltage V through its output terminal. BG-outThe second terminal of the second resistor R2 is connected to ground potential GND. The bandgap reference voltage V is adjusted by modifying the first resistor R1. BG-out This allows for the control of the LDO output voltage V. OUT The adjustment.

[0088] The LDO circuit includes a first-stage voltage regulator circuit 13, a second-stage voltage regulator circuit 14, and an external circuit 20.

[0089] The first-stage voltage regulator circuit 13 includes a first amplifier AMP1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first MOSFET M1. The first input terminal of the first amplifier is connected to the voltage divider circuit 12 to receive the bandgap reference voltage V. BG-out The second input terminal of the first amplifier is connected to the second terminal of the fourth resistor R4 and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to ground potential GND. The output terminal of the first amplifier is connected to the control terminal of the first MOSFET M1. The first terminal of the first MOSFET M1 is connected to the power supply voltage VDD. The second terminal of the first MOSFET M1 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the first terminal of the fourth resistor R4 and the second-stage voltage regulator circuit 14 to generate a reference voltage V. REF .

[0090] The second-stage voltage regulator circuit 14 includes a second amplifier AMP2 and a second MOSFET M2. The first input terminal of the second amplifier AMP2 is connected to the first-stage voltage regulator circuit 13 to receive a reference voltage V. REF The second input terminal of the second amplifier AMP2 is connected to the second terminal of the second MOS transistor M2 and the external circuit 20. The output terminal of the second amplifier AMP2 is connected to the control terminal of the second MOS transistor M2. The first terminal of the second MOS transistor M2 is connected to the input voltage VIN.

[0091] like Figure 3 As shown, the off-chip circuit 20 includes a first feedback resistor R. FB1 Second feedback resistor R FB2 The equivalent series resistance ESR, load capacitance CL, and load current source Iload. Second feedback resistor R. FB2 The first terminal is connected to the output terminal of the LDO circuit, and the second feedback resistor R FB2 The second terminal is connected to the first feedback resistor R FB1 The first terminal is connected, and the first feedback resistor R FB1 The second terminal is connected to ground potential GND, and the first feedback resistor R FB1 Used to regulate the LDO output voltage VOUT. The first terminal of the equivalent series resistance ESR is connected to the second feedback resistor R. FB2The first terminal is connected to the output terminal of the LDO circuit. The second terminal of the equivalent series resistance ESR is connected to the first terminal of the load capacitor CL. The second terminal of the load capacitor CL is connected to ground potential GND. The first terminal of the load current source Iload is connected to the second feedback resistor R. FB2 The first terminal is connected to the output terminal of the LDO circuit, and the load current source Iload is connected to the ground potential GND.

[0092] It is understandable that the second-stage voltage regulator circuit 14 is connected to the external circuit 20 to form a linear voltage regulator circuit structure, and the second feedback resistor R is adjusted. FB2 The output voltage VOUT of the LDO can be obtained by adjusting the resistance value.

[0093] This embodiment provides a method for adjusting a low-dropout voltage regulator, the method comprising:

[0094] Step S1: Perform the first test on the low dropout regulator and obtain the first bandgap reference voltage V. BG-test and the first LDO output voltage V OUT-test .

[0095] Step S2, based on the first bandgap reference voltage V BG-test and the target bandgap reference voltage V BG-set Obtain the adjustment value V BG-TRIM And based on the adjustment value V BG-TRIM Obtain the adjustment value V BG-TRIM The corresponding baseline tuning code is code1.

[0096] Step S3, based on the first bandgap reference voltage V BG-test and the first LDO output voltage V OUT-test Obtain the offset voltage V OS And based on the offset voltage V OS First bandgap reference voltage V BG-test And the second LDO output voltage V corresponding to the reference trimming code code1 for obtaining the trimming value. OUT-ch .

[0097] Step S4, based on the offset voltage V OS Target LDO output voltage V OUT_set and the second LDO output voltage V OUT-ch Obtain the voltage divider adjustment code 2, and adjust the low dropout regulator based on the base adjustment code 1 and the voltage divider adjustment code 2.

[0098] Step S5: Perform a second test on the adjusted low-dropout regulator and obtain the corresponding third LDO output voltage. Based on the corresponding third LDO output voltage and the target LDO output voltage V... OUT_setScreening and adjusting low-dropout regulators. It's understandable that screening can proceed after the second test, and the third LDO output voltage must meet the target LDO output voltage V. OUT_set If the demand is met, the corresponding low-dropout voltage regulator will be adjusted accordingly.

[0099] In this embodiment, step S2 specifically includes: obtaining the target bandgap reference voltage V. BG-set With the first bandgap reference voltage V BG-test The difference V between BG-D And based on this difference V BG-D Obtain the adjustment value V BG-TRIM Based on the adjustment value V BG-TRIM Obtain the adjustment value V BG-TRIM The corresponding baseline tuning code is code1.

[0100] It is understandable that by adjusting the temperature drift control resistor R... TC Adjustments are made to regulate the bandgap reference voltage V. BG That is, by adjusting the temperature drift control resistor R TC The temperature drift curve of the LDO output voltage can be adjusted by the resistance value.

[0101] In this embodiment, the bandgap reference voltage V at 85°C is... BG By adjusting the voltage to 1.232V, an LDO output voltage V with near-zero temperature drift can be obtained. OUT That is, the target bandgap reference voltage V. BG-set It is 1.222V.

[0102] Specifically, the target bandgap reference voltage V BG-set The target bandgap reference voltage V is 1.232V (at a temperature of 85℃). BG-set With the first bandgap reference voltage V BG-test The difference V between BG-D For: V BG-D =1.222-V BG-test By consulting the tuning code table shown in Table 1, the difference V is obtained. BG-D The closest correction value V BG-TRIM And based on the adjustment value V BG-TRIM Obtain the corresponding baseline tuning code, code1.

[0103] In this embodiment, step S3, "based on the first bandgap reference voltage V" BG-test and the first LDO output voltage V OUT-test Obtain the offset voltage V OS Specifically, it includes:

[0104] Offset voltage V OS =V OUT-test -A×V BG-test.

[0105] In the formula, V OUT-test V is the output voltage of the first LDO. BG-test Let A be the first bandgap reference voltage, and let A be the scaling factor between the first LDO output voltage and the first bandgap reference voltage. Further, let A be the scaling factor between the first LDO output voltage and the first bandgap reference voltage when offset voltage is ignored.

[0106] like Figure 3 As shown, the offset voltage V in this application OS Including the offset voltage V of the first-stage voltage regulator circuit OS_BUF and the offset voltage V of the second-stage voltage regulator circuit OS_EA V OS =V OS_BUF +V OS_EA R FB1 R is the first feedback resistor used to regulate the LDO output voltage of the chip. FB1 .

[0107] It is understandable that the offset voltage V is ignored. os The first LDO output voltage V OUT-test With the first bandgap reference voltage V BG-test The proportionality coefficient between them is determined by the circuit structure, for example... Figure 2 The low dropout regulator chip shown has a first LDO output voltage V. OUT-test Offset voltage V of the first-stage voltage regulator circuit OS_BUF The offset voltage V of the second-stage voltage regulator circuit OS_EA The relationship is:

[0108]

[0109] Therefore, in such Figure 3 In the low-dropout regulator shown, the value of A is... The calculation method for the A value may differ for different circuit structures. Those skilled in the art can obtain the A value based on the internal resistor layout of the low dropout regulator chip when performing wafer testing, which will not be elaborated upon in this application.

[0110] In step S3, "based on offset voltage V" OS First bandgap reference voltage V BG-test And the second LDO output voltage V corresponding to the reference trimming code code1 for obtaining the trimming value. OUT-ch Specifically, this includes: the output voltage V of the second LDO. OUT_ch =A×(V) BG-test +V BG-TRIM )+V os .

[0111] In the formula, VOUT-ch A is the output voltage of the second LDO, and A is the output voltage of the first LDO, V. OUT-test With the first bandgap reference voltage V BG-test The proportionality coefficient between them, V BG-TRIM For adjustment value, V os This is the offset voltage. It can be understood that the second LDO output voltage V... OUT-ch Represents the temperature drift control resistor R TC The LDO output voltage after adjustment using the reference adjustment code code1. Further, A is the first LDO output voltage V when offset voltage is ignored. OUT-test With the first bandgap reference voltage V BG-test The proportional coefficient between them.

[0112] In one embodiment, step S4 "based on offset voltage V" OS Target LDO output voltage V OUT_set and the second LDO output voltage V OUT-ch Obtaining the voltage divider adjustment code "code2" specifically includes: based on the first LDO output voltage V OUT_ch LDO target output voltage V OUT_set and offset voltage V os Obtain the adjustment accuracy coefficient K ACC And based on the second adjustment coefficient K ACC Obtain the corresponding voltage divider and adjustment code code2.

[0113] Adjustment accuracy coefficient In the formula, V OUT_set V is the target LDO output voltage. OUT-ch V is the output voltage of the second LDO. os This is the offset voltage. The adjustment accuracy coefficient K is obtained by consulting the adjustment code table (Table 2). ACC The closest output precision is used to obtain the voltage divider modifier code2 corresponding to that output precision.

[0114] As can be seen from the above, the main difference between Example 2 and Example 1 lies in whether the low-voltage regulator has a floating ground voltage V due to the pin type of the low-voltage regulator chip. ADJ When the low-voltage regulator chip has a floating ground pin, the offset voltage V os The calculation needs to take into account the floating ground voltage, and the first LDO output voltage V OUT-test With the first bandgap reference voltage V BG-test The proportionality coefficient between them needs to ignore the offset voltage V. os and floating ground voltage V ADJ When the low-voltage regulator chip does not have a floating ground pin, the offset voltage V os The calculation does not need to consider the floating ground voltage V. ADJAnd the first LDO output voltage V OUT-test With the first bandgap reference voltage V BG-test The proportionality coefficient between them only needs to ignore the offset voltage V. os .

[0115] An embodiment of the present invention also provides a low-dropout regulator for generating a target LDO output voltage based on a low-dropout regulator tuning method as described in Embodiment 1 or 2.

[0116] Figure 4 A hardware structure diagram of an electronic device according to an embodiment of this specification is shown. Figure 4 As shown, the electronic device 30 may include at least one processor 31, a memory 32 (e.g., non-volatile memory), a RAM 33, and a communication interface 34, and the at least one processor 31, memory 32, RAM 33, and communication interface 34 are connected together via a bus 35. The at least one processor 31 executes at least one computer-readable instruction stored or encoded in the memory 32.

[0117] It should be understood that the computer-executable instructions stored in memory 32, when executed, cause at least one processor 31 to perform the above-described combinations in the various embodiments of this specification. Figure 1 The description includes various operations and functions.

[0118] In the embodiments of this specification, electronic device 30 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile electronic device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable electronic device, consumer electronic device, etc.

[0119] According to one embodiment, a program product, such as a machine-readable medium, is provided. The machine-readable medium may have instructions (i.e., the elements implemented in software as described above), which, when executed by a machine, cause the machine to perform the above-described combinations of the various embodiments of this specification. Figure 1 The various operations and functions described. Specifically, a system or apparatus equipped with a readable storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer or processor of the system or apparatus to read and execute the instructions stored in the readable storage medium.

[0120] In this case, the program code read from the readable medium itself can perform the functions of any of the above embodiments, and therefore the machine-readable code and the readable storage medium storing the machine-readable code constitute a part of this specification.

[0121] Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer or the cloud via a communication network.

[0122] Those skilled in the art will understand that the various embodiments disclosed above can be modified and varied without departing from the spirit of the invention. Therefore, the scope of protection of this specification should be defined by the appended claims.

[0123] It should be noted that not all steps and units in the above process and system structure diagrams are mandatory; some steps or units can be omitted according to actual needs. The execution order of each step is not fixed and can be determined as needed. The device structure described in the above embodiments can be a physical structure or a logical structure. That is, some units may be implemented by the same physical client, or some units may be implemented by multiple physical clients, or they may be jointly implemented by certain components in multiple independent devices.

[0124] In the above embodiments, the hardware units or modules can be implemented mechanically or electrically. For example, a hardware unit, module, or processor may include permanent dedicated circuitry or logic (such as a dedicated processor, FPGA, or ASIC) to perform the corresponding operation. The hardware unit or processor may also include programmable logic or circuitry (such as a general-purpose processor or other programmable processor), which can be temporarily configured by software to perform the corresponding operation. The specific implementation method (mechanical, dedicated permanent circuitry, or temporarily configured circuitry) can be determined based on cost and time considerations.

[0125] The specific embodiments described above with reference to the accompanying drawings are exemplary embodiments, but do not represent all embodiments that can be implemented or fall within the scope of the claims. The term "exemplary" as used throughout this specification means "serving as an example, instance, or illustration" and does not imply that it is "preferred" or "advantageous" compared to other embodiments. Specific details are included to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0126] The foregoing description of this disclosure is provided to enable any person skilled in the art to implement or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles applicable herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. A method for adjusting a low-dropout voltage regulator, characterized in that, The method is based on a low-dropout regulator, which includes a bandgap reference circuit, a voltage divider circuit, and an LDO circuit. The bandgap reference circuit generates a bandgap reference voltage and adjusts itself using a reference adjustment code to regulate the bandgap reference voltage. The voltage divider circuit is connected to the bandgap reference circuit to generate a bandgap reference voltage based on the bandgap reference voltage and adjusts itself using a voltage divider adjustment code to regulate the bandgap reference voltage. The LDO circuit is connected to the voltage divider circuit and generates an LDO output voltage based on the bandgap reference voltage. The LDO circuit includes a first-stage voltage regulator circuit and a second-stage voltage regulator circuit. The first-stage voltage regulator circuit includes a first amplifier, whose first input terminal is connected to the voltage divider circuit, and whose second input terminal is connected to its output terminal. The second-stage voltage regulator circuit includes a second amplifier, whose first input terminal is connected to the output terminal of the first-stage voltage regulator circuit, and whose second input terminal is connected to its output terminal to generate the LDO output voltage. The method includes: The low dropout regulator was tested for the first time, and the first bandgap reference voltage and the first LDO output voltage were obtained. The adjustment value is obtained based on the first bandgap reference voltage and the target bandgap reference voltage, and the reference adjustment code corresponding to the adjustment value is obtained based on the adjustment value; The offset voltage is obtained based on the first bandgap reference voltage and the first LDO output voltage. The offset voltage includes the offset voltage of the first-stage voltage regulator circuit and the offset voltage of the second-stage voltage regulator circuit. The second LDO output voltage corresponding to the reference trimming code is obtained based on the offset voltage, the first bandgap reference voltage, and the trimming value. The voltage divider adjustment code is obtained based on the offset voltage, the target LDO output voltage, and the second LDO output voltage. The reference adjustment code and the voltage divider adjustment code are used to adjust the low dropout regulator.

2. The low-dropout regulator adjustment method according to claim 1, characterized in that, The adjustment value is obtained based on the first bandgap reference voltage and the target bandgap reference voltage, and the reference adjustment code corresponding to the adjustment value is obtained based on the adjustment value, including: Obtain the difference between the target bandgap reference voltage and the first bandgap reference voltage, and obtain the adjustment value based on the difference; Obtain the base adjustment code corresponding to the adjustment value based on the adjustment value.

3. The low-dropout voltage regulator adjustment method according to claim 1, characterized in that, The offset voltage is obtained based on the first bandgap reference voltage and the first LDO output voltage, including: The offset voltage ; In the formula, This is the output voltage of the first LDO. is the first bandgap reference voltage, and A is the scaling factor between the first LDO output voltage and the first bandgap reference voltage.

4. The low-dropout regulator adjustment method according to claim 1, characterized in that, The LDO circuit also includes an off-chip circuit, which includes a first feedback resistor and a second feedback resistor. The first end of the second feedback resistor is connected to the output terminal of the LDO circuit. The second end of the second feedback resistor is connected to the first end of the first feedback resistor, the bandgap reference circuit, and the voltage divider circuit to form a floating ground port of the off-chip circuit and generate a floating ground voltage. The second end of the first feedback resistor is connected to the ground potential. The offset voltage is obtained based on the first bandgap reference voltage and the first LDO output voltage, including: The offset voltage ; In the formula, This is the output voltage of the first LDO. The first bandgap reference voltage, This is the scaling factor between the first LDO output voltage and the first bandgap reference voltage. This is the floating ground voltage.

5. The low-dropout regulator adjustment method according to claim 1, characterized in that, The second LDO output voltage corresponding to the reference trimming code is obtained based on the offset voltage, the first bandgap reference voltage, and the trimming value, including: The second LDO output voltage ; In the formula, A is the proportionality coefficient between the first LDO output voltage and the first bandgap reference voltage. The first bandgap reference voltage, For adjustment value, This is the offset voltage.

6. The low-dropout regulator adjustment method according to claim 1, characterized in that, The LDO circuit also includes an off-chip circuit, which includes a first feedback resistor and a second feedback resistor. The first end of the second feedback resistor is connected to the output terminal of the LDO circuit. The second end of the second feedback resistor is connected to the first end of the first feedback resistor, the bandgap reference circuit, and the voltage divider circuit to form a floating ground port of the off-chip circuit and generate a floating ground voltage. The second end of the first feedback resistor is connected to the ground potential. The second LDO output voltage corresponding to the reference trimming code is obtained based on the offset voltage, the first bandgap reference voltage, and the trimming value, including: The second LDO output voltage ; In the formula, This is the scaling factor between the first LDO output voltage and the first bandgap reference voltage. The first bandgap reference voltage, For adjustment value, Floating ground voltage, This is the offset voltage.

7. The low-dropout regulator adjustment method according to claim 1, characterized in that, The voltage divider adjustment code is obtained based on the offset voltage, the target LDO output voltage, and the second LDO output voltage, including: The adjustment accuracy coefficient is obtained based on the target LDO output voltage, the second LDO output voltage, and the offset voltage. In the formula, The target LDO output voltage, This is the output voltage of the second LDO. Offset voltage; The corresponding voltage divider trimming code is obtained based on the trimming accuracy coefficient.

8. The low-dropout regulator adjustment method according to claim 1, characterized in that, The method further includes: performing a second test on the adjusted low-dropout regulator and obtaining the corresponding third LDO output voltage, and screening low-dropout regulators based on the corresponding third LDO output voltage and the target LDO output voltage.

9. A low-dropout voltage regulator, characterized in that, The low-dropout regulator is used to generate a target LDO output voltage based on the low-dropout regulator tuning method as described in any one of claims 1 to 8.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the low-dropout regulator adjustment method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium carries computer-executable instructions, which, when executed by a processor, are used to implement the low-dropout regulator adjustment method as described in any one of claims 1 to 8.

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