A radio frequency power amplifier and communication device based on multi-state working mode

Abstract

The present invention proposes a radio frequency power amplifier and communication equipment based on a multi-state working mode, wherein the radio frequency power amplifier includes an input distribution matching network, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first interstage matching network, a second interstage matching network, an output adaptive matching network, and a bias network for outputting four bias signals, wherein two bias signals are respectively connected to the first interstage matching network and the second interstage matching network, and the other two bias signals are connected to the output adaptive matching network; based on the different level modes of the four bias signals and the different states of the four amplifiers, the radio frequency power amplifier is operated in different power states. In view of the requirements of different output power levels, the present invention can control the radio frequency power amplifier to be in different working states, thereby achieving high working efficiency in a wide back-off area.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a radio frequency power amplifier and communication equipment based on a multi-state working mode. Background Art

[0002] With the rapid development of the satellite communication market, especially the growing demand for high-speed satellite communication and broadband digital transmission, RF front-end transceivers are evolving towards high integration, low energy consumption, compact design and economical performance. In this process, the power amplifier, as a key component in the transmitter, not only directly affects the quality of the overall communication signal, but is also one of the parts with the highest energy consumption in the system.

[0003] Traditional power amplifiers are designed using integrated circuit technology and have encountered some bottlenecks in terms of function and performance. Specifically, the operating efficiency of power amplifiers drops significantly in the wide back-off region. As communication terminals become increasingly miniaturized and multifunctional, power amplifiers are required to support a wide range of output power levels. However, due to the internal synthesis structure and DC power consumption of traditional amplifiers, which limit the efficiency at low output power, it is difficult to maintain high operating efficiency when achieving a wide range of output power. Summary of the invention

[0004] In order to overcome the above defects in the prior art, the present invention proposes a radio frequency power amplifier and a communication device based on a multi-state working mode. According to the requirements of different output power levels, the radio frequency power amplifier can be controlled to be in different working states, so that high working efficiency can be maintained in a wide back-off area.

[0005] Different output matching networks and RF switches are integrated into an adaptive output matching network, which is controlled by a bias network. At the same time, the bias network also controls the working state of the final amplifier of each RF branch, ensuring higher working efficiency at low output power levels.

[0006] In order to achieve the purpose of the present invention, the present invention provides a radio frequency power amplifier based on a multi-state working mode. The radio frequency power amplifier includes an input distribution matching network connected via an input port, a first interstage matching network and a second interstage matching network connected to the input distribution matching network via a first amplifier and a third amplifier, respectively, and an output adaptive matching network, wherein the first interstage matching network is connected to the output adaptive matching network via a second amplifier, the second interstage matching network is connected to the output adaptive matching network via a fourth amplifier, and the output adaptive matching network is connected to the output port;

[0007] The RF power amplifier also includes a bias network that outputs four bias signals, wherein two bias signals are connected to the first inter-stage matching network and the second inter-stage matching network respectively, and the other two bias signals are connected to the output adaptive matching network;

[0008] Wherein, based on different level modes of four bias signals and different states of four amplifiers, the radio frequency power amplifier operates in different power states.

[0009] Further, the input distribution matching network includes a first transformer, a first capacitor, a first resistor, a seventh capacitor and a fourth resistor;

[0010] The third terminal and the fifth terminal of the first transformer are connected to the first terminal of the first capacitor and the first terminal of the seventh capacitor respectively, and the second terminal of the first capacitor and the second terminal of the seventh capacitor are connected to the base of the first amplifier and the third amplifier via the first terminal of the first resistor and the first terminal of the fourth resistor respectively;

[0011] The second terminal and the fourth terminal of the first transformer are grounded, and the second terminal of the first resistor and the second terminal of the fourth resistor are both connected to a power source.

[0012] Furthermore, the first inter-stage matching network includes a first inductor, a second capacitor, a third capacitor and a second resistor;

[0013] The first end of the first inductor and the first end of the second capacitor are connected to the collector of the first amplifier and serve as the first input end of the first inter-stage matching network, the second end of the second capacitor is connected to the first end of the third capacitor and serves as the second output end of the first inter-stage matching network, and the second end of the third capacitor is connected to the base of the second amplifier via the first end of the second resistor and serves as the first output end of the first inter-stage matching network;

[0014] The second end of the second resistor is connected to the bias network and serves as the second input end of the first inter-stage matching network based on the first bias signal Vb1 input. The second end of the first inductor is connected to the power supply.

[0015] Further, the second inter-stage matching network includes a fifth inductor, an eighth capacitor, a ninth capacitor and a fifth resistor;

[0016] The first end of the fifth inductor and the first end of the eighth capacitor are connected to the collector of the third amplifier and serve as the first input end of the second inter-stage matching network. The second end of the eighth capacitor is connected to the first end of the ninth capacitor and serves as the second output end of the second inter-stage matching network. The second end of the ninth capacitor is connected to the base of the fourth amplifier via the first end of the fifth resistor and serves as the first output end of the second inter-stage matching network.

[0017] The second end of the fifth resistor is connected to the bias network and serves as the second input end of the second inter-stage matching network based on the second bias signal Vb2 input. The second end of the fifth inductor is connected to the power supply.

[0018] Further, the output adaptive matching network includes a second inductor, a third inductor, a fourth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a second transformer, a fourth capacitor, a fifth capacitor, a sixth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a third resistor, a sixth resistor, a third transistor and a sixth transistor;

[0019] The first end of the second inductor is connected to the collector of the second amplifier via the first end of the third inductor and serves as the first input end of the output adaptive matching network; the second end of the third inductor is connected to the first end of the fourth capacitor and the first end of the fifth capacitor; the second end of the fifth capacitor is connected to the emitter of the third transistor and the third end of the second transformer; the collector of the third transistor is connected to the first end of the sixth capacitor and the first end of the fourth inductor;

[0020] The first end of the sixth inductor is connected to the collector of the fourth amplifier via the first end of the seventh inductor and serves as the fourth input end of the output adaptive matching network; the second end of the seventh inductor is connected to the first end of the tenth capacitor and the first end of the eleventh capacitor; the second end of the eleventh capacitor is connected to the emitter of the sixth transistor and the fifth end of the second transformer; the collector of the sixth transistor is connected to the first end of the twelfth capacitor and the first end of the eighth inductor;

[0021] The base of the third transistor and the base of the sixth transistor are connected to the first ends of the third resistor and the sixth resistor respectively; the second end of the third resistor is connected to the bias network and serves as the third input end for the third bias signal Vs1 in the output adaptive matching network, and the second end of the sixth resistor is connected to the bias network and serves as the sixth input end for the fourth bias signal Vs2 in the output adaptive matching network;

[0022] The second end of the fourth inductor is connected to the second output end of the first inter-stage matching network and serves as the second input end of the output adaptive matching network;

[0023] The second end of the eighth inductor is connected to the second output end of the second inter-stage matching network and serves as the fifth input end of the output adaptive matching network;

[0024] The second ends of the second inductor and the sixth inductor are connected to the power supply, the second ends of the fourth capacitor, the sixth capacitor, the tenth capacitor, the twelfth capacitor, and the second end and the fifth end of the second transformer are all connected to ground, and the first end of the second transformer is connected to the output port.

[0025] Furthermore, the bias network includes a logic control circuit and a bias circuit. After the control signal Vtrl is input into the logic control circuit, it is input into the bias circuit, and four bias signals are output through the bias circuit, namely, a first bias signal Vb1, a second bias signal Vb2, a third bias signal Vs1, and a fourth bias signal Vs2.

[0026] Further, the logic control circuit includes a seventh resistor, an eighth resistor, a thirteenth resistor, a fourteenth resistor, a seventh transistor and a tenth transistor;

[0027] A first end of the seventh resistor is connected to the first end of the thirteenth resistor and serves as an input end of the control signal Vtrl; a second end of the seventh resistor is connected to the first end of the eighth resistor and the base of the seventh transistor, and a collector of the seventh transistor serves as a first output end of the logic control circuit;

[0028] The second end of the thirteenth resistor is connected to the first end of the fourteenth resistor and the base of the tenth transistor, and the collector of the tenth transistor serves as the second output end of the logic control circuit;

[0029] The second ends of the eighth resistor and the fourteenth resistor, the emitter of the seventh transistor and the emitter of the tenth transistor are all connected to the ground.

[0030] Further, the bias circuit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, an eighth transistor, a ninth transistor, an eleventh transistor and a twelfth transistor;

[0031] The first end of the ninth resistor is connected to the first output end of the logic control circuit, the collector and base of the eighth transistor, the base of the ninth transistor and the first end of the twelfth resistor, and serves as the first input end of the bias circuit. The collector of the ninth transistor is connected to the first end of the tenth resistor and the first end of the eleventh resistor. The second end of the eleventh resistor serves as the first output end of the bias network and outputs the third bias signal Vs1. The second end of the twelfth resistor serves as the second output end of the bias network and outputs the first bias signal Vb1.

[0032] The first end of the fifteenth resistor is connected to the second output end of the logic control circuit, the collector and base of the eleventh transistor, the base of the twelfth transistor and the first end of the eighteenth resistor, and serves as the second input end of the bias circuit. The collector of the twelfth transistor is connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor. The second end of the seventeenth resistor serves as the third output end of the bias network to output the fourth bias signal Vs2. The second end of the eighteenth resistor serves as the fourth output end of the bias network to output the second bias signal Vb2.

[0033] The second end of the ninth resistor and the second end of the fifteenth resistor are both connected to the reference voltage Vref, the second end of the tenth resistor and the second end of the sixteenth resistor are both connected to the power supply; the emitter of the ninth transistor and the emitter of the twelfth transistor are both grounded.

[0034] Furthermore, the process of making the RF power amplifier operate in different power states based on the different level modes of the four bias signals and the different states of the four amplifiers is specifically as follows:

[0035] The first bias signal Vb1 and the second bias signal Vb2 are both at a high level, the third bias signal Vs1 and the fourth bias signal Vs2 are both at a low level, the first amplifier, the second amplifier, the third amplifier and the fourth amplifier are all in an amplifying state, and the RF power amplifier operates in a high power state working mode;

[0036] The first bias signal Vb1 and the fourth bias signal Vs2 are both at a high level, the second bias signal Vb2 and the third bias signal Vs1 are both at a low level, the first amplifier, the second amplifier and the third amplifier are all in an amplifying state, the fourth amplifier is in a closed state, and the RF power amplifier operates in a medium power state working mode;

[0037] The third bias signal Vs1 and the fourth bias signal Vs2 are both at a high level, the first bias signal Vb1 and the second bias signal Vb2 are both at a low level, the first amplifier and the third amplifier are both in an amplifying state, the second amplifier and the fourth amplifier are both in a closed state, and the RF power amplifier operates in a low-power state operating mode.

[0038] The present invention also provides a communication device, comprising any one of the above described radio frequency power amplifiers.

[0039] The technical solution provided by the present invention creatively proposes a radio frequency power amplifier based on a multi-state working mode. The output matching network and the switch are combined into an adaptive output matching network, and the network cooperates with the working state of the final amplifier. Under the control of the bias network, the working efficiency and performance of the wireless transceiver system are improved.

[0040] Compared with the traditional RF front-end circuit, its beneficial effects are as follows:

[0041] The present invention realizes a variety of amplifier working states through the combined effects of the final amplifier, the bias network and the adaptive output matching network;

[0042] Under different operating conditions, the RF power amplifier can maintain a high level of operating efficiency in a wide back-off range of output power. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0044] Figure 1 A schematic diagram of a radio frequency power amplifier based on a multi-state working mode proposed by the present invention;

[0045] Figure 2 A schematic diagram of a radio frequency link provided by an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a bias network provided in one embodiment of the present invention;

[0047] Figure 4 Schematic diagram of the efficiency of a traditional RF power amplifier in the back-off region;

[0048] Figure 5 It is a schematic diagram of the efficiency of the RF power amplifier in the back-off zone of the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0050] like Figure 1 As shown, a multi-state RF power amplifier of the present invention is shown; it includes a RF chain: a first amplifier P1, a second amplifier P2, a third amplifier P3, a fourth amplifier P4, an input distribution matching network, a first inter-stage matching network 1, a second inter-stage matching network 2 and an output adaptive matching network.

[0051] The RF signal is input from the input port (RFin), passes through the input distribution matching network, and is divided into two. One signal passes through the first amplifier P1, the first inter-stage matching network 1, the second amplifier P2 and the output adaptive network in sequence; the other signal passes through the third amplifier P3, the second inter-stage matching network 3, the fourth amplifier P4 and the output adaptive network in sequence; the two signals are summarized in the output adaptive matching network and then output from the output port.

[0052] The bias network outputs four bias signals to the RF link, so that the RF power amplifier operates in different power states based on the different level modes of the four bias signals and the different states of the four amplifiers. The four bias signals are respectively a first bias signal Vb1, a second bias signal Vb2, a third bias signal Vs1, and a fourth bias signal Vs2.

[0053] like Figure 2 As shown, the input distribution matching network includes a first transformer T1, a first capacitor C1, a first resistor R1, a seventh capacitor C7 and a fourth resistor R4.

[0054] A first end of the first transformer T1 is connected to the input port (RFin); a second end of the first transformer T1 is connected to ground; a third end of the first transformer T1 is connected to a first end of the first capacitor C1; a fourth end of the first transformer T1 is connected to ground; and a fifth end of the first transformer T1 is connected to a first end of the seventh capacitor C7.

[0055] The second end of the first capacitor C1 is connected to the first end of the first resistor R1 and serves as the first output end of the input distribution matching network; the second end of the first resistor R1 is connected to the power supply VCC; the second end of the seventh capacitor C7 is connected to the first end of the fourth resistor R4 and serves as the second output end of the input distribution matching network; the second end of the fourth resistor R4 is connected to the power supply VCC.

[0056] In this embodiment, the first amplifier P1 , the second amplifier P2 , the third amplifier P3 , and the fourth amplifier P4 include a first transistor Q1 , a second transistor Q2 , a fourth transistor Q4 , and a fifth transistor Q5 , respectively.

[0057] like Figure 2 As shown, the base of the first transistor Q1 serves as the input terminal of the first amplifier P1 , the collector serves as the output terminal of the first amplifier P1 , and the emitter is connected to the ground.

[0058] The base of the second transistor Q2 serves as the input terminal of the second amplifier P2 , the collector serves as the output terminal of the second amplifier P2 , and the emitter is connected to the ground.

[0059] The third amplifier P3 includes a fourth transistor Q4 , a base of the fourth transistor Q4 serving as an input terminal of the third amplifier P3 , a collector of the fourth transistor Q4 serving as an output terminal of the third amplifier P3 , and an emitter of the fourth transistor Q4 connected to the ground.

[0060] The fourth amplifier P4 includes a fifth transistor Q5 , a base of the fifth transistor Q5 serving as an input terminal of the fourth amplifier P4 , a collector of the fifth transistor Q5 serving as an output terminal of the fourth amplifier P4 , and an emitter of the fifth transistor Q5 being connected to the ground.

[0061] In this embodiment, the first inter-stage matching network 1 includes a first inductor L1 , a second capacitor C2 , a third capacitor C3 , and a second resistor R2 .

[0062] like Figure 2As shown, the first end of the first inductor L1 is connected to the first end of the second capacitor C2 and serves as the first input end of the first inter-stage matching network 1; the second end of the first inductor L1 is connected to the power supply. The second end of the second capacitor C2 is connected to the first end of the third capacitor C3 and serves as the second output end of the first inter-stage matching network 1; the second end of the third capacitor C3 is connected to the first end of the second resistor R2 and serves as the first output end of the first inter-stage matching network 1; the second end of the second resistor R2 is connected to the bias network and serves as the second input end of the first inter-stage matching network based on the first bias signal Vb1 input.

[0063] In this embodiment, the second inter-stage matching network 2 includes a fifth inductor L5 , an eighth capacitor C8 , a ninth capacitor C9 , and a fifth resistor R5 .

[0064] like Figure 2 As shown, the first end of the fifth inductor L5 is connected to the first end of the eighth capacitor C8 and serves as the first input end of the second inter-stage matching network 2; the first end of the fifth inductor L5 is connected to the power supply. The second end of the eighth capacitor C8 is connected to the first end of the ninth capacitor C9 and serves as the second output end of the second inter-stage matching network 2; the second end of the ninth capacitor C9 is connected to the first end of the fifth resistor R5 and serves as the first output end of the second inter-stage matching network 2; the second end of the fifth resistor R5 is connected to the bias network and serves as the second input end of the second inter-stage matching network based on the second bias signal Vb2 input.

[0065] In this embodiment, the output adaptive matching network includes a second inductor L2, a third inductor L3, a fourth inductor L4, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8, a second transformer T2, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a third resistor R3, a sixth resistor R6, a third transistor Q3 and a sixth transistor Q6.

[0066] like Figure 2As shown, the first end of the second inductor L2 is connected to the first end of the third inductor L3 and serves as the first input end of the output adaptive matching network; the second end of the second inductor L2 is connected to the power supply; the second end of the third inductor L3 is connected to the first end of the fourth capacitor C4 and the first end of the fifth capacitor C5; the second end of the fourth capacitor C4 is connected to the ground; the fifth capacitor C5 is connected to the emitter of the third transistor Q3 and the third end of the second transformer T2; the collector of the third transistor Q3 is connected to the first end of the sixth capacitor C6 and the first end of the fourth inductor L4; the base of the third transistor Q3 is connected to the first end of the third resistor R3; the second end of the sixth capacitor C6 is connected to the ground; the second end of the third resistor R3 is connected to the bias network and serves as the third input end of the third bias signal Vs1 in the output adaptive matching network; the second end of the fourth inductor L4 serves as the second input end of the output adaptive matching network.

[0067] The first end of the sixth inductor L6 is connected to the first end of the seventh inductor L7 and serves as the fourth input end of the output adaptive matching network; the second end of the sixth inductor L6 is connected to the power supply; the second end of the seventh inductor L7 is connected to the first end of the tenth capacitor C10 and the first end of the eleventh capacitor C11; the second end of the tenth capacitor C10 is connected to the ground; the eleventh capacitor C11 is connected to the emitter of the sixth transistor Q6 and the fifth end of the second transformer T2; the collector of the sixth transistor Q6 is connected to the first end of the twelfth capacitor C12 and the first end of the eighth inductor L8; the base of the sixth transistor Q6 is connected to the first end of the sixth resistor R6; the second end of the twelfth capacitor C12 is connected to the ground; the second end of the sixth resistor R6 is connected to the bias network and serves as the sixth input end of the fourth bias signal Vs2 in the output adaptive matching network; the second end of the eighth inductor L8 serves as the fifth input end of the output adaptive matching network; the first end of the second transformer T2 is connected to the output port (RFout); the second end and the fourth end of the second transformer T2 are both connected to the ground.

[0068] In this embodiment, the bias network includes a logic control circuit and a bias circuit. After the control signal Vtrl is input into the logic control circuit, it is input into the bias circuit, and four bias signals are output through the bias circuit, namely, a first bias signal Vb1, a second bias signal Vb2, a third bias signal Vs1, and a fourth bias signal Vs2.

[0069] In this embodiment, the logic control circuit includes a seventh resistor R7, an eighth resistor R8, a thirteenth resistor R13, a fourteenth resistor R14, a seventh transistor Q7 and a tenth transistor Q10.

[0070] like Figure 3As shown, the first end of the seventh resistor R7 is connected to the first end of the thirteenth resistor R13 and serves as the input end of the control signal (Vtrl); the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the base of the seventh transistor Q7; the second end of the eighth resistor R8 is connected to the ground; the emitter of the seventh transistor Q7 is connected to the ground; the collector of the seventh transistor Q7 serves as the first output end of the logic control circuit. The second end of the thirteenth resistor R13 is connected to the first end of the fourteenth resistor R14 and the base of the tenth transistor Q10; the second end of the fourteenth resistor R14 is connected to the ground; the emitter of the tenth transistor Q10 is connected to the ground; the collector of the tenth transistor Q10 serves as the second output end of the logic control circuit.

[0071] In this embodiment, the bias circuit includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, an eighth transistor Q8, a ninth transistor Q9, an eleventh transistor Q11 and a twelfth transistor Q12.

[0072] like Figure 3 As shown, the first end of the ninth resistor R9 is connected to the collector and base of the eighth transistor Q8, the base of the ninth transistor Q9 and the first end of the twelfth resistor R12, and serves as the first input end of the bias circuit, and is also connected to the collector of the seventh transistor Q7; the second end of the ninth resistor R9 is connected to the reference voltage (Vref); the emitter of the ninth transistor Q9 is grounded, and the collector is connected to the first end of the tenth resistor R10 and the first end of the eleventh resistor R11; the second end of the tenth resistor R10 is connected to the power supply (VCC); the second end of the eleventh resistor R11 serves as the first output end of the bias network, and outputs the third bias signal Vs1; the second end of the twelfth resistor R12 serves as the second output end of the bias network, and outputs the first bias signal Vb1.

[0073] The first end of the fifteenth resistor R15 is connected to the collector and base of the eleventh transistor Q11, the base of the twelfth transistor Q12 and the first end of the eighteenth resistor R18, and serves as the second input end of the bias circuit, and is also connected to the collector of the tenth transistor Q10; the second end of the fifteenth resistor R15 is connected to the reference voltage (Vref); the emitter of the twelfth transistor Q12 is grounded, and the collector is connected to the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17; the second end of the sixteenth resistor R16 is connected to the power supply (VCC); the second end of the seventeenth resistor serves as the third output end of the bias network, outputting the fourth bias signal Vs2, and the second end of the eighteenth resistor serves as the fourth output end of the bias network, outputting the second bias signal Vb2.

[0074] In the specific use process of the RF power amplifier in this example, it is first necessary to determine the back-off value B of the output power, such as the back-off value B1 and the back-off value B2, and then determine different states according to the back-off value.

[0075] When the back-off value B is between (0-B1), the amplifier is in a high-power state: Vtrl<2V, the first bias signal Vb1 and the second bias signal Vb2 are both at a high level, the third bias signal Vs1 and the fourth bias signal Vs2 are both at a low level, the first amplifier P1, the second amplifier P2, the third amplifier P3 and the fourth amplifier P4 are all in an amplification state. At this time, the output power of the amplifier is the highest, and all amplifiers are maintained in a high-efficiency state.

[0076] When the back-off value B is between (B1-B2), the amplifier is in the medium power state: Vtrl=3V, the first bias signal Vb1 and the fourth bias signal Vs2 are both at high level, the second bias signal Vb2 and the third bias signal Vs1 are both at low level, the first amplifier P1, the second amplifier P2 and the third amplifier P3 are all in the amplification state, and the fourth amplifier P4 is in the off state. Since the amplifier P4 is turned off, the output power of the amplifier is in the middle at this time, and the P1, P2 and P3 amplifiers are all kept in the high efficiency state, the DC power consumption is reduced, and the working efficiency of the amplifier will be significantly improved after the switching state.

[0077] When the back-off value B is greater than B2, the amplifier is in a low-power state: Vtrl=5V, the third bias signal Vs1 and the fourth bias signal Vs2 are both at a high level, the first bias signal Vb1 and the second bias signal Vb2 are both at a low level, the first amplifier P1 and the third amplifier P3 are both in an amplifying state, the second amplifier P2 and the fourth amplifier P4 are both in a closed state, at which point the output power of the amplifier is at its lowest. Since the second amplifier P2 and the fourth amplifier P4 are turned off, and both the P1 and P3 amplifiers remain in a high-efficiency state, the DC power consumption is reduced, and the working efficiency of the amplifier is significantly improved after switching the state.

[0078] In this embodiment, the working efficiency of the conventional RF power amplifier and the RF power amplifier of the present invention is compared and analyzed. Figure 4 As shown in Figure 2, the working efficiency of traditional RF power amplifiers will decrease significantly as the back-off value increases. Figure 5 As shown, the radio frequency power amplifier of the present invention can significantly improve the working efficiency of the back-off zone.

[0079] The embodiment of the present invention further provides a communication device, including the radio frequency power amplifier provided by any of the above embodiments. The communication device may also have other modules, such as a baseband chip, an antenna circuit, etc. The above other modules may all adopt existing modules in the prior art, and the embodiments of the present invention will not be described in detail.

[0080] The present invention designs an innovative circuit architecture, improves the working efficiency of the radio frequency power amplifier in the back-off zone, and improves the transmission performance of the communication system. The radio frequency front-end circuit can be applied to various communication modules, communication devices, and communication systems according to actual needs.

[0081] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention, and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, and these all belong to the protection scope of the present invention. Therefore, the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

1. A radio frequency power amplifier based on a multi-state operating mode, characterized in that: The RF power amplifier comprises an input distribution matching network connected via an input port, a first interstage matching network and a second interstage matching network connected to the input distribution matching network via a first amplifier and a third amplifier respectively, and an output adaptive matching network, wherein the first interstage matching network is connected to the output adaptive matching network via a second amplifier, the second interstage matching network is connected to the output adaptive matching network via a fourth amplifier, and the output adaptive matching network is connected to the output port; The RF power amplifier also includes a bias network that outputs four bias signals, wherein two bias signals are connected to the first inter-stage matching network and the second inter-stage matching network respectively, and the other two bias signals are connected to the output adaptive matching network; The bias network includes a logic control circuit and a bias circuit. After a control signal Vtrl is input to the logic control circuit, it is input to the bias circuit, and four bias signals are output through the bias circuit, namely, a first bias signal Vb1, a second bias signal Vb2, a third bias signal Vs1, and a fourth bias signal Vs2; The logic control circuit includes a seventh resistor, an eighth resistor, a thirteenth resistor, a fourteenth resistor, a seventh transistor and a tenth transistor; A first end of the seventh resistor is connected to the first end of the thirteenth resistor and serves as an input end of the control signal Vtrl; a second end of the seventh resistor is connected to the first end of the eighth resistor and the base of the seventh transistor, and a collector of the seventh transistor serves as a first output end of the logic control circuit; The second end of the thirteenth resistor is connected to the first end of the fourteenth resistor and the base of the tenth transistor, and the collector of the tenth transistor serves as the second output end of the logic control circuit; The second ends of the eighth resistor and the fourteenth resistor, the emitter of the seventh transistor and the emitter of the tenth transistor are all connected to the ground; The bias circuit includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, an eighth transistor, a ninth transistor, an eleventh transistor and a twelfth transistor; The first end of the ninth resistor is connected to the first output end of the logic control circuit, the collector and base of the eighth transistor, the base of the ninth transistor and the first end of the twelfth resistor, and serves as the first input end of the bias circuit. The collector of the ninth transistor is connected to the first end of the tenth resistor and the first end of the eleventh resistor. The second end of the eleventh resistor serves as the first output end of the bias network and outputs the third bias signal Vs1. The second end of the twelfth resistor serves as the second output end of the bias network and outputs the first bias signal Vb1. The first end of the fifteenth resistor is connected to the second output end of the logic control circuit, the collector and base of the eleventh transistor, the base of the twelfth transistor and the first end of the eighteenth resistor, and serves as the second input end of the bias circuit. The collector of the twelfth transistor is connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor. The second end of the seventeenth resistor serves as the third output end of the bias network to output the fourth bias signal Vs2. The second end of the eighteenth resistor serves as the fourth output end of the bias network to output the second bias signal Vb2. The second end of the ninth resistor and the second end of the fifteenth resistor are both connected to the reference voltage Vref, the second end of the tenth resistor and the second end of the sixteenth resistor are both connected to the power supply; the emitter of the ninth transistor and the emitter of the twelfth transistor are both grounded; Wherein, based on different level modes of four bias signals and different states of four amplifiers, the radio frequency power amplifier operates in different power states.

2. The radio frequency power amplifier according to claim 1, characterized in that: The input distribution matching network includes a first transformer, a first capacitor, a first resistor, a seventh capacitor and a fourth resistor; The third terminal and the fifth terminal of the first transformer are connected to the first terminal of the first capacitor and the first terminal of the seventh capacitor respectively, and the second terminal of the first capacitor and the second terminal of the seventh capacitor are connected to the base of the first amplifier and the third amplifier via the first terminal of the first resistor and the first terminal of the fourth resistor respectively; The second terminal and the fourth terminal of the first transformer are grounded, and the second terminal of the first resistor and the second terminal of the fourth resistor are both connected to a power source.

3. The radio frequency power amplifier according to claim 1, characterized in that: The first inter-stage matching network comprises a first inductor, a second capacitor, a third capacitor and a second resistor; The first end of the first inductor and the first end of the second capacitor are connected to the collector of the first amplifier and serve as the first input end of the first inter-stage matching network, the second end of the second capacitor is connected to the first end of the third capacitor and serves as the second output end of the first inter-stage matching network, and the second end of the third capacitor is connected to the base of the second amplifier via the first end of the second resistor and serves as the first output end of the first inter-stage matching network; The second end of the second resistor is connected to the bias network and serves as the second input end of the first inter-stage matching network based on the first bias signal Vb1 input. The second end of the first inductor is connected to the power supply.

4. The radio frequency power amplifier according to claim 3, characterized in that: The second inter-stage matching network includes a fifth inductor, an eighth capacitor, a ninth capacitor and a fifth resistor; The first end of the fifth inductor and the first end of the eighth capacitor are connected to the collector of the third amplifier and serve as the first input end of the second inter-stage matching network. The second end of the eighth capacitor is connected to the first end of the ninth capacitor and serves as the second output end of the second inter-stage matching network. The second end of the ninth capacitor is connected to the base of the fourth amplifier via the first end of the fifth resistor and serves as the first output end of the second inter-stage matching network. The second end of the fifth resistor is connected to the bias network and serves as the second input end of the second inter-stage matching network based on the second bias signal Vb2 input. The second end of the fifth inductor is connected to the power supply.

5. The radio frequency power amplifier according to claim 4, characterized in that: The output adaptive matching network includes a second inductor, a third inductor, a fourth inductor, a sixth inductor, a seventh inductor, an eighth inductor, a second transformer, a fourth capacitor, a fifth capacitor, a sixth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a third resistor, a sixth resistor, a third transistor and a sixth transistor; The first end of the second inductor is connected to the collector of the second amplifier via the first end of the third inductor and serves as the first input end of the output adaptive matching network; the second end of the third inductor is connected to the first end of the fourth capacitor and the first end of the fifth capacitor; the second end of the fifth capacitor is connected to the emitter of the third transistor and the third end of the second transformer; the collector of the third transistor is connected to the first end of the sixth capacitor and the first end of the fourth inductor; The first end of the sixth inductor is connected to the collector of the fourth amplifier via the first end of the seventh inductor and serves as the fourth input end of the output adaptive matching network; the second end of the seventh inductor is connected to the first end of the tenth capacitor and the first end of the eleventh capacitor; the second end of the eleventh capacitor is connected to the emitter of the sixth transistor and the fifth end of the second transformer; the collector of the sixth transistor is connected to the first end of the twelfth capacitor and the first end of the eighth inductor; The base of the third transistor and the base of the sixth transistor are connected to the first ends of the third resistor and the sixth resistor respectively; the second end of the third resistor is connected to the bias network and serves as the third input end for the third bias signal Vs1 in the output adaptive matching network, and the second end of the sixth resistor is connected to the bias network and serves as the sixth input end for the fourth bias signal Vs2 in the output adaptive matching network; The second end of the fourth inductor is connected to the second output end of the first inter-stage matching network and serves as the second input end of the output adaptive matching network; The second end of the eighth inductor is connected to the second output end of the second inter-stage matching network and serves as the fifth input end of the output adaptive matching network; The second ends of the second inductor and the sixth inductor are connected to the power supply, the second ends of the fourth capacitor, the sixth capacitor, the tenth capacitor, the twelfth capacitor, and the second end and the fifth end of the second transformer are all connected to ground, and the first end of the second transformer is connected to the output port.

6. The radio frequency power amplifier according to claim 5, characterized in that: The process of making the RF power amplifier work in different power states based on the different level modes of the four bias signals and the different states of the four amplifiers is specifically as follows: The first bias signal Vb1 and the second bias signal Vb2 are both at a high level, the third bias signal Vs1 and the fourth bias signal Vs2 are both at a low level, the first amplifier, the second amplifier, the third amplifier and the fourth amplifier are all in an amplifying state, and the RF power amplifier operates in a high power state working mode; The first bias signal Vb1 and the fourth bias signal Vs2 are both at a high level, the second bias signal Vb2 and the third bias signal Vs1 are both at a low level, the first amplifier, the second amplifier and the third amplifier are all in an amplifying state, the fourth amplifier is in a closed state, and the RF power amplifier operates in a medium power state working mode; The third bias signal Vs1 and the fourth bias signal Vs2 are both at a high level, the first bias signal Vb1 and the second bias signal Vb2 are both at a low level, the first amplifier and the third amplifier are both in an amplifying state, the second amplifier and the fourth amplifier are both in a closed state, and the RF power amplifier operates in a low-power state operating mode.

7. A communication device, characterized in that: Comprising a radio frequency power amplifier as described in any one of claims 1-6.

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