Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor device structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: providing a semiconductor substrate, the semiconductor substrate comprising an active region; forming a gate structure on the active region; performing a nitridation treatment on a surface of the active region which is not covered by the gate structure to form a nitrided medium layer, and then preparing a lightly doped drain region in the active region under the nitrided medium layer; forming a side wall structure on a side wall of the gate structure; and preparing a source / drain region in the active region which is not covered by the gate structure and the side wall structure. The semiconductor structure preparation method can effectively improve the damage of the transistor in the preparation process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device. Typically, a DRAM wafer includes an array region and a peripheral region, with the peripheral region housing circuitry including transistors. The transistors in the peripheral region are susceptible to damage during fabrication, resulting in poor electrical stability of the device. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for fabricating semiconductor structures to address the problems mentioned in the background art, so as to improve the damage to transistors during the fabrication process and enhance the electrical stability of the devices.

[0004] According to some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0005] A semiconductor substrate is provided, the semiconductor substrate including an active region;

[0006] A gate structure is formed on the active region;

[0007] The surface of the active region not covered by the gate structure is nitrided to form a nitrided dielectric layer, and then a lightly doped drain region is prepared in the active region under the nitrided dielectric layer.

[0008] A sidewall structure is formed on the sidewall of the gate structure;

[0009] Source and drain regions are prepared in the active region not covered by the gate structure and the sidewall structure.

[0010] In some embodiments of this disclosure, the surface of the active region not covered by the gate structure has an oxide dielectric layer before the nitriding treatment is performed;

[0011] During the nitriding process, the oxide medium layer is transformed into the nitrided medium layer.

[0012] In some embodiments of this disclosure, the nitriding process includes: transforming the oxidized medium layer into the nitrided medium layer using a reactive gas via remote plasma nitriding, wherein the reactive gas includes a nitrogen source gas and a reducing gas.

[0013] In some embodiments of this disclosure, the flow rate ratio of the nitrogen source gas to the reducing gas in the reaction gas is 1:0.5 to 1:3.

[0014] In some embodiments of this disclosure, the reaction temperature is controlled to be 30°C to 60°C during the nitriding process.

[0015] In some embodiments of this disclosure, the reaction time is controlled to be 30s to 180s during the nitriding process.

[0016] In some embodiments of this disclosure, during the nitriding process, the thickness of the nitrided dielectric layer is controlled to be 5 nm to 30 nm.

[0017] In some embodiments of this disclosure, forming a gate structure on the active region includes:

[0018] A gate material layer is formed on the semiconductor substrate, and the gate material layer is etched to form the gate structure.

[0019] In some embodiments of this disclosure, after forming the gate structure and before performing the nitriding treatment, the method further includes:

[0020] A first protective layer is formed, which covers the surface of the gate structure and the surface of the active region not covered by the gate structure;

[0021] A second protective layer is formed, which covers the surface of the first protective layer;

[0022] The second protective layer and the first protective layer covering the surface of the active region are etched to expose the active region not covered by the gate structure; and,

[0023] Remove the second protective layer on the sidewall of the gate structure and at least retain the first protective layer covering the sidewall of the gate structure.

[0024] In some embodiments of this disclosure, the material of the first protective layer is different from the material of the oxide dielectric layer, and the material of the first protective layer includes nitrides; and / or,

[0025] The material of the second protective layer is different from that of the first protective layer; the material of the second protective layer includes oxides.

[0026] In some embodiments of this disclosure, forming a sidewall structure on the sidewall of the gate structure includes:

[0027] A sidewall material layer is formed, which covers the surfaces of the first protective layer and the nitriding medium layer;

[0028] The sidewall material layer located on the nitride dielectric layer is etched using the nitride dielectric layer as an etch stop layer, and portions of the sidewall material layer on both sides of the gate structure are retained as the sidewall structure.

[0029] In some embodiments of this disclosure, after preparing the sidewall structure, the method further includes: preparing a third protective layer covering the sidewall structure.

[0030] In some embodiments of this disclosure, after preparing the source / drain regions, a step of preparing source / drain electrode contacts on the source / drain regions is further included.

[0031] In some embodiments of this disclosure, the steps for fabricating the source-drain contacts include:

[0032] An interlayer dielectric layer is formed on the semiconductor substrate, and a connection via is formed in the interlayer dielectric layer to expose the bottom of the source / drain region;

[0033] The connection hole is filled with conductive material that is electrically connected to the source / drain region to form the source / drain electrode contact.

[0034] Furthermore, according to some embodiments of this disclosure, a semiconductor structure is also provided, comprising:

[0035] An active region, wherein a lightly doped drain region and a source / drain region are provided;

[0036] A gate structure, wherein the gate structure is disposed on the active region;

[0037] A sidewall structure, wherein the sidewall structure is disposed on the sidewall of the gate structure;

[0038] A nitrided dielectric layer is disposed between the sidewall structure and the active region.

[0039] In traditional techniques, the active region surface is typically covered with an oxide dielectric layer during sidewall fabrication. However, this oxide dielectric layer cannot effectively prevent the deposited material from reacting with the active region, leading to oxidation damage in the active region. Furthermore, the etching progress during sidewall fabrication is difficult to control precisely, easily resulting in over-etching and causing over-etching damage to the active region.

[0040] In the semiconductor structure fabrication method provided in this disclosure, a step of nitriding the surface of the active region to form a nitrided dielectric layer is introduced between the formation of the gate structure and the formation of the sidewall structure. Compared with the oxide dielectric layer used in conventional techniques, the nitrided dielectric layer can protect the active region from oxidation damage during the fabrication of the sidewall structure. Furthermore, the etching rate of the nitrided dielectric layer is easier to control, thus better protecting the active region and improving over-etching damage. Therefore, this semiconductor structure fabrication method can effectively improve the damage suffered by the transistor during the fabrication process. Attached Figure Description

[0041] Figure 1 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor structure according to the present disclosure.

[0042] Figure 2 This is a schematic diagram of a cross-sectional structure of a semiconductor substrate provided in this disclosure;

[0043] Figure 3 In order to be in Figure 2 A schematic diagram of a gate structure fabricated based on the structure shown.

[0044] Figure 4 In order to be in Figure 3 A schematic diagram of the structure for fabricating the first and second protective layers based on the structure shown;

[0045] Figure 5 In order to be in Figure 4 A schematic diagram of the structure of etching the second protective layer and the first protective layer on the active region based on the structure shown;

[0046] Figure 6 In order to be in Figure 5 A schematic diagram of the structure shown below with the second protective layer removed;

[0047] Figure 7 In order to be in Figure 6 A schematic diagram of a nitrided dielectric layer prepared by nitriding treatment based on the structure shown;

[0048] Figure 8 In order to be in Figure 7 A schematic diagram of a lightly doped drain region fabricated based on the structure shown.

[0049] Figure 9 In order to be in Figure 8 A schematic diagram of the structure for preparing the sidewall material layer based on the structure shown;

[0050] Figure 10 In order to be in Figure 9 A schematic diagram of the sidewall structure fabricated based on the structure shown;

[0051] Figure 11 In order to be in Figure 10 A schematic diagram of the source / drain region fabricated based on the structure shown;

[0052] Figure 12 In order to be in Figure 11 A schematic diagram of the structure for fabricating the third protective layer based on the structure shown;

[0053] Figure 13 In order to be in Figure 12 A schematic diagram of a structure in which a first interlayer dielectric layer, a second interlayer dielectric layer, a first pattern layer, and a second pattern layer are stacked sequentially based on the structure shown.

[0054] Figure 14 In order to be in Figure 13 A schematic diagram of a structure in which a second pattern layer, a first pattern layer, a second interlayer dielectric layer, and a first interlayer dielectric layer are etched based on the structure shown.

[0055] Figure 15 In order to be in Figure 14 A schematic diagram of the structure for fabricating the third and fourth patterned layers based on the structure shown;

[0056] Figure 16 In order to be in Figure 15 A schematic diagram of the structure in which the fourth pattern layer, the third pattern layer, the second interlayer dielectric layer, the third protective layer, and the gate top protective layer are etched based on the structure shown.

[0057] Figure 17 In order to be in Figure 16 A schematic diagram of the structure shown, with the third and fourth pattern layers removed;

[0058] Figure 18 In order to be in Figure 17 A schematic diagram of the fabrication of source-drain contacts and gate leads based on the structure shown;

[0059] The reference numerals and their meanings in the accompanying drawings are as follows:

[0060] 100. Active region; 110. Oxide dielectric layer; 120. Nitride dielectric layer; 130. Source / drain region; 140. Lightly doped drain region; 150. Inversion doped region; 200. Gate structure; 201. First gate conductive layer; 202. Gate barrier layer; 203. Second gate conductive layer; 210. Gate protection layer; 220. First protection layer; 230. Sidewall structure; 231. Sidewall material layer; 240. Third protection layer; 250. First interlayer dielectric layer; 260. Second interlayer dielectric layer; 310. Second protection layer; 320. First patterned layer; 330. Second patterned layer; 340. Third patterned layer; 350. Fourth patterned layer; 410. Source / drain contact; 420. Gate lead. Detailed Implementation

[0061] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0063] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0064] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0066] The embodiments disclosed herein are described with reference to cross-sectional views that serve as schematic representations of preferred embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.

[0067] This is publicly available. Figure 1 A method for fabricating a semiconductor structure according to the above embodiments is shown, with reference to Figure 1 As shown, the method for fabricating this semiconductor structure includes steps S1 to S8, as detailed below.

[0068] Step S1: Provide a semiconductor substrate.

[0069] Figure 2 A schematic cross-sectional view of the semiconductor substrate is shown. (Refer to...) Figure 2 As shown, the semiconductor substrate includes an active region 100 and an oxide dielectric layer 110. The oxide dielectric layer 110 is stacked on the active region 100 and completely covers the surface of the active region 100.

[0070] It is understood that the material of the oxide dielectric layer 110 includes oxides. In some instances of this embodiment, the material of the oxide dielectric layer 110 may be an insulating material.

[0071] In some examples of this embodiment, the material of the active region 100 can be a semiconductor material. For example, the material of the active region 100 can include one or more of silicon, germanium, and silicon-germanium alloys. Furthermore, the material of the active region 100 can also include doping elements.

[0072] In some instances of this embodiment, the material of the oxide dielectric layer 110 may include an oxide of the material of the active region 100. For example, if the material of the active region 100 includes silicon, then the material of the oxide dielectric layer 110 may include silicon oxide. The oxide dielectric layer 110 may be formed by oxidation based on the material of the active region 100, or it may be formed by deposition.

[0073] In some examples of this embodiment, the thickness of the oxide dielectric layer 110 can be from 5 nm to 100 nm. Further, the thickness of the oxide dielectric layer 110 can be appropriately thinner; for example, the thickness of the oxide dielectric layer 110 can be 5 nm, 10 nm, 20 nm, 30 nm, or 50 nm. The thickness of the oxide dielectric layer 110 can also be within any two of these thicknesses.

[0074] Step S2: Form a gate structure on the active region.

[0075] Figure 3 It shows in Figure 2 A schematic diagram of the gate structure 200 fabricated based on the structure shown. (Refer to...) Figure 3 As shown, the gate structure 200 is disposed on the side of the oxide dielectric layer 110 away from the active region 100, and the gate structure 200 is disposed on a portion of the active region 100. For ease of description, in this embodiment, the portion of the active region 100 located under the gate structure 200 is referred to as the gate region of the active region 100.

[0076] Reference Figure 3 As shown, an oxide dielectric layer 110 is provided between the gate structure 200 and the active region 100. This oxide dielectric layer 110 can serve as a gate dielectric for insulating the gate structure 200 and the active region 100.

[0077] In some examples of this embodiment, reference is made to Figure 3 As shown, the gate structure 200 includes a first gate conductive layer 201, a gate barrier layer 202, and a second gate conductive layer 203 stacked sequentially from bottom to top.

[0078] In some examples of this embodiment, the material of the first gate conductive layer 201 may be a conductor and / or semiconductor material with high adhesion to the oxide dielectric layer 110. In this embodiment, the material of the first gate conductive layer 201 may include polysilicon. Further, the polysilicon is doped polysilicon to improve the conductivity of the first gate conductive layer 201.

[0079] In some examples of this embodiment, the material of the second gate conductive layer 203 can be a conductor material with good conductivity, so that the gate structure 200 as a whole has better conductivity. For example, the material of the second gate conductive layer 203 can be a metallic material. Further, the material of the second gate conductive layer 203 can include one or more of gold, silver, copper, aluminum, and tungsten. In this embodiment, the material of the second gate conductive layer 203 is tungsten.

[0080] A gate barrier layer 202 is disposed between the first gate conductive layer 201 and the second gate conductive layer 203 to prevent elements of the second gate conductive layer 203 from diffusing into the first gate conductive layer 201. In some examples of this embodiment, the material of the gate barrier layer 202 may include one or more of titanium and titanium nitride. In this embodiment, the material of the gate barrier layer 202 is titanium nitride.

[0081] Reference Figure 3 As shown, in some instances of this embodiment, a step of fabricating a gate top protective layer 210 is included during or after the step of fabricating the gate structure 200. The gate top protective layer 210 is disposed on the side of the gate structure 200 away from the semiconductor substrate.

[0082] In some examples of this embodiment, the material of the gate top guard layer 210 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the gate top guard layer 210 is silicon nitride.

[0083] The steps of fabricating the gate structure 200 and the gate top protection layer 210 may include: sequentially fabricating a first conductive material layer, a barrier material layer, a second conductive material layer and a top protection material layer on a semiconductor substrate, and then etching to remove the top protection material layer, the second conductive material layer, the barrier material layer and the first conductive material layer on other regions outside the gate region, so as to form the gate top protection layer 210, the second gate conductive layer 203, the gate barrier layer 202 and the first gate conductive layer 201, respectively.

[0084] Step S3: Prepare the first protective layer covering the gate structure.

[0085] The first protective layer 220 is used to protect the gate structure 200.

[0086] In some examples of this embodiment, after forming the gate structure 200, the method further includes: forming a first protective layer 220, which covers the surface of the gate structure 200 and the surface of the active region 100 not covered by the gate structure 200; forming a second protective layer 310, which covers the surface of the first protective layer 220; etching the second protective layer 310 and the first protective layer 220 covering the surface of the active region 100 to expose the active region 100 not covered by the gate structure 200; and removing the second protective layer 310 on the sidewall of the gate structure 200 while retaining at least the first protective layer 220 covering the sidewall of the gate structure 200.

[0087] Figure 4 It shows in Figure 3 A schematic diagram showing the fabrication of a first protective layer 220 and a second protective layer 310 based on the structure shown. (Refer to...) Figure 4 As shown, the first protective layer 220 covers the gate structure 200 and the oxide dielectric layer 110 that is not shielded by the gate structure 200. In actual fabrication, the first protective layer 220 can be directly deposited on the semiconductor substrate and the surface of the gate structure 200. The second protective layer 310 is fabricated on the first protective layer 220. In actual fabrication, the second protective layer 310 can be deposited on the surface of the first protective layer 220.

[0088] Figure 5 It shows in Figure 4 A schematic diagram of the structure in which the second protective layer 310 and the first protective layer 220 are etched on the active region 100 based on the structure shown.

[0089] Reference Figure 5 As shown, in some examples of this embodiment, in the step of etching the second protective layer 310 and the first protective layer 220 on the active region 100, the second protective layer 310 and the first protective layer 220 stacked on the oxide dielectric layer 110 are removed, while a portion of the first protective layer 220 attached to the sidewall of the gate structure 200 is retained.

[0090] It is understandable that after the second protective layer 310 and the first protective layer 220 are removed, the oxide dielectric layer 110 is exposed from the area outside the gate structure.

[0091] In some examples of this embodiment, the second protective layer 310 and the first protective layer 220 can be removed by dry etching. Furthermore, by performing dry etching along a direction perpendicular to the semiconductor substrate, the second protective layer 310 and the first protective layer 220 stacked on the oxide dielectric layer 110 can be removed, while the first protective layer 220 attached to the sidewall of the gate structure 200 is retained.

[0092] Additionally, refer to Figure 5 As shown, during the etching process using this method, the second protective layer 310 and the first protective layer 220 located above the gate structure 200 will also be etched simultaneously, but this does not significantly affect the first protective layer 220 attached to the sidewall of the gate structure 200.

[0093] The first protective layer 220, attached to the sidewall of the gate structure 200, is used to protect the gate structure 200 in subsequent processes. In some embodiments of this example, the material of the first protective layer 220 includes an insulating material. For example, the material of the first protective layer 220 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the first protective layer 220 is silicon nitride.

[0094] In some instances of this embodiment, the material of the second protective layer 310 includes an insulating material. For example, the material of the second protective layer 310 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the second protective layer 310 is silicon oxide.

[0095] In some instances of this embodiment, during the etching of the second protective layer 310, the first protective layer 220 can be used as an etching stop layer to control the etching amount of the second protective layer 310. Therefore, in this embodiment, the material of the first protective layer 220 can be different from the material of the second protective layer 310, so that the second protective layer 310 and the first protective layer 220 have different etching rates.

[0096] In some instances of this embodiment, during the etching of the first protective layer 220, the oxide dielectric layer 110 can be used as an etching stop layer to control the etching amount of the first protective layer 220. Therefore, in this embodiment, the material of the first protective layer 220 can be different from the material of the oxide dielectric layer 110, so that the first protective layer 220 and the oxide dielectric layer 110 have different etching rates.

[0097] Figure 6 It shows in Figure 5 A schematic diagram of the structure shown, with the second protective layer 310 removed. (Refer to...) Figure 6 As shown, part of the second protective layer 310 that was originally attached to the sidewall of the gate structure 200 was removed.

[0098] In some examples of this embodiment, the second protective layer 310 can be removed by cleaning. Cleaning allows the remaining second protective layer 310 on the sidewall to be removed with minimal impact on the first protective layer 220.

[0099] It is understandable that, through methods such as Figures 4-6This method enables the fabrication of a first protective layer 220 on the sidewall of the gate structure 200 to protect the sidewall of the gate structure 200.

[0100] Step S4: Nitride the surface of the active region not covered by the gate structure to form a nitrided dielectric layer.

[0101] The nitrided dielectric layer is used to protect the surface of the active region 100.

[0102] In some examples of this embodiment, reference is made to Figure 6 As shown, before nitriding, the surface of the active region 100 not covered by the gate structure 200 has an oxide dielectric layer 110. During the nitriding process, the oxide dielectric layer 110 can be transformed into a nitrided dielectric layer 120.

[0103] It is understood that in this embodiment, the oxide medium layer 110 is pre-set on the surface of the active region 100 and retained in this step. However, in some other embodiments, the oxide medium layer may also be formed by natural oxidation after the surface of the active region is exposed.

[0104] Figure 7 It shows in Figure 6 A schematic diagram of the nitrided dielectric layer 120 prepared by nitriding treatment based on the structure shown. (Refer to...) Figure 7 As shown, the portion of the oxide dielectric layer 110 on the active region 100 not covered by the gate structure 200 is transformed into a nitride dielectric layer 120. Therefore, the nitride dielectric layer 120 also masks the active region 100 not covered by the gate structure 200. It can be understood that in this step, all oxide dielectric layers 110 not covered by the gate structure 200 can be transformed into nitride dielectric layers 120, while the oxide dielectric layers 110 covered by the gate structure 200 can be retained to serve as the gate dielectric.

[0105] In this embodiment, the nitriding medium layer 120 is transformed from the oxide medium layer 110. This means that the oxygen element in the oxide medium layer 110 is at least partially replaced by nitrogen element to form the nitriding medium layer 120, i.e., the nitriding medium layer 120 can still contain some oxides. In some examples of this embodiment, in the step of reacting the oxide medium layer 110 to form the nitriding medium layer 120, all the oxygen element in the oxide medium layer 110 is replaced by nitrogen element, which means that the nitriding medium layer 120 does not contain oxygen element.

[0106] In some examples of this embodiment, the nitriding process includes: transforming the oxide dielectric layer 110 into a nitrided dielectric layer 120 using a reactive gas via remote plasma nitriding; the reactive gas may include a nitrogen source gas and a reducing gas. (See reference...) Figure 7 As shown, Figure 7The dashed arrows in the diagram indicate the direction of motion of the plasma of the reactive gas. After the oxide dielectric layer 110, which is not shielded by the gate structure 200, comes into contact with the plasma of the reactive gas, a nitriding reaction occurs, and a nitrided dielectric layer 120 is formed.

[0107] The nitrogen source gas can be a raw material capable of reacting with the material of the oxidizing medium layer 110 to form corresponding nitrides. The reducing gas is used to reduce the oxidizing medium layer 110 during the nitriding process to promote the reaction.

[0108] In some examples of this embodiment, the nitrogen source may include nitrogen gas.

[0109] In some examples of this embodiment, the reducing gas may be hydrogen.

[0110] In some examples of this embodiment, during the nitriding process, the flow rate ratio of nitrogen to reducing gas is (1:0.5) to (1:3). Further, in the reaction gas, the flow rate ratio of nitrogen to reducing gas is (1:0.5) to (1:2).

[0111] In some examples of this embodiment, the reaction temperature can be controlled to be 30°C to 60°C during the nitriding process.

[0112] In some examples of this embodiment, the reaction time can be controlled to be 30s to 180s during the nitriding process.

[0113] In some examples of this embodiment, the thickness of the formed nitrided dielectric layer 120 can also be controlled to be 5 nm to 30 nm.

[0114] The nitrided dielectric layer 120 not only prevents damage to the active region 100 caused by oxidation of elements in the active region 100, but also, compared to the active region 100 and the oxide dielectric layer 110, the nitrided dielectric layer 120 is more difficult to etch in subsequent processes. Therefore, it can serve as an etch stop layer in subsequent processes, effectively protecting the underlying active region 100 and further mitigating damage caused by etching of the active region 100.

[0115] Step S5: Prepare a lightly doped drain region in the active region under the nitrided dielectric layer.

[0116] Figure 8 It shows in Figure 7 A schematic diagram of a lightly doped drain region fabricated based on the structure shown.

[0117] Reference Figure 8As shown, the lightly doped drain region 140 is located in the active region 100 not covered by the gate structure 200. The doping type of the lightly doped drain region 140 can be the same as that of the active region 100. The lightly doped drain region 140 is also called a lightly doped drain (LDD). It can be located at the edge of the gate close to the channel, and its doping concentration is lower than that of the subsequently fabricated source and drain regions. Its function is to provide a doping concentration gradient for the source and drain regions.

[0118] Reference Figure 8 As shown, in some instances of this embodiment, after forming the nitride dielectric layer 120, a step of forming an inversion-doped region 150 in the active region under the nitride dielectric layer is further included. The inversion-doped region 150 may be located below the lightly doped drain region 140, and the doping type of the inversion-doped region 150 is opposite to that of the active region 100. The inversion-doped region 150 can serve as a halo in the semiconductor structure. The inversion elements in the inversion-doped region 150 can suppress the diffusion of the depletion layer of the source and drain into the channel to form a charge-sharing effect, prevent source and drain penetration, and reduce leakage current and threshold drift.

[0119] In some examples of this embodiment, the lightly doped drain region 140 may be prepared by ion implantation.

[0120] In some examples of this embodiment, the inversion doped region 150 can also be prepared by ion implantation.

[0121] It can be understood that by controlling the energy of ion implantation, the depth of ion implantation can be controlled so that the lightly doped drain region 140 and the inversion doped region 150 are located at different depths of the active region 100.

[0122] Step S6: A sidewall structure is formed on the sidewall of the gate structure.

[0123] In some examples of this embodiment, the step of forming a sidewall structure on the sidewall of the gate structure includes: forming a sidewall material layer covering the surface of the first protective layer 220 and the nitride dielectric layer 120, etching the sidewall material layer located on the nitride dielectric layer 120 using the nitride dielectric layer 120 as an etch stop layer, and retaining a portion of the sidewall material layer on both sides of the gate structure 200 as a sidewall structure.

[0124] Figure 9 It shows in Figure 8 A schematic diagram of the structure for fabricating the sidewall material layer 231 based on the structure shown. (Refer to...) Figure 9 As shown, the sidewall material layer 231 completely covers the surface of the first protective layer 220 and the nitriding medium layer 120.

[0125] In some examples of this embodiment, the material of the sidewall material layer 231 may include one or more of silicon oxide and silicon oxynitride. In this embodiment, the material of the sidewall material layer 231 is silicon oxide.

[0126] In some examples of this embodiment, the sidewall material layer 231 may be prepared by chemical vapor deposition.

[0127] Figure 10 It shows in Figure 9 A schematic diagram of the sidewall structure 230 fabricated based on the structure shown. (Refer to...) Figure 10 As shown, in this embodiment, the sidewall structure 230 can cover the lightly doped drain region 140. In the step of fabricating the sidewall structure 230, the sidewall material layer 231 located on the nitride dielectric layer 120 is etched using the nitride dielectric layer 120 as an etch stop layer, and a portion of the sidewall material layer 231 on both sides of the gate structure 200 is retained as the sidewall structure 230.

[0128] In some examples of this embodiment, when etching the sidewall material layer 231, the entire sidewall material layer 231 can be etched simultaneously. During the etching process, the sidewall material layer 231 located on the lightly doped drain region 140 is relatively thick. When the sidewall material layer 231 on the active region 100 outside the lightly doped drain region 140 is completely removed, most of the sidewall material layer 231 located on the lightly doped drain region 140 can be retained and serve as the sidewall structure 230.

[0129] In some examples of this embodiment, the material of the sidewall material layer 231 may be different from the material of the nitride dielectric layer 120, so that the nitride dielectric layer 120 can serve as an etching stop layer. During the etching process, an etchant with a higher etching rate for the sidewall material layer 231 than for the nitride dielectric layer 120 may be selected. For example, the etchant selectivity ratio for the sidewall material layer 231 and the nitride dielectric layer 120 may be ≥10:1.

[0130] Reference Figure 10 As shown, after a portion of the sidewall material layer 231 is removed, a portion of the nitride dielectric layer 120 is exposed outside the sidewall structure 230. In some examples of this embodiment, after the step of fabricating the sidewall structure 230, a step of removing the exposed nitride dielectric layer 120 from the area outside the sidewall structure 230 is included. The method for removing the nitride dielectric layer 120 may be dry etching.

[0131] In some examples of this embodiment, no additional mask may be required during the step of removing the dielectric nitride layer 120. It is understood that when removing the dielectric nitride layer 120 on the source / drain regions, the sidewall structure 230 and the gate top protection layer 210 may be partially removed, but this does not affect the gate structure 200 and the active region 100 located below, so no additional mask is required.

[0132] In this embodiment, when etching the sidewall material layer 231, an etchant with a relatively slow etching rate on the nitride dielectric layer 120 can be selected. Therefore, using the nitride dielectric layer 120 as the etching stop layer for the sidewall material layer 231 allows for more precise control of the etching progress of the sidewall material layer 231, thereby protecting the bottom active region 100 from etching. When the etching of the sidewall material layer 231 is essentially complete, the nitride dielectric layer 120 on the active region 100 is essentially unetched. Then, the nitride dielectric layer 120 is removed. Because the etching rate difference between the nitride dielectric layer 120 and the active region 100 is significant, and the removal amount when removing the nitride dielectric layer 120 separately is easier to control, the damage to the active region 100 is significantly less in the above steps.

[0133] It is understandable that the nitride dielectric layer 120 here is formed by the reaction of the oxide dielectric layer 110. If the oxide dielectric layer 110 is not reacted into the nitride dielectric layer 120, that is, the active region 100 is still covered by the oxide dielectric layer 110, then during the deposition of the sidewall material layer 231, the oxide dielectric layer 110 cannot effectively prevent the deposition material from reacting with the active region 100, resulting in oxidation damage to the active region 100. Furthermore, the etching progress of the sidewall material layer 231 is also more difficult to control accurately, and over-etching is prone to occur, leading to over-etching damage to the active region 100.

[0134] Step S7: Prepare source / drain regions in the active region not covered by the gate structure and sidewall structure.

[0135] Figure 11 It shows in Figure 10 A schematic diagram of the source / drain region 130 fabricated based on the structure shown. (Refer to...) Figure 11 As shown, the source / drain region 130 is located on the side of the sidewall structure 230 away from the gate structure 200.

[0136] In some examples of this embodiment, the source / drain region 130 can be obtained by doping the active region 100. It is understood that the doping concentration in the source / drain region 130 should be higher than the doping concentration in the lightly doped drain region 140.

[0137] In some examples of this embodiment, the active region 100 may be doped by ion implantation during the step of preparing the source / drain region 130.

[0138] In some examples of this embodiment, after preparing the sidewall structure 230, a third protective layer covering the sidewall structure 230 is also prepared.

[0139] Figure 12 It shows in Figure 11 A schematic diagram of the structure for fabricating the third protective layer 240 based on the structure shown. (Refer to...) Figure 12 As shown, the third protective layer 240 covers the surface of the source / drain region 130, the surface of the sidewall structure 230, and the surface of the gate top protective layer 210.

[0140] It is understandable that after the source / drain region 130 is fabricated, the third protective layer 240 can shield and protect the source / drain region 130 and the sidewall structure 230 to facilitate the fabrication of subsequent structures.

[0141] In some examples of this embodiment, the material of the third protective layer 240 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the third protective layer 240 may include silicon nitride.

[0142] Step S8: Prepare source-drain contacts on the source-drain region.

[0143] In some examples of this embodiment, the step of preparing the source-drain contact includes: forming an interlayer dielectric layer on a semiconductor substrate, forming a connection hole in the interlayer dielectric layer that exposes the source-drain region at its bottom; and filling the connection hole with a conductive material electrically connected to the source-drain region to form a source-drain contact.

[0144] In this embodiment, the interlayer dielectric layer may include a first interlayer dielectric layer and a second interlayer dielectric layer.

[0145] In some examples of this embodiment, the step of preparing the source-drain contact also includes preparing a gate lead on the gate structure 200.

[0146] The process of fabricating source-drain contacts on the source-drain region 130 and fabricating gate leads on the gate structure 200 can be referred to Figures 13-18 .

[0147] Figure 13 It shows in Figure 12 A schematic diagram of a structure in which a first interlayer dielectric layer 250, a second interlayer dielectric layer 260, a first pattern layer 320, and a second pattern layer 330 are stacked sequentially based on the structure shown.

[0148] Reference Figure 13 As shown, a first interlayer dielectric layer 250 is disposed on the source / drain region 130 and the sidewall structure 230. In some examples of this embodiment, the first interlayer dielectric layer 250 has a flat surface to facilitate the fabrication of a flat second interlayer dielectric layer 260 on the first interlayer dielectric layer 250.

[0149] In some examples of this embodiment, the top of the first interlayer dielectric layer 250 is flush with the top of the third protective layer 240.

[0150] In some examples of this embodiment, the material of the first interlayer dielectric layer 250 may include one or more of silicon nitride, silicon oxynitride, and silicon oxide. In this embodiment, the material of the first interlayer dielectric layer 250 is selected from silicon oxide.

[0151] Reference Figure 13 As shown, the second interlayer dielectric layer 260 is disposed on the first interlayer dielectric layer 250 and the third protective layer 240.

[0152] In some examples of this embodiment, the material of the second interlayer dielectric layer 260 may include one or more of silicon nitride, silicon oxynitride, and silicon oxide. In this embodiment, the material of the second interlayer dielectric layer 260 is different from the material of the first interlayer dielectric layer 250; for example, the material of the second interlayer dielectric layer 260 is selected from silicon nitride.

[0153] Reference Figure 13 As shown, the first pattern layer 320 and the second pattern layer 330 are stacked sequentially on the second interlayer dielectric layer 260.

[0154] In some examples of this embodiment, the materials of the first pattern layer 320 and the second pattern layer 330 may be different. For example, the material of the first pattern layer 320 may include a spin-coated carbon hard mask material, and the material of the second pattern layer 330 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0155] Figure 14 It shows in Figure 13 A schematic diagram of a structure in which a second pattern layer 330, a first pattern layer 320, a second interlayer dielectric layer 260, and a first interlayer dielectric layer 250 are etched based on the structure shown.

[0156] Reference Figure 14 As shown, after the second pattern layer 330 is etched, it forms an opening that defines the location of the connection hole. It can be understood that before etching the second pattern layer 330, a photolithographic layer can be prepared on the second pattern layer 330 to define the area to be etched. When etching the second pattern layer 330, the first pattern layer 320 can be used as an etching stop layer.

[0157] Reference Figure 14 As shown, it can be understood that the opening of the second pattern layer 330 is located on the source / drain region 130.

[0158] Reference Figure 14As shown, the first pattern layer 320 is etched based on the second pattern layer 330 to transfer the pattern in the second pattern layer 330 to the first pattern layer 320. Therefore, the first pattern layer 320 has openings that communicate with the second pattern layer 330. When etching the first pattern layer 320, the second interlayer dielectric layer 260 can be used as an etching stop layer.

[0159] Reference Figure 14 As shown, the second interlayer dielectric layer 260 is etched based on the first patterning layer 320 to transfer the pattern in the first patterning layer 320 to the second interlayer dielectric layer 260. Therefore, the second interlayer dielectric layer 260 has openings that communicate with the first patterning layer 320. When etching the second interlayer dielectric layer 260, the first interlayer dielectric layer 250 can be used as an etching stop layer.

[0160] Reference Figure 14 As shown, the first interlayer dielectric layer 250 is etched based on the second interlayer dielectric layer 260 to transfer the pattern of the second interlayer dielectric layer 260 into the first interlayer dielectric layer 250.

[0161] In addition, refer to Figure 14 As shown, when the first interlayer dielectric layer 250 is used, a third protective layer 240 can be used as an etch stop layer. This requires that the material of the third protective layer 240 is different from the material of the first interlayer dielectric layer 250. By using the third protective layer 240 as an etch stop layer, the first interlayer dielectric layer 250 on the source / drain region 130 can be removed to expose the third protective layer 240 on the source / drain region 130.

[0162] Understandable. Figure 13 and Figure 14 The process shown is primarily used to form interconnects in the interlayer dielectric layer, which define the fabrication area for subsequent source-drain contacts.

[0163] Figure 15 It shows in Figure 14 A schematic diagram of the structure for fabricating the third pattern layer 340 and the fourth pattern layer 350 based on the structure shown.

[0164] Reference Figure 15 As shown, the third patterning layer 340 is disposed on the third protective layer 240 and the second interlayer dielectric layer 260. In some examples of this embodiment, the third patterning layer 340 has a flat surface.

[0165] Reference Figure 15 As shown, the fourth pattern layer 350 is stacked on the third pattern layer 340.

[0166] In some examples of this embodiment, the materials of the third patterning layer 340 and the fourth patterning layer 350 may be different. For example, the material of the third patterning layer 340 may include a spin-coated carbon hard mask material, and the material of the fourth patterning layer 350 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. Furthermore, the materials of the third patterning layer 340 and both the second interlayer dielectric layer 260 and the first interlayer dielectric layer 250 may be different.

[0167] In some examples of this embodiment, the material of the third patterned layer 340 can be the same as the material of the first patterned layer 320. In the actual fabrication process, the already fabricated first patterned layer 320 can be retained, and the material of the third patterned layer 340 can be fabricated based on the first patterned layer 320 to form the third patterned material layer 340.

[0168] Figure 16 It shows in Figure 15 A schematic diagram of a structure in which a fourth pattern layer 350, a third pattern material layer 340, a second interlayer dielectric layer 260, a third protective layer 240, and a gate top protective layer 210 are etched based on the structure shown.

[0169] Reference Figure 16 As shown, the fourth pattern layer 350 has openings. It can be understood that before etching the fourth pattern layer 350, a photolithographic layer can be prepared on the fourth pattern layer 350 to define the area to be etched. When etching the fourth pattern layer 350, the third pattern layer 340 can be used as an etching stop layer.

[0170] Reference Figure 16 As shown, it can be understood that the opening in the fourth pattern layer 350 is located on the gate structure 200.

[0171] Reference Figure 16 As shown, the third pattern layer 340 is etched based on the fourth pattern layer 350 to transfer the pattern in the fourth pattern layer 350 to the third pattern layer 340. Therefore, the third pattern layer 340 has openings that communicate with the fourth pattern layer 350. When etching the third pattern layer 340, the second interlayer dielectric layer 260 can be used as an etching stop layer.

[0172] Reference Figure 16 As shown, the second interlayer dielectric layer 260 is further etched based on the third patterning layer 340. The pattern in the third patterning layer 340 is also transferred to the second interlayer dielectric layer 260. Therefore, the second interlayer dielectric layer 260 also has openings that communicate with the third patterning layer 340.

[0173] Reference Figure 16As shown, the third protective layer 240 and the gate top protective layer 210 are etched based on the third patterning layer 340. The pattern in the third patterning layer 340 is also transferred to the third protective layer 240 and the gate top protective layer 210, so the third protective layer 240 and the gate top protective layer 210 also have openings that communicate with the third patterning layer 340.

[0174] In some examples of this embodiment, when etching the gate top protective layer 210, the etching amount can be controlled so as not to etch through the gate top protective layer 210, so as to temporarily protect the second gate conductive layer 203.

[0175] Figure 17 It shows in Figure 16 The diagram shows a structure with the third pattern layer 340 and the fourth pattern layer 350 removed from the structure shown. Further, after removing the third pattern layer 340 and the fourth pattern layer 350, the method includes removing a portion of the remaining gate top protective layer 210 on the second gate conductive layer 203 and removing the remaining third protective layer 240 on the source / drain region 130, to expose the second gate conductive layer 203 and the source / drain region 130, respectively.

[0176] in, Figures 15-17 The process shown is used to form the gate lead hole that exposes the gate structure 200.

[0177] Reference Figure 17 As shown, after removing the third pattern layer 340 and the fourth pattern layer 350, the gate top guard layer 210 on the gate structure 200 is etched to expose the gate structure 200. The third guard layer 240 on the source / drain region 130 is etched to expose the source / drain region 130. A portion of the retained third guard layer 240 can be used to protect the sidewall structure 230.

[0178] In some examples of this embodiment, the material of the third protective layer 240 is the same as that of the gate top protective layer 210. This allows the gate top protective layer 210 and the third protective layer 240 to be etched in the same etching process.

[0179] Figure 18 It shows in Figure 17 A schematic diagram showing the fabrication of source / drain contacts 410 and gate leads 420 based on the structure shown. (Refer to...) Figure 18 As shown, the source-drain contact 410 is electrically connected to the source-drain region 130. Further, the source-drain contact 410 directly contacts the source-drain region 130. The gate lead 420 is electrically connected to the gate structure 200. Further, the gate lead 420 directly contacts the gate structure 200.

[0180] Reference Figure 18As shown, the source-drain contact 410 and the gate lead 420 can be separated by a first interlayer dielectric layer 250 and a second interlayer dielectric layer 260.

[0181] In some examples of this embodiment, the steps of fabricating the source-drain contacts 410 and the gate lead 420 may include: depositing conductive material on the source-drain region 130 and the gate structure 200, and then etching back the conductive material to form the insulatingly spaced source-drain contacts 410 and the gate lead 420, respectively. The conductive material may be a metallic material, such as one or more of copper, aluminum, gold, silver, and tungsten. In this embodiment, the conductive material is tungsten.

[0182] Understandable, through Figures 13-18 The described fabrication method is capable of fabricating the source / drain contacts 410 and the gate lead 420.

[0183] The semiconductor structure provided in this disclosure can be prepared by steps S1 to S8.

[0184] Furthermore, this disclosure also provides a method such as Figure 18 The semiconductor structure shown includes an active region 100, a gate structure 200, a sidewall structure 230, and a dielectric nitride layer 120. The active region 100 contains a lightly doped drain region 140 and a source / drain region 130. The gate structure 200 is disposed on the active region 100, the sidewall structure 230 is disposed on the sidewall of the gate structure 200, and the dielectric nitride layer 120 is disposed between the sidewall structure 230 and the active region 100.

[0185] Compared to traditional semiconductor structures, this semiconductor structure incorporates a nitride dielectric layer 120 during fabrication, which effectively protects the active region 100 and reduces oxidation and over-etching damage to the source / drain regions 130 during the fabrication process, thereby improving the stability of the semiconductor device.

[0186] Furthermore, referring to Figure 18 As shown, the semiconductor structure may further include source / drain contacts 410 and gate leads 420. The source / drain contacts 410 are disposed on and in contact with the source / drain region 130, and the gate leads 420 are disposed on and in contact with the gate structure 200.

[0187] Please note that the above embodiments are for illustrative purposes only and are not intended to limit this disclosure.

[0188] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0189] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method of fabricating a semiconductor structure, characterized by, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including an active region; A gate structure is formed on the active region; A first protective layer is formed, which covers the surface of the gate structure and the surface of the active region not covered by the gate structure; A second protective layer is formed, which covers the surface of the first protective layer; The second protective layer and the first protective layer covering the surface of the active region are etched to expose the active region not covered by the gate structure; Remove the second protective layer on the sidewall of the gate structure and at least retain the first protective layer covering the sidewall of the gate structure; Nitriding is performed on the oxide dielectric layer on the surface of the active region not covered by the gate structure to transform the oxide dielectric layer into a nitrided dielectric layer, and then a lightly doped drain region is prepared in the active region under the nitrided dielectric layer. Forming a sidewall structure on the sidewall of the gate structure includes: forming a sidewall material layer, the sidewall material layer covering the surface of the first protective layer and the nitride dielectric layer; etching the sidewall material layer located on the nitride dielectric layer using the nitride dielectric layer as an etch stop layer, and retaining portions of the sidewall material layer on both sides of the gate structure as the sidewall structure; The nitride dielectric layer not covered by the sidewall structure is removed by separate etching; Source and drain regions are prepared in the active region not covered by the gate structure and the sidewall structure; The material of the first protective layer is different from that of the oxide medium layer, and the material of the first protective layer includes nitrides; the material of the second protective layer is different from that of the first protective layer, and the material of the second protective layer includes oxides.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The nitriding process includes: using a reactive gas to remotely nitrid the oxide medium layer to transform it into the nitrided medium layer via plasma nitriding, wherein the reactive gas includes a nitrogen source gas and a reducing gas.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, In the reaction gas, the flow rate ratio of the nitrogen source gas to the reducing gas is 1:0.5 to 1:3; and / or, During the nitriding process, the reaction temperature is controlled at 30℃~60℃; and / or, During the nitriding process, the reaction time is controlled to be 30s~180s.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, During the nitriding process, the thickness of the nitrided medium layer is controlled to be 5 nm to 30 nm.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, After fabricating the source / drain regions, the method further includes a step of fabricating source / drain contacts on the source / drain regions. The step of fabricating source / drain contacts includes: An interlayer dielectric layer is formed on the semiconductor substrate, and a connection via is formed in the interlayer dielectric layer to expose the bottom of the source / drain region; The connection hole is filled with conductive material that is electrically connected to the source / drain region to form the source / drain electrode contact.

6. A semiconductor structure, prepared by the method for preparing a semiconductor structure as described in any one of claims 1-5, characterized in that, include: A semiconductor substrate, wherein an active region is disposed therein, and a lightly doped drain region and a source-drain region are disposed therein; A gate structure is disposed on the active region, wherein neither the lightly doped drain region nor the source / drain region is covered by the gate structure. A sidewall structure, wherein the sidewall structure is disposed on the sidewall of the gate structure; A nitrided dielectric layer is provided, which is not covered by the gate structure. The nitrided dielectric layer is disposed between the sidewall structure and the active region. The lightly doped drain region is disposed below the nitrided dielectric layer and covered by the nitrided dielectric layer. The source and drain regions are disposed on the side of the nitrided dielectric layer away from the gate structure.

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