3D group-pair structure single storage tube NOR flash memory and operation method thereof

Abstract

The present invention provides a single storage tube NOR flash memory with a 3D group pair structure and an operation method thereof. In the flash memory, a gate layer in a gate stack structure is interspersed between two adjacent isolation layers, and a plurality of openings are provided in the gate stack structure. Two first doped columns of a first conductive type are a group and stand vertically in an opening at intervals; two second doped columns of a second conductive type are a group and are arranged in the same opening, and the two second doped columns in the same group are respectively attached to the two side walls of a first doped column; one of the second doped columns in a group is in contact with a local bit line, and the other is in contact with a local source line; a charge trap structure fills the gap between a first doped column and its corresponding opening side wall. In this way, the storage density of the flash memory can be significantly improved. The operation method provided by the present invention is used to perform data operations on the above-mentioned flash memory.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a single storage tube NOR flash memory with a 3D group pair structure and an operation method thereof. Background Art

[0002] Modern electronic devices usually contain electronic memory configured to store data, such as volatile memory and / or non-volatile memory. Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it has become a memory element widely used in personal computers and electronic devices.

[0003] Flash memory is a type of non-volatile memory. In traditional NOR flash memory arrays, the storage cell with 1T (1 Transistor) structure has the advantage of small area, but the programming power consumption is relatively large; the storage cell with 2T (2 Transistor) and split gate structure has added a selection tube. Although the current of the storage tube is improved, the unit storage area is increased. In addition, with the development of planar non-volatile memory, the production process of semiconductors has made great progress. However, the storage density of planar flash memory arrays can no longer meet market demand, and it is necessary to develop non-volatile memory with higher storage density. Summary of the invention

[0004] One of the purposes of the present invention is to improve the storage density of NOR flash memory and reduce the programming power consumption of NOR flash memory.

[0005] In order to achieve the above-mentioned object, the present invention provides a single-storage-tube NOR flash memory with a 3D pair structure. The single-storage-tube NOR flash memory with a 3D pair structure includes: a gate stack structure, the gate stack structure includes a plurality of first isolation layers and a plurality of gate layers stacked in layers, one of the gate layers is interspersed between two adjacent first isolation layers, and the gate stack structure has a plurality of openings; a plurality of first doped columns, the first doped columns are of a first conductive type, two of the first doped columns form a group and stand upright in one of the openings at intervals; the first doped columns have opposite first and second sidewalls and opposite third and fourth sidewalls; for a group of the first doped columns, the first sidewall of one of the first doped columns faces the sidewall of the opening and the second sidewall faces another of the first doped columns; a plurality of second doped columns, the The second doped column is of a second conductivity type opposite to the first conductivity type; two of the second doped columns form a group and are arranged in the same opening, and the two second doped columns in the same group respectively cover the third side wall and the fourth side wall of one of the first doped columns; a plurality of charge trap structures, one of the charge trap structures fills the gap between one of the first doped columns and the side wall of the opening facing the first side wall of the first doped column; and a plurality of local bit lines and a plurality of local source lines erected in the plurality of the openings, one of the local bit line and one of the local source lines form a group and correspond to a group of the second doped columns; one of the two second doped columns in the same group is in contact with the corresponding local bit line, and the other is in contact with the corresponding local source line.

[0006] Optionally, the plurality of openings are arranged in a plurality of rows in the gate stack structure, and the openings in two adjacent rows are staggered in a vertical direction of the row direction.

[0007] Optionally, the single storage tube NOR flash memory of the 3D pair structure includes multiple storage tubes, the channel region of one of the storage tubes is a portion of the first doped column corresponding to the side wall of one of the gate layers in the opening, the channel of one of the storage tubes is a planar channel, and two storage tubes corresponding to one of the gate layers in one of the openings are two storage tubes in a pair.

[0008] Optionally, the first side wall and the second side wall of the first doped column are both straight planes; and the channel of the storage tube is a straight channel.

[0009] Optionally, the single storage tube NOR flash memory with the 3D pair structure further includes a substrate, and the gate stack structure is formed on the substrate.

[0010] Optionally, a plurality of bit line selection tubes and a plurality of source line selection tubes are formed on the substrate, two of the bit line selection tubes form a group, and two of the source line selection tubes form a group; a plurality of global bit lines and a plurality of global source lines are also formed on the top surface of the substrate, two of the global bit lines form a group, and two of the global source lines form a group; the first ends of the two bit line selection tubes in the same group are connected to the same local bit line and the second ends are respectively connected to the two global bit lines in the same group; the first ends of the two source line selection tubes in the same group are connected to the same local source line and the second ends are respectively connected to the two global source lines in the same group.

[0011] Optionally, multiple word lines are formed on the substrate; a group of the bit line selection tubes includes a first bit line selection tube and a second bit line selection tube, and a group of the source line selection tubes includes a first source line selection tube and a second source line selection tube; for the selection tubes corresponding to a group of the local bit lines and the local source lines, the gate of the first bit line selection tube and the gate of the first source line selection tube are commonly connected to one of the word lines, and the gate of the second bit line selection tube and the gate of the second source line selection tube are commonly connected to another of the word lines.

[0012] Optionally, a plurality of the openings are arranged in rows and columns on the substrate, the local bit lines and the local source lines of the same group in one opening are arranged in a row, two groups of the local bit lines and the local source lines in one opening are arranged in two rows, and the local bit lines and the local source lines in a row of openings are arranged in two rows; for the selection tubes corresponding to the local bit lines and the local source lines in the same row, the gate of the first bit line selection tube and the gate of the first source line selection tube are commonly connected to one of the word lines, and the gate of the second bit line selection tube and the gate of the second source line selection tube are commonly connected to another of the word lines.

[0013] Optionally, a group of the global bit lines includes a first global bit line and a second global bit line, and a group of the global source lines includes a first global source line and a second global source line; in the bit line selection tubes corresponding to the local bit lines in the openings in the same column, the second end of the first bit line selection tube is connected to the first global bit line, and the second end of the second bit line selection tube is connected to the second global bit line; in the source line selection tubes corresponding to the local source lines in the openings in the same column, the second end of the first source line selection tube is connected to the first global source line, and the second end of the second source line selection tube is connected to the second global source line.

[0014] Optionally, the charge trap structure includes a first oxide layer, a nitride layer, and a second oxide layer stacked vertically on the first side wall of the first doped column; the first oxide layer contacts the corresponding first side wall of the first doped column, the second oxide layer contacts the opening side wall, and the nitride layer is located between the first oxide layer and the second oxide layer.

[0015] The present invention also provides an operation method for a single storage tube NOR flash memory with a 3D group pair structure, which is used to perform a read operation on the single storage tube NOR flash memory with the above-mentioned 3D group pair structure, including: the gate layer, local bit line and local source line corresponding to the storage tube to be read are respectively called a selected gate layer, a selected local bit line and a selected local source line; a turn-on positive voltage is applied to the selected gate layer to turn on the storage tube corresponding to the selected gate layer; a turn-off negative voltage is applied to the unselected gate layer to turn off the storage tube corresponding to the unselected gate layer; a first read voltage is applied to the selected local bit line, and a second read voltage is applied to the selected local source line; the unselected local bit line and the unselected local source line are suspended; and a well region negative voltage is applied to all the first doped columns.

[0016] The present invention also provides an operating method for a single storage tube NOR flash memory with a 3D group pair structure, which is used to perform a write operation on the single storage tube NOR flash memory with the above-mentioned 3D group pair structure, including: referring to the gate layer, local bit line and local source line corresponding to the storage tube to be written as a selected gate layer, a selected local bit line and a selected local source line respectively; applying a first positive voltage to the selected gate layer, and applying a first negative voltage to the unselected gate layer; applying a second negative voltage to all the first doped columns; and applying a third negative voltage to both the selected local bit line and the selected local source line, and applying a second positive voltage to both the unselected local bit line and the unselected local source line.

[0017] The present invention also provides an operating method for a single storage tube NOR flash memory with a 3D group pair structure, which is used to perform an erasing operation on the single storage tube NOR flash memory with the above-mentioned 3D group pair structure, including: referring to the gate layer, local bit line and local source line corresponding to the storage tube to be erased as a selected gate layer, a selected local bit line and a selected local source line respectively; applying an erasing negative voltage to the selected gate layer and applying a protective positive voltage to the unselected gate layer; applying a first erasing positive voltage to all the local bit lines and applying a second erasing positive voltage to all the local source lines; and applying a well region positive voltage to all the first doped columns.

[0018] In the single-storage-tube NOR flash memory of the 3D group pair structure provided by the present invention, the gate stack structure includes a plurality of gate layers isolated from each other, the gate stack structure has a plurality of openings, the first doped column, the second doped column and the charge trap structure are all erected in the opening, thereby forming a 3D structure NOR storage array, wherein the channel region of a storage tube is a portion of a first doped column corresponding to the side wall of a gate layer in the opening, two first doped columns are arranged in one opening and each first doped column independently corresponds to two second doped columns and one charge trap structure, so that two columns of storage tubes in a vertical direction are formed in the same opening, two storage tubes in the same group are in the same opening, and the two storage tubes in the same group can be individually controlled by two groups of local source lines and local bit lines, thereby realizing a 1T storage structure, thus significantly improving the storage density of the 3D NOR flash memory, and when the flash memory is writing data, the voltage of the local bit line and the local source line corresponding to one storage tube are equal, so that the programming power consumption of the NOR flash memory can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic plan view of a gate layer of a single-storage-tube NOR flash memory with a 3D pair structure provided by an embodiment of the present invention.

[0020] Figure 2 A cross-sectional view of a gate stack structure of a single storage transistor NOR flash memory with a 3D pair structure provided by an embodiment of the present invention.

[0021] Figure 3 A schematic diagram of the current direction of a storage tube of a single storage tube NOR flash memory with a 3D pair structure provided by the present invention during a read operation.

[0022] Figure 4 A schematic diagram of the electron flow direction of a storage tube of a single storage tube NOR flash memory with a 3D pair structure provided by the present invention during a write operation.

[0023] Figure 5 A schematic diagram of the electron flow direction of a storage tube of a single storage tube NOR flash memory with a 3D pair structure provided by the present invention during an erase operation.

[0024] Figure 6 The circuit diagram of a storage array of a single storage transistor NOR flash memory with a 3D pair structure according to an embodiment of the present invention is shown.

[0025] Figure 7 A cross-sectional schematic diagram of a single storage tube NOR flash memory with a 3D pair structure provided by an embodiment of the present invention.

[0026] Figure 8 A circuit diagram of a selection tube, a global bit line, and a global source line on a substrate provided by an embodiment of the present invention.

[0027] Fig. 9 FIG. 4 is a schematic diagram of the layout of global bit lines, global source lines, word lines and openings on a substrate according to an embodiment of the present invention.

[0028] Fig.10 A schematic plan view of a gate layer of a single-storage-tube NOR flash memory with a 3D pair structure provided by another embodiment of the present invention.

[0029] Fig.11 Schematic diagram of voltage application during a read operation of a single-storage-tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0030] Fig.12 The diagram is a schematic diagram of voltage application conditions of a global bit line, a global source line and a select tube gate when a read operation is performed on a single storage tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0031] Fig.13 Schematic diagram of voltage application during a write operation on a single-storage-tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0032] Fig.14 The diagram is a schematic diagram of voltage application conditions of a global bit line, a global source line and a select tube gate when performing a write operation on a single storage tube NOR flash memory of a 3D pair structure according to an embodiment of the present invention.

[0033] Fig.15 Schematic diagram of voltage application during an erase operation on a single-storage-tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0034] Fig.16 The diagram is a schematic diagram of voltage application conditions of a global bit line, a global source line and a select tube gate when performing an erase operation on a single storage tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following is a further detailed description of the 3D group pair structure single storage tube NOR flash memory and its operation method proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] Figure 1 A schematic plan view of a gate layer of a single storage tube NOR flash memory with a 3D pair structure provided by an embodiment of the present invention. Figure 2 A cross-sectional view of a gate stack structure of a single storage transistor NOR flash memory of a 3D pair structure provided by an embodiment of the present invention. Figure 1 It can be a cross-sectional view of the XY plane, Figure 2 It may be a cross-sectional view of the gate stack structure in the Z direction, where the Z direction is perpendicular to the X direction and the Y direction.

[0037] refer to Figure 1 and Figure 2 As shown, the single-storage-tube NOR flash memory of the 3D pair structure provided in this embodiment includes a gate stack structure, a plurality of first doped columns 201, a plurality of second doped columns 202, a plurality of charge trap structures 205, a plurality of local bit lines 203, and a plurality of local source lines 204. The gate stack structure includes a plurality of first isolation layers 102 and a plurality of gate layers 101 arranged in a stacked manner, one gate layer 101 is interspersed between two adjacent first isolation layers 102, and a plurality of openings 103 are provided in the gate stack structure. The first doped columns 201 are of the first conductivity type, two first doped columns 201 form a group and stand vertically in an opening 103 at intervals; the first doped columns 201 have opposite first sidewalls 201a and second sidewalls 201b and opposite third sidewalls 201c and fourth sidewalls 201d; for a group of first doped columns 201, the first sidewall 201a of a first doped column faces the sidewall of the opening 103 and the second sidewall 201b faces another first doped column 201. The second doped column 202 is of a second conductivity type opposite to the first conductivity type; two second doped columns 202 form a group and are arranged in the same opening 103, and the two second doped columns 202 in the same group respectively cover the third sidewall 201c and the fourth sidewall 201d of a first doped column 201. A charge trap structure 205 fills the gap between a first doped column 201 and the sidewall of the opening to which the first sidewall 201a of the first doped column faces. A plurality of local bit lines 203 and a plurality of local source lines 204 stand in a plurality of openings 103, a local bit line 203 and a local source line 204 form a group and correspond to a group of second doped columns 202; one of the two second doped columns 202 in the same group contacts the corresponding local bit line 203, and the other contacts the corresponding local source line 204.

[0038] Specifically, in the gate stack structure, adjacent gate layers 101 are isolated by a first isolation layer 102. The material of the gate layer 101 includes, but is not limited to, metal or polysilicon. The material of the first isolation layer 102 includes, but is not limited to, silicon oxide (SiO2) or silicon nitride (SiN). The thickness of the gate layer 101 and the first isolation layer 102 can be set as needed.

[0039] refer to Figure 1 As shown, the gate stack structure has a plurality of openings 103, and each opening 103 can penetrate the gate stack structure. Exemplarily, the opening shape of the opening 103 can be rectangular, such as a rectangle, but is not limited thereto. In the present application, the same opening 103 can simultaneously generate two pairs of relatively independently controlled single-tube memory cell transistors.

[0040] The first doped column 201 may be doped polysilicon or other thin film deposition layers. The first doped column 201 is of a first conductivity type. Exemplarily, the first conductivity type is, for example, a P type, and the first doped column 201 is, for example, a P well, but is not limited thereto.

[0041] Exemplary, reference Figure 1 As shown, the first doped column 201 is a rectangular column, and the first doped column 201 has a first side wall 201a and a second side wall 201b opposite to each other, and a third side wall 201c and a fourth side wall 201d opposite to each other. A group of first doped columns 201 is arranged in one opening 103, and for a group of first doped columns 201, the first side wall 201a of one first doped column 201 faces the side wall of the opening 103 and the second side wall 201b faces another first doped column 201.

[0042] The second doped column 202 is a second conductivity type opposite to the first conductivity type. In this embodiment, the second conductivity type is N-type, but is not limited thereto. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type. The material of the second doped column 202 includes but is not limited to polysilicon.

[0043] In this embodiment, two second doped columns 202 form a group and are vertically disposed in the same opening 103. The two second doped columns 202 in the same group respectively cover the third sidewall 201c and the fourth sidewall 201d of a first doped column 201, or in other words, the two second doped columns 202 in the same group are respectively connected to the third sidewall 201c and the fourth sidewall 201d of a first doped column 201. Figure 1 As shown, in this embodiment, two groups of second doped columns 202 are disposed in one opening 103 , and one group of second doped columns 202 is located on both sides of one first doped column 201 .

[0044] refer to Figure 1 As shown, a charge trap structure 205 fills a gap between a first doped column 201 and a sidewall of the opening to which a first sidewall 201 a of the first doped column 201 faces.

[0045] Exemplarily, the storage tube of the single storage tube NOR flash memory of the 3D group pair structure is a charge trap type storage tube. The charge trap structure 205 includes a first side wall 201a of the first doped column 201 in the vertical direction (i.e. Figure 1The first oxide layer, the nitride layer, and the second oxide layer stacked in the Y direction (in the Y direction), that is, the charge trap structure 205 is an ONO layer. The first oxide layer is in contact with the first sidewall 201a of the corresponding first doped column 201, the second oxide layer is in contact with the opening sidewall, and the nitride layer is located between the first oxide layer and the second oxide layer. The first oxide layer and the second oxide layer can be silicon oxide layers, and the nitride layer can be a silicon nitride layer.

[0046] Continue to refer Figure 1 As shown, a plurality of local bit lines 203 and a plurality of local source lines 204 of a single storage tube NOR flash memory of a 3D pair structure stand upright in a plurality of openings 103, and the local bit lines 203 and the local source lines 204 extend along a Z direction perpendicular to the X direction and the Y direction. A local bit line 203 and a local source line 204 form a group and correspond to a group of second doped columns 202; one second doped column 202 of a group of second doped columns 202 contacts the corresponding local bit line 203, and another second doped column 202 contacts the local source line 204.

[0047] In this embodiment, the local bit lines 203 and local source lines 204 in the same group are equivalent and can be switched with each other. Each group of local bit lines 203 and local source lines 204 can be independently controlled, and each first doped column 201 can also be independently controlled.

[0048] Exemplary, reference Figure 1 As shown, the opening shape of the opening 103 can be a rectangle, but is not limited thereto. Each opening 103 has two local bit lines 203 and two local source lines 204, and the two local bit lines 203 and the two local source lines 204 are respectively arranged near the four corners of the rectangle. Figure 1 As shown, the charge trap structure 205 also extends to fill the gap between the local source line 203 and the sidewall of the opening and extends to fill the gap between the local source line 204 and the sidewall of the opening.

[0049] In this embodiment, two first doped columns 201, four second doped columns 202, two local bit lines 203 and two local source lines 204 extending along the Z direction are arranged in one opening 103, one first doped column 201 corresponds to one charge trap structure 205, two second doped columns 202, one local bit line 203 and one local source line 204, and the two second doped columns 202, one local bit line 203 and one local source line 204 corresponding to one first doped column 201 can be arranged in a row in the X direction.

[0050] The opening 103 is also filled with a second isolation layer 206, which isolates the two first doped columns 201 and the second doped columns 202, the local bit line 203 and the local source line 204 corresponding to the two first doped columns 201. The second isolation layer 206 also isolates the sidewalls of the opening and the local bit line 203 and the local source line 204 in the opening. Exemplarily, the material of the second isolation layer 206 includes, but is not limited to, silicon dioxide.

[0051] Exemplarily, the depths of the multiple openings 103 in the gate stack structure are equal, the local bit lines 203 and the local source lines 204 in the openings 103 can be at the same height, and the first doped column 201, the second doped column 202 and the charge trap structure 205 can be at the same height, but are not limited thereto.

[0052] In this embodiment, the single-storage-tube NOR flash memory of the 3D pair structure includes a plurality of storage tubes, the channel region of one storage tube is a portion of a first doped column 201 corresponding to a side wall of a gate layer 101 in the opening 103, and the channel of one storage tube is a planar channel. The first side wall 201a and the second side wall 201b of the first doped column 201 are both straight planes, and the channel of the storage tube is a straight channel.

[0053] Figure 3 This is a schematic diagram of the current direction of the storage tube of the single storage tube NOR flash memory of the 3D group pair structure provided by the present invention during the read operation. Figure 3 As shown, when the flash memory of the present application is read, as Figure 3 As shown, the read current in the storage tube flows from the local bit line 203 to the local source line 204, that is, the direction of the read current is horizontal (ie, X direction) and perpendicular to the elongation direction of the first doped column 201 (ie, Z direction).

[0054] Figure 4 This is a schematic diagram of the electron flow direction of the storage tube of the single storage tube NOR flash memory of the 3D group pair structure provided by the present invention during the write operation. Figure 4 As shown, when the flash memory of the present application is written, Figure 4 As shown, electrons flow from the first doped column 201 into the charge trap structure 205 , that is, the current direction is opposite to the Y direction.

[0055] Figure 5 This is a schematic diagram of the electron flow direction of the storage tube of the single storage tube NOR flash memory of the 3D group pair structure provided by the present invention during the erase operation. Figure 5 As shown, when the flash memory of the present application is erased, Figure 5 As shown, electrons flow out from the charge trap structure 205 to the first doped column 201 , that is, the current direction is in the Y direction.

[0056] Figure 6FIG. 1 is a circuit diagram of a storage array of a single storage transistor NOR flash memory of a 3D pair structure according to an embodiment of the present invention. Figure 6 As shown, one first doped column corresponds to one column of storage tubes, wherein, Figure 6 The column direction corresponds to Figure 2 The Z direction is the depth direction of the opening 103. One column of storage tubes is connected to one bit line (BL) and one source line (SL). Two storage tubes corresponding to one gate layer (Gate Layer) in one opening 103 are two storage tubes in a pair, such as Figure 6 The two storage tubes in the middle dotted frame are two storage tubes in a pair; two rows of storage tubes are formed in one opening 103 .

[0057] Figure 7 A cross-sectional schematic diagram of a single storage tube NOR flash memory with a 3D pair structure provided by an embodiment of the present invention. Figure 7 As shown, the single storage tube NOR flash memory of the 3D pair structure further includes a substrate 100. The substrate 100 can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon on insulator (SOI) or a germanium on insulator (GOI), etc., and certain doping particles can be implanted into the substrate 100 according to design requirements to change electrical parameters.

[0058] A plurality of selection tubes 104 and a metal layer 105 located on the selection tubes 104 may be formed on the substrate 100, and a gate stack structure is formed on the substrate 100. Specifically, the gate stack structure is formed on the metal layer 105, that is, a plurality of gate layers 101 and a plurality of first isolation layers 102 are stacked on the metal layer 105. A plurality of metal layers 105 may be formed on the substrate 100. Figure 7 and Figure 1 As shown, the traces in metal layer 105 are perpendicular to local bit lines 203 and local source lines 204 .

[0059] Exemplary, reference Figure 7 As shown, the gate of the selection tube 104 is formed on the substrate 100 , and the source and drain of the selection tube 104 are formed in the substrate 100 . Figure 8 A circuit diagram of a selection tube, a global bit line, and a global source line on a substrate provided by an embodiment of the present invention. Figure 7 and Figure 8 As shown, a plurality of selection tubes 104 are arranged in an array on the substrate 100 , and the plurality of selection tubes 104 include a plurality of bit line selection tubes connected to the local bit lines 203 and a plurality of source line selection tubes connected to the local source lines 204 .

[0060] refer to Figure 7 and Figure 8As shown, the metal layer 105 may include a plurality of global bit lines (GBL), a plurality of global source lines (GSL) and a plurality of word lines (WL). Specifically, the substrate 100 may have a first metal layer, a second metal layer and a third metal layer, the local bit lines and the local source lines may be connected to the pads of the second metal layer or the third metal layer, the global bit lines and the global source lines may be formed in the first metal layer or the second metal layer, and the first metal layer, the second metal layer and the third metal layer may be interconnected by contact holes (CT).

[0061] refer to Figure 7 and Figure 8 As shown, the gate of a row of selection tubes is connected to a word line, and a column of selection tubes is correspondingly connected to two global bit lines or two global source lines. The column direction of a column of selection tubes refers to Figure 8 In the Y direction, the column direction of the selection tube is perpendicular to the column direction of the storage tube. It should be noted that when operating the single storage tube NOR flash memory with a 3D group pair structure, voltage can be applied to the local bit line and the local source line through the global bit line and the global source line, and the local bit line and the local source line can be connected to the corresponding global bit line and the global source line through the control of the selection tube.

[0062] Specifically, two global bit lines form a group, and a group of global bit lines includes a first global bit line and a second global bit line. Exemplarily, the first global bit line GBL0 and the second global bit line GBL0' form a group, and the first global bit line GBL1 and the second global bit line GBL1' form a group.

[0063] Two global source lines form a group, and a group of global source lines includes a first global source line and a second global source line. Exemplarily, the first global source line GSL0 and the second global source line GSL0' form a group, and the first global source line GSL1 and the second global source line GSL1' form a group.

[0064] Two bit line selection tubes form a group, and two source line selection tubes form a group; the first ends of the two bit line selection tubes in the same group are connected to the same local bit line and the second ends are respectively connected to the two global bit lines in the same group; the first ends of the two source line selection tubes in the same group are connected to the same local source line and the second ends are respectively connected to the two global source lines in the same group.

[0065] Exemplary, reference Figure 8 As shown, a group of bit line selection transistors includes a first bit line selection transistor M1 and a second bit line selection transistor M2 adjacent to each other. Figure 8Taking the group of bit line selection tubes in the upper left corner as an example, the first ends of the first bit line selection tube M1 and the second bit line selection tube M2 are both connected to the local bit line BL00, the second end of the first bit line selection tube M1 is connected to the first global bit line GBL0, and the second end of the second bit line selection tube M2 is connected to the second global bit line GBL0'; a group of source line selection tubes includes the adjacent first source line selection tube N1 and the second source line selection tube N2. Figure 8 Taking a group of source line selection tubes in the upper left corner as an example, the first end of the first source line selection tube N1 and the first end of the second source line selection tube N2 are both connected to the local source line SL00, the second end of the first source line selection tube N1 is connected to the first global source line GSL0, and the second end of the second source line selection tube N2 is connected to the second global source line GSL0'.

[0066] Fig. 9 FIG. 1 is a schematic diagram of the layout of global bit lines, global source lines, word lines and openings on a substrate in one embodiment of the present invention. Fig. 9 As shown, on a plane parallel to the top surface of the substrate 100, multiple openings 103 are arranged in rows and columns on the substrate 100, and local bit lines and local source lines of the same group in one opening 103 are arranged in a row, such as the local bit lines BL00 and the local source lines SL00 of the same group are arranged in a row, two groups of local bit lines and local source lines in one opening 103 are arranged in two rows, and the local bit lines and local source lines in a row of openings 103 are arranged in two rows; the local bit lines in a column of openings are arranged in a column, and the local source lines in a column of openings are arranged in a column, such as the local bit lines BL00, BL10, BLN0 and BLN+10 are arranged in a row, and the local source lines SL00, SL10, SLN0 and SLN+10 are arranged in a row.

[0067] refer to Figure 8 and Fig. 9 As shown, a plurality of word lines are formed on the substrate 100. For the selection tubes corresponding to a group of local bit lines and local source lines, such as the selection tubes corresponding to the local bit lines BL00 and the local source lines SL00 of the same group, the gate of the first bit line selection tube M1 and the gate of the first source line selection tube N1 are commonly connected to a word line WL0, and the gate of the second bit line selection tube M2 and the gate of the second source line selection tube N2 are commonly connected to another word line WL0'. For the selection tubes corresponding to the local bit lines and local source lines of the same row, the gate of the first bit line selection tube M1 and the gate of the first source line selection tube N1 are commonly connected to a word line, and the gate of the second bit line selection tube M2 and the gate of the second source line selection tube N2 are commonly connected to another word line. It should be noted that Figure 6 The circuit diagram of the memory array corresponding to the word lines WL0 and WL1 is exemplarily shown.

[0068] refer to Figure 8 and Fig. 9As shown, the bit line selection tubes corresponding to the local bit lines in the same column of openings 103 correspond to a group of global bit lines. Among the bit line selection tubes corresponding to the local bit lines in the same column of openings 103, the second ends of all the first bit line selection tubes M1 are connected to the first global bit line, and the second ends of all the second bit line selection tubes N2 are connected to the second global bit line, such as the second end of the first bit line selection tube M1 corresponding to the local bit lines in the first column is connected to the first global bit line GBL0, and the second end of the second bit line selection tube M2 corresponding to the local bit lines in the first column is connected to the second global bit line GBL0'; the source line selection tubes corresponding to the local source lines in the same column of openings 103 correspond to a group of global source lines. Among the source line selection tubes corresponding to the local source lines in the same column of openings 103, the second ends of all the first source line selection tubes N1 are connected to the first global source line, and the second ends of all the second source line selection tubes N2 are connected to the second global source line, such as the second end of the first source line selection tube N1 corresponding to the local source lines in the first column is connected to the first global source line GSL0, and the second end of the second source line selection tube N2 corresponding to the local source lines in the first column is connected to the second global source line GSL0'.

[0069] Fig.10 A schematic cross-sectional view of a gate layer of a single storage transistor NOR flash memory with a 3D pair structure provided by another embodiment of the present invention. Fig.10 As shown, a plurality of openings 103 are arranged in a plurality of rows in the gate stack structure, and the row direction is, for example, the X direction. The openings 103 in two adjacent rows are staggered in the vertical direction of the row direction, so that the space for picking up the top or bottom lines of the gate stack structure can be increased. When the openings 103 in two adjacent rows are staggered in the vertical direction of the row direction, a column of openings 103 is not a straight column, but a curved column that is bent along with the stagger, and the local bit line column and the local source line column in a column of openings 103 are also correspondingly curved columns.

[0070] The present invention provides an operation method of the single storage tube NOR flash memory with the 3D group pair structure.

[0071] The present invention provides an operation method of a single-storage-tube NOR flash memory with a 3D group pair structure, which is used for performing a read operation on the single-storage-tube NOR flash memory with the above-mentioned 3D group pair structure. The operation method comprises: referring to the gate layer, local bit line and local source line corresponding to the storage tube to be read as a selected gate layer, a selected local bit line and a selected local source line respectively; applying a positive turn-on voltage to the selected gate layer to turn on the storage tube corresponding to the selected gate layer; applying a negative turn-off voltage to the unselected gate layer to turn off the storage tube corresponding to the unselected gate layer; applying a first read voltage to the selected local bit line and applying a second read voltage to the selected local source line; suspending the unselected local bit line and the unselected local source line; and applying a well region negative voltage to all first doped columns.

[0072] When a read operation is performed on a single storage tube NOR flash memory with a 3D group pair structure, a first read voltage is applied to all global bit lines and a second read voltage is applied to all global source lines; a selection tube turn-on voltage is applied to word lines connected to the gates of two bit line selection tubes corresponding to a selected local bit line, so that the selection tubes corresponding to the selected local bit line and the selected local source line are in an on state; the word line connected to the gates of the two bit line selection tubes connected to the selected local bit line is a selected word line, and the remaining word lines are unselected word lines, and a 0V voltage is applied to the unselected word lines, so that the selection tubes connected to the unselected word lines are all in a closed state.

[0073] Fig.11 Schematic diagram of voltage application during a read operation of a single-storage-tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0074] Exemplary, reference Fig.11 As shown, a turn-on positive voltage Vgread-select is applied to the selected gate layer Gate Layer N, and the storage tube corresponding to the selected gate layer is in the turned-on state; a turn-off negative voltage Vgread-unselect is applied to the unselected gate layers Gate Layer 0, Gate Layer 1 and Gate Layer N+1, so that the storage tubes corresponding to the unselected gate layers are in the turned-off state; the first read voltage Vbread is applied to the selected local bit lines BL10, BL11, ..., BL1N; the second read voltage Vsread is applied to the selected local source lines SL10, SL11, ..., SL1N; the unselected local bit lines BL00, BL01, ..., BL0N and the unselected local source lines SL00, SL01, ..., SL0N are all suspended (float); and the well region negative voltage Vrwell is applied to all the first doped columns.

[0075] Exemplarily, the turn-on positive voltage Vgread-select is greater than or equal to 0V and less than or equal to 3.5V. Exemplarily, the turn-off negative voltage Vgread-unselect is greater than or equal to -3.5V and less than or equal to 0V. Exemplarily, the first read voltage Vbread is greater than or equal to 0V and less than or equal to 2.5V. Exemplarily, the second read voltage Vsread is greater than or equal to 0V and less than or equal to 2.5V. Exemplarily, the well region negative voltage Vrwell is greater than or equal to -3.5V and less than or equal to 0V.

[0076] Fig.12 The diagram is a schematic diagram of voltage application conditions of a global bit line, a global source line and a select tube gate when a read operation is performed on a single storage tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0077] For example, corresponding to Fig.11When performing a read operation, the voltage applied to Fig.12 As shown, a first read voltage Vbread is applied to all global bit lines GBL, and a second read voltage Vsread is applied to all global source lines GSL; the word lines WL1 and WL1' connected to the gates of the two bit line selection tubes corresponding to the selected local bit lines are selected word lines, and the remaining word lines are unselected word lines. The selection tube turn-on voltage Vwron is applied to the selected word lines, so that the selection tubes corresponding to the selected local bit lines and the selected local source lines are turned on, and then the voltage on the global bit lines and the global source lines can flow to the selected local bit lines and the selected local source lines; 0V voltage is applied to the unselected word lines, so that the selection tubes connected to the unselected word lines are all turned off, and then the voltage on the global bit lines and the global source lines will not flow to the selected local bit lines and the selected local source lines. Exemplarily, the selection tube turn-on voltage Vwron is greater than or equal to 2.5V and less than or equal to 5V.

[0078] In this embodiment, a page of memory tubes corresponding to two word lines is taken as a reading unit for reading. In other embodiments, some memory tubes corresponding to the selected word line can be read by changing the voltage of some global bit lines and global source lines.

[0079] The present invention provides an operation method of a single-storage-tube NOR flash memory with a 3D group pair structure, which is used for performing a write operation on the single-storage-tube NOR flash memory with the above-mentioned 3D group pair structure. The operation method comprises: referring to the gate layer, local bit line and local source line corresponding to the storage tube to be written as a selected gate layer, a selected local bit line and a selected local source line respectively; applying a first positive voltage to the selected gate layer, and applying a first negative voltage to the unselected gate layer; applying a second negative voltage to all first doped columns; and applying a third negative voltage to both the selected local bit line and the selected local source line, and applying a second positive voltage to both the unselected local bit line and the unselected local source line.

[0080] When a write operation is performed on a single-storage-tube NOR flash memory with a 3D pair structure, for a group of global bit lines corresponding to the selected local bit line and a group of global source lines corresponding to the selected local source line, the first global bit line and the second global source line are both applied with a third negative voltage, and the second global bit line and the second global source line are both applied with a second positive voltage; for a group of global bit lines corresponding to the unselected local bit line and a group of global source lines corresponding to the unselected local source line, the first global bit line, the first global source line, the second global bit line, and the second global source line are all applied with a second positive voltage; the first source line selection tube M1 connected to the selected local bit line and the first source line selection tube N1 connected to the selected local source line SL10 are connected with the selected local bit line. 1, so that the first bit line selection tube M1 and the first source line selection tube N1 are turned on; a fourth negative voltage is applied to the word line connected to the second bit line selection tube M2 connected to the selected local bit line and the second source line selection tube N2 connected to the selected local source line, so that the second bit line selection tube M2 and the second source line selection tube N2 are turned off; the word lines connected to the gates of the two bit line selection tubes corresponding to the selected local bit line are all called selected word lines, and the remaining word lines are unselected word lines. The fourth negative voltage is applied to the word line connected to the first bit line selection tube M1 among the unselected word lines, and the third positive voltage is applied to the word line connected to the second bit line selection tube M2 among the unselected word lines.

[0081] Fig.13 Schematic diagram of voltage application during a write operation on a single-storage-tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0082] Exemplary, reference Fig.13 As shown, a first positive voltage Vgpro-select is applied to the selected gate layer Gate Layer N, and a first negative voltage Vgpro-unselect is applied to the unselected gate layers Gate Layer 0, Gate Layer 1, Gate Layer N+1, etc.; a second negative voltage Vpro-well is applied to all first doped columns; a third negative voltage Vpro is applied to the selected local bit lines BL10, BL1N and the selected local source lines SL10, SL1N, and a second positive voltage Vinhibit is applied to the unselected local bit lines BL00, BL01, BL11, BL0N, etc. and the unselected local source lines SL00, SL01, SL11, SL0N, etc.

[0083] Fig.14 The diagram is a schematic diagram of voltage application conditions of a global bit line, a global source line and a select tube gate when performing a write operation on a single storage tube NOR flash memory of a 3D pair structure according to an embodiment of the present invention.

[0084] For example, corresponding to Fig.13 When performing a write operation, the voltage applied to Fig.14As shown, the first global bit line GBL0 and the second global bit line GBL0' of the same group are selected from the local bit line BL10, the first global bit line GBLN and the second global bit line GBLN' of the same group are selected from the local bit line BL1N, the first global source line GSL0 and the second global source line GSL0' of the same group are selected from the local source line SL10, the first global source line GSLN and the second global bit line GSLN' of the same group are selected from the local source line SL1N, the third negative voltage Vpro is applied to the first global bit line GBL0, GBLN and the second global source line GBL0', GBLN', and the second global source line GSL0', GSLN', and the second positive voltage Vinhibit is applied to the second global bit line GBL0', GBLN' and the second global source line GSL0', GSLN'; for a group of global bit lines corresponding to an unselected local bit line and a group of global source lines corresponding to an unselected local source line, the first global bit line GBL1, the first global source line GSL1, and the second global bit line GBL0' are connected to the first global bit line GBL0'. 1' and the second global source line GSL1' are both applied with a second positive voltage Vinhibit; a third positive voltage Vwpon is applied to the word line WL1 connected to the first bit line selection tube M1 connected to the selected local bit line and the first source line selection tube N1 connected to the selected local source line SL10, and a fourth negative voltage Vwpoff is applied to the word line WL1' connected to the second bit line selection tube M2 connected to the selected local bit line and the second source line selection tube N2 connected to the selected local source line, so that Vpro flows to the selected local bit line and the selected local source line; the word lines WL1 and WL1' connected to the gates of the two bit line selection tubes corresponding to the selected local bit line are both called selected word lines, and the remaining word lines are unselected word lines. The fourth negative voltage Vwpoff is applied to the word line connected to the first bit line selection tube M1 among the unselected word lines, and the third positive voltage Vwpon is applied to the word line connected to the second bit line selection tube M2 among the unselected word lines, so that Vinhibit flows to the unselected local bit lines and the unselected local source lines.

[0085] Exemplarily, the first positive voltage Vgpro-select is greater than or equal to 3.6V and less than or equal to 5.4V. Exemplarily, the first negative voltage Vgpro-unselect is greater than or equal to -4.5V and less than or equal to -2.5V. Exemplarily, the second negative voltage Vpro-well is greater than or equal to -5.4V and less than or equal to -3.6V; the third negative voltage Vpro is greater than or equal to -5.4V and less than or equal to -3.6V. Exemplarily, the second positive voltage Vinhibit is greater than or equal to 0V and less than or equal to 2.5V. Exemplarily, the third positive voltage Vwpon is greater than or equal to 3.6V and less than or equal to 5.4V. Exemplarily, the fourth negative voltage Vwpoff is greater than or equal to -5.4V and less than or equal to -3.6V.

[0086] It should be noted that for the single storage tube NOR flash memory of the 3D pair structure of the present application, the smallest write unit is a single storage tube. In addition, during the write operation, if Fig.13 As shown, the potentials of the local bit line and the local source line connected to a storage tube are equal, so there is basically no channel current when data is written, which significantly reduces the power consumption of data writing.

[0087] The present invention provides an operation method of a single storage tube NOR flash memory with a 3D group pair structure, which is used for performing an erasing operation on the single storage tube NOR flash memory with the above-mentioned 3D group pair structure. The operation method comprises: referring to the gate layer, local bit line and local source line corresponding to the storage tube to be erased as a selected gate layer, a selected local bit line and a selected local source line respectively; applying an erasing negative voltage to the selected gate layer and applying a protective positive voltage to the unselected gate layer; applying a first erasing positive voltage to all the local bit lines and applying a second erasing positive voltage to all the local source lines; and applying a well region positive voltage to all the first doped columns.

[0088] Fig.15 Schematic diagram of voltage application during an erase operation on a single-storage-tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0089] Exemplary, reference Fig.15 As shown, a negative erase voltage Vgerase-select is applied to the selected gate layer Gate Layer N, and a protective positive voltage Vgerase-unselect is applied to the unselected gate layers Gate Layer 0, Gate Layer 1 and Gate Layer N+1; a first erase positive voltage Vberase is applied to all local bit lines, and a second erase positive voltage Vserase is applied to all local source lines; a well region positive voltage Verase+ is applied to all first doped columns.

[0090] Fig.16 The diagram is a schematic diagram of voltage application conditions of a global bit line, a global source line and a select tube gate when performing an erase operation on a single storage tube NOR flash memory having a 3D pair structure according to an embodiment of the present invention.

[0091] For example, corresponding to Fig.15 When performing an erase operation, refer to the voltage application condition. Fig.16 As shown, when the single storage tube NOR flash memory with a 3D group pair structure is erased, the first erase positive voltage Vberase is applied to all global bit lines GBL, the second erase positive voltage Vserase is applied to all global source lines GSL, and the selection tube turn-on positive voltage Vweon is applied to all word lines.

[0092] Exemplarily, the erase negative voltage Vgerase-select is greater than or equal to -5.4V and less than or equal to -3.6V. Exemplarily, the protection positive voltage Vgerase-unselect is greater than or equal to 3.6V and less than or equal to 5.4V. Exemplarily, the well region positive voltage Verase+ is greater than or equal to 3.6V and less than or equal to 5.4V. Exemplarily, the first erase positive voltage Vberase is greater than or equal to 3.6V and less than or equal to 5.4V. Exemplarily, the second erase positive voltage Vserase is greater than or equal to 3.6V and less than or equal to 5.4V. Exemplarily, the selection tube turn-on positive voltage Vweon is greater than or equal to 3.6V and less than or equal to 5.4V.

[0093] In this embodiment, the minimum unit of erasing a single storage tube NOR flash memory of a 3D group pair structure is all storage tubes corresponding to one gate layer.

[0094] In the single-storage-tube NOR flash memory of the 3D group pair structure provided by the present invention, the gate stack structure includes a plurality of gate layers 101 isolated from each other, and a plurality of openings 103 are provided in the gate stack structure. The first doped column 201, the second doped column 202 and the charge trap structure 205 are all erected in the opening 103, thereby forming a 3D structure NOR storage array, wherein the channel region of a storage tube is a portion of a first doped column 201 corresponding to the side wall of a gate layer 101 in the opening 103, two first doped columns 201 are arranged in one opening 103 and each first doped column 201 independently corresponds to two second doped columns 202 and one charge trap structure 205, so that two columns of storage tubes in the vertical direction are formed in the same opening, two storage tubes in the same group are in the same opening, and the two storage tubes in the same group can be individually controlled by two groups of local source lines and local bit lines, thereby realizing a 1T storage structure, thus significantly improving the 3D The storage density of the NOR flash memory is high, and when the flash memory is writing data, the voltage of the local bit line and the local source line corresponding to a storage tube are equal, which can reduce the programming power consumption of the NOR flash memory.

[0095] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A single storage tube NOR flash memory with a 3D pair structure, characterized in that: include: A gate stack structure, the gate stack structure comprising a plurality of first isolation layers and a plurality of gate layers stacked in layers, one of the gate layers being interspersed between two adjacent first isolation layers, and the gate stack structure having a plurality of openings; A plurality of first doped columns, wherein the first doped columns are of a first conductivity type, two of the first doped columns form a group and stand in one of the openings at intervals; the first doped columns have opposite first and second sidewalls and opposite third and fourth sidewalls; for a group of the first doped columns, a first sidewall of one of the first doped columns faces a sidewall of the opening and a second sidewall faces another first doped column; a plurality of second doped columns, the second doped columns being of a second conductivity type opposite to the first conductivity type; Two of the second doped columns form a group and are disposed in the same opening, and the two second doped columns in the same group respectively cover the third side wall and the fourth side wall of one of the first doped columns; a plurality of charge trap structures, wherein one of the charge trap structures fills a gap between one of the first doped columns and a sidewall of the opening to which the first sidewall of the first doped column faces; as well as A plurality of local bit lines and a plurality of local source lines are erected in the plurality of the openings, wherein one local bit line and one local source line form a group and correspond to a group of the second doped columns; one of the two second doped columns in the same group is in contact with the corresponding local bit line, and the other is in contact with the corresponding local source line; Among them, the single storage tube NOR flash memory of the 3D pair structure includes multiple storage tubes, the channel region of one of the storage tubes is a portion of the first doped column corresponding to the side wall of one of the gate layers in the opening, the channel of one of the storage tubes is a planar channel, and the two storage tubes corresponding to one of the gate layers in one of the openings are two storage tubes in a pair.

2. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 1, characterized in that: The plurality of openings are arranged in a plurality of rows in the gate stack structure, and the openings in two adjacent rows are staggered in a vertical direction of the row direction.

3. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 1, characterized in that: The first side wall and the second side wall of the first doped column are both straight planes; and the channel of the storage tube is a straight channel.

4. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 1, characterized in that: The single-storage-tube NOR flash memory of the 3D pair structure further includes a substrate, and the gate stack structure is formed on the substrate.

5. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 4, characterized in that: A plurality of bit line selection tubes and a plurality of source line selection tubes are formed on the substrate, two of the bit line selection tubes form a group, and two of the source line selection tubes form a group; a plurality of global bit lines and a plurality of global source lines are also formed on the top surface of the substrate, two of the global bit lines form a group, and two of the global source lines form a group; the first ends of the two bit line selection tubes in the same group are connected to the same local bit line and the second ends are respectively connected to the two global bit lines in the same group; the first ends of the two source line selection tubes in the same group are connected to the same local source line and the second ends are respectively connected to the two global source lines in the same group.

6. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 5, characterized in that: A plurality of word lines are formed on the substrate; a group of the bit line selection tubes includes a first bit line selection tube and a second bit line selection tube, and a group of the source line selection tubes includes a first source line selection tube and a second source line selection tube; for the selection tubes corresponding to a group of the local bit lines and the local source lines, the gate of the first bit line selection tube and the gate of the first source line selection tube are commonly connected to one of the word lines, and the gate of the second bit line selection tube and the gate of the second source line selection tube are commonly connected to another of the word lines.

7. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 6, characterized in that: A plurality of the openings are arranged in rows and columns on the substrate, the local bit lines and the local source lines of the same group in one of the openings are arranged in a row, two groups of the local bit lines and the local source lines in one of the openings are arranged in two rows, and the local bit lines and the local source lines in a row of the openings are arranged in two rows; for the selection tubes corresponding to the local bit lines and the local source lines in the same row, the gate of the first bit line selection tube and the gate of the first source line selection tube are commonly connected to one of the word lines, and the gate of the second bit line selection tube and the gate of the second source line selection tube are commonly connected to another of the word lines.

8. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 7, characterized in that: A group of the global bit lines includes a first global bit line and a second global bit line, and a group of the global source lines includes a first global source line and a second global source line; in the bit line selection tubes corresponding to the local bit lines in the same column of the openings, the second end of the first bit line selection tube is connected to the first global bit line, and the second end of the second bit line selection tube is connected to the second global bit line; in the source line selection tubes corresponding to the local source lines in the same column of the openings, the second end of the first source line selection tube is connected to the first global source line, and the second end of the second source line selection tube is connected to the second global source line.

9. The single storage tube NOR flash memory of the 3D pair structure as claimed in claim 1, characterized in that: The charge trap structure includes a first oxide layer, a nitride layer, and a second oxide layer stacked vertically on the first side wall of the first doped column; the first oxide layer contacts the corresponding first side wall of the first doped column, the second oxide layer contacts the opening side wall, and the nitride layer is located between the first oxide layer and the second oxide layer.

10. An operating method of a single storage tube NOR flash memory with a 3D pair structure, characterized in that: The method is used for performing a read operation on a single storage tube NOR flash memory of a 3D pair structure according to any one of claims 1 to 9, comprising: The gate layer, local bit line and local source line corresponding to the storage tube to be read are respectively referred to as a selected gate layer, a selected local bit line and a selected local source line; Applying a positive turn-on voltage to the selected gate layer to turn on the storage tube corresponding to the selected gate layer; applying a negative turn-off voltage to the unselected gate layer to turn off the storage tube corresponding to the unselected gate layer; Applying a first read voltage to the selected local bit line and applying a second read voltage to the selected local source line; suspending unselected local bit lines and unselected local source lines; and A negative well region voltage is applied to all the first doped columns.

11. An operating method of a single storage tube NOR flash memory with a 3D pair structure, characterized in that: The method is used for performing a write operation on a single storage tube NOR flash memory of a 3D pair structure according to any one of claims 1 to 9, comprising: The gate layer, local bit line and local source line corresponding to the storage tube to be written are respectively referred to as a selected gate layer, a selected local bit line and a selected local source line; Applying a first positive voltage to the selected gate layer, and applying a first negative voltage to the unselected gate layer; applying a second negative voltage to all of the first doped columns; and A third negative voltage is applied to both the selected local bit line and the selected local source line, and a second positive voltage is applied to both the unselected local bit line and the unselected local source line.

12. A method for operating a single storage tube NOR flash memory with a 3D pair structure, characterized in that: The method for performing an erase operation on a single storage tube NOR flash memory with a 3D pair structure according to any one of claims 1 to 9 comprises: The gate layer, local bit line and local source line corresponding to the storage tube to be erased are respectively referred to as a selected gate layer, a selected local bit line and a selected local source line; Applying an erasing negative voltage to the selected gate layer and applying a protective positive voltage to the unselected gate layer; applying a first positive erasure voltage to all the local bit lines, and applying a second positive erasure voltage to all the local source lines; and A well region positive voltage is applied to all the first doped columns.

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