A data processing method and a data processing device

Abstract

The embodiment of the present application discloses a data processing method and a data processing device. The method of the embodiment of the present application includes the following steps. Convolution interleaving is performed on n channel data streams to obtain n first data streams. Wherein, n>1, and the n channel data streams are all subjected to the first FEC encoding. Each a codeword after the first FEC encoding is distributed in b channel data streams, a≤b≤n, a≥1. The continuous z symbols in each first data stream come from z different codewords, z>1. Afterwards, each K first data stream in the n first data streams is multiplexed to obtain 1 second data stream, so as to obtain a total of m second data streams. Wherein, the n first data streams include G first data stream subsets, and the symbols in different first data stream subsets come from different codewords, m=n / K, K>1, G>1. The continuous y symbols in each second data stream come from y different codewords, y>z.

Description

[0001] This application claims the priority of the Chinese patent application filed with the China Patent Office on January 28, 2022, with application number 202210109956.X and invention name “A data processing method and data processing device”, the priority of the Chinese patent application filed with the China Patent Office on March 23, 2022, with application number 202210290887.7 and invention name “A data processing method and data processing device”, and the priority of the Chinese patent application filed with the China Patent Office on September 1, 2022, with application number 202211065772.4 and invention name The priority of the Chinese patent application entitled "A Data Processing Method and Data Processing Device", the priority of the Chinese patent application filed with the China Patent Office on October 24, 2022, with application number 202211305113.3 and invention name "A Data Processing Method and Data Processing Device", and the priority of the Chinese patent application filed with the China Patent Office on November 18, 2022, with application number 202211448533.7 and invention name "A Data Processing Method and Data Processing Device", all of which are incorporated into this application by application. Technical Field

[0002] The present application relates to the field of communications, and in particular to a data processing method and a data processing device. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing toward high capacity and ultra-high speeds. Forward error correction (FEC) is used to correct errors in transmitted data, resolving transmission errors and recovering the original data from the received data.

[0004] Currently, a cascade FEC transmission scheme is proposed, in which the transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted, and sends the data after the first FEC encoding to the transmitting processing module. The transmitting processing module performs a second FEC encoding on the data after the first FEC encoding, and transmits the data after the second FEC encoding to the data receiving end through a channel. Specifically, the transmitting processing module will receive multiple data streams, and it is necessary to first perform convolution interleaving on the multiple data streams, and then perform a second FEC encoding on each data stream after the convolution interleaving. It should be understood that in order to improve performance, the data stream participating in the second FEC encoding should come from multiple codewords after the first FEC encoding. However, this requires the use of convolution interleaving with a longer delay to achieve this, and the application effect is not ideal in scenarios requiring low latency. Summary of the Invention

[0005] The embodiments of the present application provide a data processing method and a data processing device, which can achieve better cascaded FEC solution performance in a scenario with lower latency.

[0006] In a first aspect, the present application provides a data processing method comprising the following steps. First, convolution interleaving is performed on n channel data streams to obtain n first data streams. Here, n is an integer greater than 1, and all n channel data streams undergo first FEC encoding. Each a codeword after the first FEC encoding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. The z consecutive symbols in each first data stream come from z different codewords, where z is an integer greater than 1. Subsequently, each K first data streams in the n first data streams are multiplexed to obtain a second data stream, resulting in a total of m second data streams. Here, the n first data streams include G first data stream subsets, where the symbols in different first data stream subsets come from different codewords, where m = n / K, K is an integer greater than 1, and G is an integer greater than 1. The y consecutive symbols in each second data stream come from y different codewords, where y > z. If K≤G, then the K first data streams are respectively from the K first data stream subsets. If K>G, then the K first data streams include K / G first data streams in each first data stream subset.

[0007] In this embodiment, the n-channel data streams are all codeword streams after outer code encoding. The n-channel data streams are respectively subjected to convolution interleaving processing, and the n-channel data streams after convolution interleaving are multiplexed into m-channel second data streams, which are then subjected to inner code encoding. By adopting the data interleaving and multiplexing processing scheme provided by the present application, it is possible to achieve the multiple symbols of the multiplexed m-channel data streams from multiple different outer codewords in the continuous output with a shorter delay, so that the cascaded FEC scheme can help reduce the delay of data interleaving while ensuring good performance. In other words, the scheme of combining convolution interleaving processing with data multiplexing in the present application makes the overall delay of the cascaded FEC scheme lower, which is more suitable for application scenarios requiring low delay.

[0008] In some possible implementations, performing convolution interleaving on a channel data stream to obtain a first data stream includes: delaying the channel data stream according to p delay lines to obtain the first data stream. Wherein, p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units of each two adjacent delay lines is Q. Each storage unit is used to store d symbols, and z = p*d. The symbols in each channel data stream are input into the p delay lines in sequence according to the sequence of the p delay lines. Each delay line inputs d symbols at a time and outputs d symbols at a time. The continuous p*d symbols in a first data stream include d symbols output by each delay line. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. In this implementation, a specific implementation method of convolution interleaving is provided, which improves the practicality of this solution.

[0009] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 storage units, where d(p*Q+1)≥a*N / b, d≤a, and N is the length of the codeword, so that z consecutive symbols in each first data stream can come from z different codewords.

[0010] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 storage units. Here, d(p*Q-1)≥a*N / b, d≤a, and N is the length of a codeword, so that z consecutive symbols in each first data stream can come from z different codewords.

[0011] In some possible implementations, if K ≤ G, then y = K*z; if K > G, then y = G*z. This multiplexing approach ensures that y > z can be achieved in multiple different application scenarios, achieving better performance of the cascaded FEC solution with lower latency.

[0012] In some possible implementations, each second data stream includes multiple second data stream symbol subsets, each second data stream symbol subset includes K groups of symbols, and each group of symbols includes Δ symbols. Two adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets. If K ≤ G, then Δ is a divisor of z; if K > G, then Δ = z.

[0013] In this embodiment, since the two adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets, the y consecutive symbols in the second data stream after multiplexing come from y different codewords, where y>z (y=K*z or y=G*z). It should be understood that if only convolution interleaving is used to obtain that the y consecutive symbols in the output data stream come from y different codewords, the required delay is relatively high. However, in this solution, while reducing the time occupied by convolution interleaving, combined with multiplexing processing, comparable performance can still be achieved. In addition, the time occupied by multiplexing processing is relatively short, and combining convolution interleaving and multiplexing can achieve comparable performance with a shorter delay.

[0014] In some possible implementations, the jth group of symbols in each second data stream symbol subset comes from the jth first data stream among the K first data streams participating in the multiplexing, where 0≤j≤K-1. This provides a rule for selecting the K first data streams participating in the multiplexing, ensuring that two adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets.

[0015] In some possible implementations, if K>G, two adjacent first data streams among the K first data streams participating in the multiplexing are from different first data stream subsets. Through the above approach, in the scenario where K>G, a rule for selecting the K first data streams participating in the multiplexing is provided, ensuring that y=G*z.

[0016] In some possible implementations, if K>G, each of the G consecutive first data streams participating in the multiplexing is from a different subset of the first data stream. Through the above approach, in the scenario where K>G, a rule for selecting the K first data streams participating in the multiplexing is provided, further ensuring that y=G*z.

[0017] In some possible implementations, n=32, and K=2, 4, or 8. Through the above approach, several specific types of multiplexers are provided, expanding the application scenarios of this solution.

[0018] In some possible implementations, n = 32, p = 2, 3, 4, 6 or 8, and d = 1 or 2. Through the above approach, several specific types of convolutional interleavers are provided, expanding the application scenarios of this solution.

[0019] In some possible implementations, a = 1 or 2, and b = 4, 8, or 16. Through the above-mentioned approach, several distribution modes of channel data streams are provided, which expands the application scenarios of this solution.

[0020] In some possible implementations, before performing convolution interleaving on the n channel data streams to obtain the n first data streams, the method further includes: performing channel reordering on the n channel data streams so that the n channel data streams are arranged in a preset order.

[0021] In some possible implementations, before performing convolution interleaving on the n channel data streams to obtain the n first data streams, the method further includes: performing channel de-skew on the n channel data streams. In this implementation, a specific implementation method for channel data alignment is provided, which enhances the feasibility of this solution.

[0022] In some possible implementations, before performing convolution interleaving on the n channel data streams to obtain the n first data streams, the method further includes: aligning the n channel data streams so that symbols in the n channel data streams are aligned. This implementation provides another specific implementation of channel data alignment, enhancing the flexibility of the present solution.

[0023] In some possible implementations, after obtaining a total of m second data streams, the method further includes: performing second FEC encoding on each of the m second data streams. The information bit length of the second FEC encoding is less than or equal to y symbols.

[0024] In a second aspect, the present application provides a data processing device. The data processing device includes a convolutional interleaver and a multiplexer. The convolutional interleaver is configured to perform convolutional interleaving on n channel data streams to obtain n first data streams. Where n is an integer greater than 1, and each of the n channel data streams undergoes first FEC encoding. Each a codeword after the first FEC encoding is distributed across b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. The z consecutive symbols in each first data stream come from z different codewords, where z is an integer greater than 1. The multiplexer is configured to multiplex each K first data streams among the n first data streams to obtain one second data stream, thereby obtaining a total of m second data streams. Where n first data streams include G first data stream subsets, where symbols in different first data stream subsets come from different codewords, where m = n / K, K is an integer greater than 1, and G is an integer greater than 1. The y consecutive symbols in each second data stream come from y different codewords, where y > z. If K≤G, then the K first data streams are respectively from the K first data stream subsets. If K>G, then the K first data streams include K / G first data streams in each first data stream subset.

[0025] In some possible implementations, the convolution interleaver is specifically configured to delay a channel data stream according to p delay lines to obtain a first data stream. Here, p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between two adjacent delay lines is Q. Each storage unit is used to store d symbols, and z = p*d. The symbols in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines. Each delay line inputs d symbols at a time and outputs d symbols at a time. The continuous p*d symbols in a first data stream include d symbols output by each delay line. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0026] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 storage units, where d(p*Q+1)≥a*N / b, N is the length of the codeword, and d≤a.

[0027] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 storage units, where d(p*Q-1)≥a*N / b, N is the length of the codeword, and d≤a.

[0028] In some possible implementations, if K≤G, then y=K*z; if K>G, then y=G*z.

[0029] In some possible implementations, each second data stream includes multiple second data stream symbol subsets, each second data stream symbol subset includes K groups of symbols, and each group of symbols includes Δ symbols. Two adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets. If K ≤ G, then Δ is a divisor of z; if K > G, then Δ = z.

[0030] In some possible implementations, the j-th group of symbols in each second data stream symbol subset comes from the j-th first data stream among the K first data streams participating in the multiplexing, where 0≤j≤K-1.

[0031] In some possible implementations, if K>G, two adjacent first data streams among the K first data streams participating in the multiplexing come from different first data stream subsets.

[0032] In some possible implementations, if K>G, each of the G consecutive first data streams participating in the multiplexing comes from different first data stream subsets.

[0033] In some possible implementations, n=32, K=2, 4, or 8.

[0034] In some possible implementations, n=32, p=2, 3, 4, 6 or 8, and d=1 or 2.

[0035] In some possible implementations, a=1 or 2, b=4, 8, or 16.

[0036] In some possible embodiments, the data processing device further includes a channel reordering unit, which, before performing convolution interleaving on the n channel data streams to obtain n first data streams, is used to: perform channel reordering on the n channel data streams so that the n channel data streams are arranged in a preset order.

[0037] In some possible implementations, the data processing device further includes a channel data alignment unit. Before performing convolution interleaving on the n channel data streams to obtain the n first data streams, the channel data alignment unit is configured to perform channel de-skew on the n channel data streams.

[0038] In some possible implementations, the data processing device further includes a channel data alignment unit. Before performing convolution interleaving on the n channel data streams to obtain n first data streams, the channel data alignment unit is used to: align the n channel data streams so that the symbols in the n channel data streams are aligned.

[0039] In some possible implementations, the data processing device further includes an encoder. After obtaining a total of m second data streams, the encoder is configured to: perform second FEC encoding on each of the m second data streams, where the information bit length of the second FEC encoding is less than or equal to y symbols.

[0040] In a third aspect, the present application provides a data processing method, which includes the following steps. Interleaving n channel data streams to obtain m target data streams, where n is a multiple of 4. The n channel data streams are all encoded by the first forward error correction FEC, and each a codeword after the first FEC encoding is distributed in b channel data streams, a≤b≤n, and n is divisible by b. The F consecutive symbols in each target data stream come from F different codewords, F>a. The F consecutive symbols in each target data stream come from at least K1 different channel data streams, and the F consecutive symbols in each target data stream come from at most K2 symbols of the n symbols aligned by the n channel data streams, K1 and K2 are divisors of n, and K2 is a divisor of K1. At most K3 of the F consecutive symbols in each target data stream come from the same channel data stream, The integer representing the quotient of F / K1 rounded up, where any two of the K3 symbols are separated by at least K4 symbols on the same channel data stream, and K4 ≥ a*N*K2 / n, where N is the codeword length.

[0041] In some possible implementations, K1=n / 4, K2=n / 16.

[0042] In some possible implementations, interleaving n channel data streams to obtain m target data streams includes: performing convolution interleaving on each of the n channel data streams to obtain n first data streams. The z consecutive symbols in each first data stream come from at least e different codewords, where z is an integer greater than 1, a≤e≤F, and e*k2≥F. At most k1 / k2 of the z consecutive symbols in each first data stream come from the same codeword. Grouping and interleaving each K1 first data stream among the n first data streams to obtain S target data streams, thereby obtaining a total of m target data streams. Wherein, S is an integer greater than or equal to 1, m=S*n / K1, S≥k1 / k2, the n first data streams include K1 first data stream groups, the symbols of every two first data streams in the same first data stream group come from the same codeword, and the K1 first data streams each come from the K1 first data stream groups.

[0043] In some possible implementations, performing convolution interleaving on a channel data stream to obtain a first data stream includes: delaying the channel data stream according to p delay lines to obtain the first data stream. p is an integer greater than 1, p*a ≥ F / k², each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is used to store d symbols, and z = p*d. Symbols in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs d symbols at a time and outputs d symbols at a time, and the consecutive p*d symbols in the first data stream include the d symbols output by each delay line, Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d ≤ a.

[0044] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 storage units, wherein d(p*Q+1)≥K4.

[0045] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 storage units, wherein d(p*Q-1)≥K4.

[0046] In some possible implementations, the K first data streams participating in group interleaving include a first symbol matrix, the first symbol matrix including K rows and B columns of symbols, where B = R*p*d, and R is an integer greater than or equal to 1. The S target data streams after group interleaving include a second symbol matrix, the second symbol matrix including S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix come from at least F different codewords, and at most R*K1 / K2 symbols in the first symbol matrix come from the same codeword.

[0047] In some possible implementations, the F symbols in each row of the second symbol matrix come from at least Column, and Each column has at most K2 symbols, The F symbols in each row of the second symbol matrix include at least symbols, represents an integer obtained by rounding down the quotient of F / K1, and the F symbols in each row of the second symbol matrix include at most symbols, Indicates the integer obtained by rounding up the quotient of F / K.

[0048] In some possible implementations, symbols from odd columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix. Symbols from even columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix.

[0049] In some possible implementations, the symbols output by the delay lines with the same delay value in each row of the second symbol matrix come from different rows of the first symbol matrix.

[0050] In some possible implementations, a maximum of K3 symbols in each row of the second symbol matrix come from the same row of the first symbol matrix, and any two of the K3 symbols are output by two delay lines whose delay difference is greater than or equal to 2*Q*d.

[0051] In some possible implementations, interleaving n channel data streams to obtain m target data streams includes: performing a first group interleaving on the n channel data streams to obtain T first data streams, wherein C consecutive symbols in each first data stream come from at least E different codewords, where T = n / K1, C is a multiple of a, and E ≥ K2*a. Performing a convolutional interleaving on the T first data streams to obtain T second data streams, wherein H consecutive symbols in each second data stream come from at least F different codewords, where F ≥ E, and at most K1 / K2 consecutive symbols of the H consecutive symbols in each second data stream come from the same codeword. Performing a second group interleaving on each of the T second data streams to obtain S target data streams, resulting in a total of m target data streams, where m = T*S, and S ≥ k1 / K2.

[0052] In some possible implementations, the n channel data streams participating in the first group interleaving include a third symbol matrix, the third symbol matrix including n rows and A columns of symbols, where A is a multiple of a. The T first data streams after the first group interleaving include a fourth symbol matrix, the fourth symbol matrix including T rows and C columns of symbols, where T is a divisor of n, n*A=T*C. Every T consecutive symbols in a column of the third symbol matrix constitute a symbol submatrix, and the T symbols in each column of the fourth symbol matrix correspond one-to-one to each symbol submatrix in the third symbol matrix.

[0053] In some possible embodiments, the symbol sub-matrices in the third symbol matrix are arranged in a first order, the 1st to nth rows of each column in the third symbol matrix include the 1st to n / Tth symbol sub-matrices arranged in the first order, the n / Tth symbol sub-matrix of the previous column to the 1st symbol sub-matrix of the next column in two adjacent columns of the third symbol matrix are two consecutive symbol sub-matrices arranged in the first order, the T symbols in the 1st column of the fourth symbol matrix come from the first symbol sub-matrix arranged in the first order in the third symbol matrix, and so on, until the T symbols in the Cth column of the fourth symbol matrix come from the last symbol sub-matrix arranged in the first order in the third symbol matrix. Alternatively, the symbol sub-matrices in the third symbol matrix are arranged in the second order, the 1st column to the Ath row of every T rows in the third symbol matrix include the 1st to the Ath symbol sub-matrices arranged in the second order, the Ath symbol sub-matrix in the first T rows to the 1st symbol sub-matrix in the last T rows of two adjacent consecutive T rows of the third symbol matrix are two consecutive symbol sub-matrices arranged in the second order, the T symbols in the 1st column of the fourth symbol matrix come from the first symbol sub-matrix arranged in the second order in the third symbol matrix, and so on, until the T symbols in the Cth column of the fourth symbol matrix come from the last symbol sub-matrix arranged in the second order in the third symbol matrix.

[0054] In some possible implementations, performing convolution interleaving on a first data stream to obtain a second data stream includes: delaying the first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, p*E≥F, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is used to store C symbols, p*C=H, the symbols in each first data stream are input into the p delay lines in sequence according to the sequence of the p delay lines, each delay line inputs C symbols at a time and outputs C symbols at a time, the consecutive p*C symbols in a second data stream include C symbols output by each delay line, and Q is an integer greater than or equal to 1.

[0055] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 storage units, wherein C(p*Q+1)≥K1*K4.

[0056] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 storage units, wherein C(p*Q-1)≥K1*K4.

[0057] In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output by p delay lines respectively, the symbols in each symbol set come from at least F different codewords, each target data stream includes F symbols, R*p*C=S*F, R is an integer greater than or equal to. The F symbols in the target data stream come from at least different subsets of symbols, and Each symbol subset has at most K2*a symbols, Indicates the integer obtained by rounding up the quotient of F / (K2*a).

[0058] In some possible implementations, the F symbols in the target data stream include a first group of symbols from a first symbol subset and a second group of symbols from a second symbol subset, the first symbol subset and the second symbol subset belong to the same symbol set, the first symbol subset and the second symbol subset are output by two adjacent delay lines, the symbols in the first symbol subset and the symbols in the second symbol subset are arranged in order, and the order of the first group of symbols in the first symbol subset is different from the order of the second group of symbols in the second symbol subset. The F symbols in the target data stream include a third group of symbols from a third symbol subset and a fourth group of symbols from a fourth symbol subset, the third symbol subset and the fourth symbol subset belong to different symbol sets, the third symbol subset and the fourth symbol subset are output by the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are arranged in order, and the order of the third group of symbols in the third symbol subset is different from the order of the fourth group of symbols in the fourth symbol subset.

[0059] In some possible implementations, each target data stream has at most F symbols. symbols come from the same set of symbols, Integer representing the quotient of F / R rounded up.

[0060] In some possible implementations, after obtaining a total of m target data streams, the method further includes: performing second FEC encoding on each of the m target data streams, where the information bit length of the second FEC encoding is equal to F symbols.

[0061] In a fourth aspect, the present application provides a data processing device, which includes an interleaving module. The interleaving module is used to: interleave n channel data streams to obtain m target data streams, where n is a multiple of 4, and the n channel data streams are all encoded by the first forward error correction FEC. After the first FEC encoding, each a codeword is distributed in b channel data streams, a≤b≤n, and n is divisible by b. The F consecutive symbols in each target data stream come from F different codewords, and F>a. The F consecutive symbols in each target data stream come from at least K1 different channel data streams, and the F consecutive symbols in each target data stream come from at most K2 symbols of the n symbols aligned by the n channel data streams, K1 and K2 are divisors of n, and K2 is a divisor of K1. At most K3 of the F consecutive symbols in each target data stream come from the same channel data stream, The integer representing the quotient of F / K1 rounded up, where any two of the K3 symbols are separated by at least K4 symbols on the same channel data stream, and K4 ≥ a*N*K2 / n, where N is the codeword length.

[0062] In some possible implementations, K1=n / 4, K2=n / 16.

[0063] In some possible implementations, the interleaving module includes a convolution interleaver and a block interleaver. The convolution interleaver is configured to perform convolution interleaving on n channel data streams to obtain n first data streams, wherein z consecutive symbols in each first data stream come from at least e different codewords, where z is an integer greater than 1, a≤e≤F, and e*k2≥F, and at most k1 / k2 of the z consecutive symbols in each first data stream come from the same codeword. The block interleaver is configured to perform block interleaving on each K1 of the n first data streams to obtain S target data streams, thereby obtaining a total of m target data streams, where S is an integer greater than or equal to 1, m=S*n / K1, S≥k1 / k2, the n first data streams include K1 first data stream groups, the symbols of every two first data streams in the same first data stream group come from the same codeword, and the K1 first data streams are respectively derived from the K1 first data stream groups.

[0064] In some possible implementations, the convolutional interleaver is specifically configured to delay a channel data stream according to p delay lines to obtain a first data stream, where p is an integer greater than 1, p*a ≥ F / k², each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is used to store d symbols, and z = p*d. Symbols in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs d symbols at a time and outputs d symbols at a time, and the consecutive p*d symbols in the first data stream include the d symbols output by each delay line, Q is an integer greater than or equal to 1, d is an integer greater than or equal to 1, and d ≤ a.

[0065] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 storage units, wherein d(p*Q+1)≥K4.

[0066] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 storage units, wherein d(p*Q-1)≥K4.

[0067] In some possible implementations, the K first data streams participating in group interleaving include a first symbol matrix, the first symbol matrix including K rows and B columns of symbols, where B = R*p*d, and R is an integer greater than or equal to 1. The S target data streams after group interleaving include a second symbol matrix, the second symbol matrix including S rows and F columns of symbols, where K*B = S*F. The symbols in the first symbol matrix come from at least F different codewords, and at most R*K1 / K2 symbols in the first symbol matrix come from the same codeword.

[0068] In some possible implementations, the F symbols in each row of the second symbol matrix come from at least Column, and Each column has at most K2 symbols, The F symbols in each row of the second symbol matrix include at least symbols, represents an integer obtained by rounding down the quotient of F / K1, and the F symbols in each row of the second symbol matrix include at most symbols, Indicates the integer obtained by rounding up the quotient of F / K.

[0069] In some possible implementations, the symbols from the odd columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix, and the symbols from the even columns of the first symbol matrix in each row of the second symbol matrix are located in different rows of the first symbol matrix.

[0070] In some possible implementations, the symbols output by the delay lines with the same delay value in each row of the second symbol matrix come from different rows of the first symbol matrix.

[0071] In some possible implementations, a maximum of K3 symbols in each row of the second symbol matrix come from the same row of the first symbol matrix, and any two of the K3 symbols are output by two delay lines whose delay difference is greater than or equal to 2*Q*d.

[0072] In some possible implementations, the convolutional interleaving module includes a first block interleaver, a convolutional interleaver, and a second block interleaver. The first block interleaver is configured to perform a first block interleave on n channel data streams to obtain T first data streams, wherein C consecutive symbols in each first data stream come from at least E different codewords, T = n / K1, C is a multiple of a, and E ≥ K2*a. The convolutional interleaver is configured to perform a convolutional interleave on the T first data streams to obtain T second data streams, wherein H consecutive symbols in each second data stream come from at least F different codewords, F ≥ E, and at most K1 / K2 consecutive symbols of the H consecutive symbols in each second data stream come from the same codeword. The second block interleaver is configured to perform a second block interleave on each of the T second data streams to obtain S target data streams, thereby obtaining a total of m target data streams, m = T*S, and S ≥ k1 / K2.

[0073] In some possible implementations, the n channel data streams participating in the first group interleaving include a third symbol matrix, the third symbol matrix including n rows and A columns of symbols, where A is a multiple of a. The T first data streams after the first group interleaving include a fourth symbol matrix, the fourth symbol matrix including T rows and C columns of symbols, where T is a divisor of n, n*A=T*C. Every T consecutive symbols in a column of the third symbol matrix constitute a symbol submatrix, and the T symbols in each column of the fourth symbol matrix correspond one-to-one to each symbol submatrix in the third symbol matrix.

[0074] In some possible embodiments, the symbol sub-matrices in the third symbol matrix are arranged in a first order, the 1st to nth rows of each column in the third symbol matrix include the 1st to n / Tth symbol sub-matrices arranged in the first order, the n / Tth symbol sub-matrix of the previous column to the 1st symbol sub-matrix of the next column in two adjacent columns of the third symbol matrix are two consecutive symbol sub-matrices arranged in the first order, the T symbols in the 1st column of the fourth symbol matrix come from the first symbol sub-matrix arranged in the first order in the third symbol matrix, and so on, until the T symbols in the Cth column of the fourth symbol matrix come from the last symbol sub-matrix arranged in the first order in the third symbol matrix. Alternatively, the symbol sub-matrices in the third symbol matrix are arranged in the second order, the 1st column to the Ath row of every T rows in the third symbol matrix include the 1st to the Ath symbol sub-matrices arranged in the second order, the Ath symbol sub-matrix in the first T rows to the 1st symbol sub-matrix in the last T rows of two adjacent consecutive T rows of the third symbol matrix are two consecutive symbol sub-matrices arranged in the second order, the T symbols in the 1st column of the fourth symbol matrix come from the first symbol sub-matrix arranged in the second order in the third symbol matrix, and so on, until the T symbols in the Cth column of the fourth symbol matrix come from the last symbol sub-matrix arranged in the second order in the third symbol matrix.

[0075] In some possible implementations, the convolutional interleaver is specifically configured to delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, p*E ≥ F, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is used to store C symbols, and p*C = H. Symbols in each first data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs C symbols at a time and outputs C symbols at a time, and the consecutive p*C symbols in a second data stream include the C symbols output by each delay line, and Q is an integer greater than or equal to 1.

[0076] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes 0 storage units, wherein C(p*Q+1)≥K1*K4.

[0077] In some possible implementations, the delay line with the smallest sequence number among the p delay lines includes 0 storage units, wherein C(p*Q-1)≥K1*K4.

[0078] In some possible implementations, each second data stream includes R symbol sets, each symbol set includes p symbol subsets, each symbol subset includes C symbols, the p symbol subsets are output by p delay lines respectively, the symbols in each symbol set come from at least F different codewords, each target data stream includes F symbols, R*p*C=S*F, R is an integer greater than or equal to. The F symbols in the target data stream come from at least different subsets of symbols, and Each symbol subset has at most K2*a symbols, Indicates the integer obtained by rounding up the quotient of F / (K2*a).

[0079] In some possible implementations, the F symbols in the target data stream include a first group of symbols from a first symbol subset and a second group of symbols from a second symbol subset, the first symbol subset and the second symbol subset belong to the same symbol set, the first symbol subset and the second symbol subset are output by two adjacent delay lines, the symbols in the first symbol subset and the symbols in the second symbol subset are arranged in order, and the order of the first group of symbols in the first symbol subset is different from the order of the second group of symbols in the second symbol subset. The F symbols in the target data stream include a third group of symbols from a third symbol subset and a fourth group of symbols from a fourth symbol subset, the third symbol subset and the fourth symbol subset belong to different symbol sets, the third symbol subset and the fourth symbol subset are output by the same delay line, the symbols in the third symbol subset and the symbols in the fourth symbol subset are arranged in order, and the order of the third group of symbols in the third symbol subset is different from the order of the fourth group of symbols in the fourth symbol subset.

[0080] In some possible implementations, each target data stream has at most F symbols. symbols come from the same set of symbols, Integer representing the quotient of F / R rounded up.

[0081] In some possible implementations, the data processing device further includes an encoder. After obtaining a total of m target data streams, the encoder is configured to: perform second FEC encoding on each of the m target data streams, where the information bit length of the second FEC encoding is equal to F symbols.

[0082] In a fifth aspect, the present application provides a data processing method comprising the following steps. First, each of the t channel data streams in n channel data streams is grouped and interleaved to obtain s first data streams, thereby obtaining a total of m first data streams. n = q*t, m = q*s, where n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. The n channel data streams are all encoded using a first forward error correction (FEC) encoding, and each a codeword after the first FEC encoding is distributed among b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each a consecutive symbol in each channel data stream comes from a different codeword, and each L1 consecutive symbol in each channel data stream comes from at least a different codeword, L1 = N*a / b, where N represents the length of the codeword. The t channel data streams include a consecutive symbols in each channel data stream, totaling t*a symbols. The t*a symbols include Δ bits in each symbol, totaling D bits, where D = Δ*t*a. The D bits are continuous in any of the s first data streams, where Δ = M / s, where M represents the number of bits contained in a symbol. Subsequently, convolution interleaving is performed on each of the m first data streams to obtain m second data streams.

[0083] In some possible implementations, each consecutive d symbols in each of the first data streams come from v different codewords, and each consecutive L2 symbols in each of the first data streams come from at least v different codewords, where v is divisible by a, L2=t / s*L1, and d=D / M.

[0084] In some possible implementations, n=32, 16 channel data streams located on odd channels among the n channel data streams come from the same codeword, 16 channel data streams located on even channels among the n channel data streams come from the same codeword, and the data streams located on odd channels and the data streams located on even channels among the n channel data streams come from different codewords.

[0085] In some possible implementations, t=2, s=1, and group-interleaving each of t channel data streams among n channel data streams to obtain s first data streams includes: group-interleaving the 2*i th channel data stream and the 2*i+1 th channel data stream to obtain one first data stream, where 0≤i<16. Two consecutive symbols in the 2*i th channel data stream and two consecutive symbols in the 2*i+1 th channel data stream are consecutive in the one first data stream obtained by group interleaving, and every four consecutive symbols in the one first data stream obtained by group interleaving come from four different codewords.

[0086] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by the group interleaving comes from the The first of 20 consecutive bits in the data stream of a channel bits, the represents rounding down, 0≤j<40, and β is 1, 2, 4, 5, 10 or 20.

[0087] In some possible implementations, t=2, s=1, and group-interleaving each of t channel data streams in n channel data streams to obtain s first data streams includes: group-interleaving the 2*i channel data stream and the 2*i+1 channel data stream to obtain one first data stream, where 0≤i<16. A j-th group of β consecutive bits in the 2*i channel data stream and a j-th group of β consecutive bits in the 2*i+1 channel data stream are consecutive in the one first data stream obtained by group interleaving, where j≥0, β is 1, 2, 4, 5, 10, or 20, and each of four consecutive symbols in the one first data stream obtained by group interleaving comes from four different codewords.

[0088] In some possible implementations, t=2, s=2, and grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i th channel data stream and the 2*i+1 th channel data stream to obtain the 2*i th first data stream and the 2*i+1 th first data stream, 0≤i<16. The 2 consecutive symbols in the 2*i-th channel data stream and the 2 consecutive symbols in the 2*i+1-th channel data stream, a total of 4 symbols, 5 bits of each symbol, a total of 20 bits, are continuous in the 2*i-th first data stream, and each of the 20 consecutive bits in the 2*i-th first data stream comes from 4 different codewords. The other 5 bits of each symbol in the 2*i-th channel data stream and the 2 consecutive symbols in the 2*i+1-th channel data stream, a total of 4 symbols, are continuous in the 2*i+1-th first data stream, and each of the 20 consecutive bits in the 2*i+1-th first data stream comes from 4 different codewords.

[0089] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0090] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0091] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving a total of 4 channel data streams, namely, the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, and the 4*i+3 channel data stream, to obtain a first data stream, 0≤i≤7, and each of the 4 channel data streams includes 2 consecutive symbols, a total of 8 symbols, in the 1 first data stream obtained by group interleaving. The invention relates to a first data stream obtained by group interleaving, wherein every consecutive 8 symbols in a first data stream obtained by group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords. The 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in a first data stream obtained by group interleaving come from different codewords respectively. The 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in a first data stream obtained by group interleaving come from different codewords respectively.

[0092] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving a total of 4 channel data streams, namely, the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, and the 4*i+3 channel data stream to obtain 1 first data stream, 0≤i≤7, the jth group of 2 consecutive symbols, totaling 8 symbols, included in each of the 4 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, and each of the 4 channel data streams includes The j-th group of two consecutive symbols are consecutive in a first data stream obtained by the group interleaving, j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0093] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: grouping and interleaving 4 channel data streams, namely the 4*i-th channel data stream, the 4*i+1-th channel data stream, the 4*i+2-th channel data stream, and the 4*i+3-th channel data stream, to obtain 1 first data stream, 0≤i≤7, the j-th symbol included in each of the 4 channel data streams, a total of 4 symbols, is continuous in the 1 first data stream obtained by the group interleaving, j≥0, and each 4 consecutive symbols in the 1 first data stream obtained by the group interleaving come from 4 different codewords.

[0094] In some possible implementations, t=8, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams, namely, the 8*i+1 channel data stream, the 8*i+2 channel data stream, the 8*i+3 channel data stream, the 8*i+4 channel data stream, the 8*i+5 channel data stream, the 8*i+6 channel data stream, and the 8*i+7 channel data stream, to obtain 1 first data stream, 0≤i≤3, and each of the 8 channel data streams includes 2 consecutive symbols, a total of 16 symbols, which are continuous in the 1 first data stream obtained by the group interleaving, and each consecutive 16 symbols in the 1 first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively.

[0095] In some possible implementations, t=8, s=1, and grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes:

[0096] Perform group interleaving on 8 channel data streams, namely, the 8*i th channel data stream, the 8*i+1 th channel data stream, the 8*i+2 th channel data stream, the 8*i+3 th channel data stream, the 8*i+4 th channel data stream, the 8*i+5 th channel data stream, the 8*i+6 th channel data stream, and the 8*i+7 th channel data stream, to obtain a first data stream, 0≤i≤3, the j th group of 2 consecutive symbols, totaling 16 symbols, included in each of the 8 channel data streams are continuous in the first data stream obtained by the group interleaving, the j th group of 2 consecutive symbols included in each of the 8 channel data streams are continuous in the first data stream obtained by the group interleaving, j≥0, and each consecutive 16 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively.

[0097] In some possible implementations, t=8, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams, namely, the 8*i-th channel data stream, the 8*i+1-th channel data stream, the 8*i+2-th channel data stream, the 8*i+3-th channel data stream, the 8*i+4-th channel data stream, the 8*i+5-th channel data stream, the 8*i+6-th channel data stream, and the 8*i+7-th channel data stream to obtain 1 first data stream, 0≤i≤3, and the 8 channel data streams The j-th symbol included in each channel data stream, a total of 8 symbols, are continuous in a first data stream obtained by the group interleaving, j≥0, each consecutive 8 symbols in the first data stream obtained by the group interleaving come from 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0098] In some possible implementations, n=32, the 16 consecutive channel data streams ordered first among the n channel data streams come from the same codeword, the 16 consecutive channel data streams ordered last among the n channel data streams come from the same codeword, and the 16 consecutive channel data streams ordered first and the 16 consecutive channel data streams ordered last among the n channel data streams come from different codewords.

[0099] In some possible implementations, t=2, s=1, and group-interleaving each of t channel data streams among n channel data streams to obtain s first data streams includes: group-interleaving the i-th channel data stream and the (i+16)-th channel data stream to obtain one first data stream, where 0≤i<16. Two consecutive symbols in the i-th channel data stream and two consecutive symbols in the (i+16)-th channel data stream are consecutive in the one first data stream obtained by group interleaving, and every four consecutive symbols in the one first data stream obtained by group interleaving come from four different codewords.

[0100] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by the group interleaving comes from the The first of 20 consecutive bits in the data stream of a channel bits, the represents rounding down, 0≤j<40, and β is 1, 2, 4, 5, 10 or 20.

[0101] In some possible implementations, t=2, s=1, and group-interleaving each of t channel data streams in n channel data streams to obtain s first data streams includes: group-interleaving the i-th channel data stream and the (i+16)-th channel data stream to obtain one first data stream, where 0≤i<16. A j-th group of β consecutive bits in the i-th channel data stream and a j-th group of β consecutive bits in the (i+16)-th channel data stream are consecutive in the one first data stream obtained by group interleaving, where j≥0, β is 1, 2, 4, 5, 10, or 20, and each of four consecutive symbols in the one first data stream obtained by group interleaving comes from four different codewords.

[0102] In some possible implementations, t=2, s=2, and grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: grouping and interleaving the i-th channel data stream and the i+16-th channel data stream to obtain the 2*i-th first data stream and the 2*i+1-th first data stream, 0≤i<16. The 2 consecutive symbols in the i-th channel data stream and the 2 consecutive symbols in the i+16-th channel data stream, a total of 4 symbols, 5 bits of each symbol, a total of 20 bits, are continuous in the 2*i-th first data stream, and each of the 20 consecutive bits in the 2*i-th first data stream comes from 4 different codewords. The other 5 bits of each symbol in the 2 consecutive symbols in the i-th channel data stream and the 2 consecutive symbols in the i+16-th channel data stream, a total of 4 symbols, are continuous in the 2*i+1-th first data stream, and each of the 20 consecutive bits in the 2*i+1-th first data stream comes from 4 different codewords.

[0103] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0104] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0105] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i channel data stream, the 2*i+1 channel data stream, the 2*i+16 channel data stream, and the 2*i+17 channel data stream, a total of 4 channel data streams, to obtain 1 first data stream, 0≤i≤7, and each of the 4 channel data streams includes 2 consecutive symbols, a total of 8 symbols, in the 1 first data stream obtained by the group interleaving. The data stream is continuous, every consecutive 8 symbols in a first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0106] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i channel data stream, the 2*i+1 channel data stream, the 2*i+16 channel data stream, and the 2*i+17 channel data stream, a total of 4 channel data streams, to obtain 1 first data stream, 0≤i≤7, the jth group of 2 consecutive symbols, a total of 8 symbols, included in each of the 4 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, and each of the 4 channel data streams includes 1 first data stream. The j-th group of two consecutive symbols are continuous in a first data stream obtained by the group interleaving, j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0107] In some possible implementations, t=4, s=1, and grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: grouping and interleaving the 2*i-th channel data stream, the 2*i+1-th channel data stream, the 2*i+16-th channel data stream, and the 2*i+17-th channel data stream, a total of 4 channel data streams, to obtain 1 first data stream, 0≤i≤7, the j-th symbol included in each of the 4 channel data streams, a total of 4 symbols, is continuous in the 1 first data stream obtained by the group interleaving, j≥0, and each 4 consecutive symbols in the 1 first data stream obtained by the group interleaving come from 4 different codewords.

[0108] In some possible implementations, t=8, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams, namely, the 4*i+1 channel data stream, the 4*i+2 channel data stream, the 4*i+3 channel data stream, the 4*i+16 channel data stream, the 4*i+17 channel data stream, the 4*i+18 channel data stream, and the 4*i+19 channel data stream, to obtain 1 first data stream, 0≤i≤3, and each of the 8 channel data streams includes 2 consecutive symbols, a total of 16 symbols, which are continuous in the 1 first data stream obtained by the group interleaving, and each consecutive 16 symbols in the 1 first data stream obtained by the group interleaving are from to at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of every 16 consecutive symbols in a first data stream obtained by the group interleaving come from different codewords respectively.

[0109] In some possible implementations, t=8, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams, namely the 4*i+1th channel data stream, the 4*i+2th channel data stream, the 4*i+3th channel data stream, the 4*i+16th channel data stream, the 4*i+17th channel data stream, the 4*i+18th channel data stream, and the 4*i+19th channel data stream, to obtain 1 first data stream, 0≤i≤3, the jth group of 2 consecutive symbols, totaling 16 symbols, included in each of the 8 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, the jth group of 2 consecutive symbols included in each of the 8 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, and j≥0 , every consecutive 16 symbols in a first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0110] In some possible implementations, t=8, s=1, and grouping and interleaving each t channel data streams in the n channel data streams to obtain s first data streams includes: grouping and interleaving 8 channel data streams, namely, the 4*i channel data stream, the 4*i+1 channel data stream, the 4*i+2 channel data stream, the 4*i+3 channel data stream, the 4*i+16 channel data stream, the 4*i+17 channel data stream, the 4*i+18 channel data stream, and the 4*i+19 channel data stream, to obtain 1 first data stream, 0≤i≤3, and the 8 channel data streams The j-th symbol included in each channel data stream in the stream, a total of 8 symbols, are continuous in a first data stream obtained by the group interleaving, j≥0, each consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0111] In some possible implementations, performing convolution interleaving on a first data stream to obtain a second data stream includes: delaying the first data stream according to p delay lines to obtain the second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is used to store d symbols, symbols in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs d symbols at a time and outputs d symbols at a time, the consecutive p*d symbols in the second data stream include the d symbols output by each delay line, and Q is an integer greater than or equal to 1.

[0112] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes zero storage units, d(p*Q+1)≥L2, and L2=t / s*L1. Alternatively, the delay line with the smallest sequence number among the p delay lines includes zero storage units, d(p*Q-1)≥L2, and L2=t / s*L1.

[0113] In some possible implementations, after performing convolution interleaving on the m first data streams to obtain m second data streams, the method further includes: performing second FEC encoding on the m second data streams to obtain m coded data streams. Information data of length K symbols in each coded data stream comes from at most K different codewords, where K ≥ p*d.

[0114] In some possible implementations, performing convolution interleaving on a first data stream to obtain a second data stream includes: delaying the first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units of each two adjacent delay lines is Q, each storage unit is used to store 4 symbols, the symbols in each channel data stream are sequentially input into the p delay lines according to the sequence numbers of the p delay lines, each delay line inputs 4 symbols at a time and outputs 4 symbols at a time, the consecutive p*4 symbols in the second data stream include 4 symbols output by each delay line, and Q satisfies 4(p*Q-1)≥272 or 4(p*Q+1)≥272 or 4(p*Q-1)≥544 or 4(p*Q+1)≥544.

[0115] In some possible implementations, after performing convolution interleaving on the m first data streams to obtain m second data streams, the method further includes: performing second FEC encoding on the m second data streams to obtain m coded data streams, wherein information data of a length of K symbols in each of the coded data streams comes from at most K different codewords, and K≥p*4.

[0116] In some possible implementations, performing convolution interleaving on a first data stream to obtain a second data stream includes: delaying the first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units of each adjacent delay line is Q; each storage unit is used to store 34 bits, and the bits in each channel data stream are sequentially input into the delay lines according to the sequence number of the p delay lines. The p delay lines have a single input of 34 bits and a single output of 34 bits, and the consecutive p*34 bits in one second data stream include the 34 bits output by each delay line; or, each storage unit is used to store 68 bits, and the bits in each channel data stream are sequentially input into the p delay lines according to the sequence numbers of the p delay lines, and each delay line has a single input of 68 bits and a single output of 68 bits, and the consecutive p*68 bits in one second data stream include the 68 bits output by each delay line.

[0117] In some possible implementations, p=2, and each storage unit is used to store 68 bits; or, p=4, and each storage unit is used to store 34 bits.

[0118] In a sixth aspect, the present application provides a data processing device. The data processing device includes a block interleaver and a convolutional interleaver. The block interleaver is configured to perform block interleaving on each of t channel data streams among n channel data streams to obtain s first data streams, thereby obtaining a total of m first data streams. n = q*t, m = q*s, where n is an integer greater than 1, n is divisible by q, q is an integer greater than or equal to 1, t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1. The n channel data streams are all encoded using a first forward error correction (FEC) encoding. After the first FEC encoding, each a codeword is distributed among b channel data streams, where a ≤ b ≤ n, n is divisible by b, and a is an integer greater than or equal to 1. Each a consecutive symbol in each channel data stream comes from a different codeword, and each L1 consecutive symbol in each channel data stream comes from at least a different codeword, where L1 = N*a / b, and N represents the length of the codeword. The t channel data streams include a consecutive symbols in each channel data stream, totaling t*a symbols. The t*a symbols include Δ bits in each symbol, totaling D bits, where D=Δ*t*a. The D bits are continuous in any one of the s first data streams, where Δ=M / s, where M represents the number of bits contained in a symbol. The convolutional interleaver is configured to perform convolutional interleaving on each of the m first data streams to obtain m second data streams.

[0119] In some possible implementations, each consecutive d symbols in each of the first data streams come from v different codewords, and each consecutive L2 symbols in each of the first data streams come from at least v different codewords, where v is divisible by a, L2=t / s*L1, and d=D / M.

[0120] In some possible implementations, n=32, 16 channel data streams located on odd channels among the n channel data streams come from the same codeword, 16 channel data streams located on even channels among the n channel data streams come from the same codeword, and the data streams located on odd channels and the data streams located on even channels among the n channel data streams come from different codewords.

[0121] In some possible implementations, t=2, s=1, and the group interleaver is specifically configured to: perform group interleaving on the 2*i th channel data stream and the 2*i+1 th channel data stream to obtain a first data stream, where 0≤i<16. Two consecutive symbols in the 2*i th channel data stream and two consecutive symbols in the 2*i+1 th channel data stream are consecutive in the first data stream obtained by the group interleaving, and every four consecutive symbols in the first data stream obtained by the group interleaving come from four different codewords.

[0122] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by the group interleaving comes from the The first of 20 consecutive bits in the data stream of a channel bits, the represents rounding down, 0≤j<40, and β is 1, 2, 4, 5, 10 or 20.

[0123] In some possible implementations, t=2, s=1, and the group interleaver is specifically configured to: perform group interleaving on the 2*i th channel data stream and the 2*i+1 th channel data stream to obtain a first data stream, where 0≤i<16. A j-th group of β consecutive bits in the 2*i th channel data stream and a j-th group of β consecutive bits in the 2*i+1 th channel data stream are consecutive in the first data stream obtained by the group interleaving, where j≥0, β is 1, 2, 4, 5, 10, or 20, and each of four consecutive symbols in the first data stream obtained by the group interleaving comes from four different codewords.

[0124] In some possible implementations, t=2, s=2, and the group interleaver is specifically used to: group interleave the 2*i th channel data stream and the 2*i+1 th channel data stream to obtain the 2*i th first data stream and the 2*i+1 th first data stream, 0≤i<16. The 2 consecutive symbols in the 2*i-th channel data stream and the 2 consecutive symbols in the 2*i+1-th channel data stream, a total of 4 symbols, 5 bits of each symbol, a total of 20 bits, are continuous in the 2*i-th first data stream, and each of the 20 consecutive bits in the 2*i-th first data stream comes from 4 different codewords. The other 5 bits of each symbol in the 2*i-th channel data stream and the 2 consecutive symbols in the 2*i+1-th channel data stream, a total of 4 symbols, are continuous in the 2*i+1-th first data stream, and each of the 20 consecutive bits in the 2*i+1-th first data stream comes from 4 different codewords.

[0125] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0126] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0127] In some possible implementations, t=4, s=1, and the group interleaver is specifically used to: perform group interleaving on four channel data streams, namely the 4*i-th channel data stream, the 4*i+1-th channel data stream, the 4*i+2-th channel data stream, and the 4*i+3-th channel data stream, to obtain a first data stream, 0≤i≤7, and the consecutive 2 symbols, totaling 8 symbols, included in each of the four channel data streams are continuous in the first data stream obtained by the group interleaving, and every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, and the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords, respectively, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords, respectively.

[0128] In some possible implementations, t=4, s=1, and the group interleaver is specifically configured to: perform group interleaving on a 4*i-th channel data stream, a 4*i+1-th channel data stream, a 4*i+2-th channel data stream, and a 4*i+3-th channel data stream, a total of 4 channel data streams, to obtain a first data stream, 0≤i≤7, the j-th group of 2 consecutive symbols included in each of the 4 channel data streams, a total of 8 symbols, are continuous in the first data stream obtained by the group interleaving, and the j-th group of 2 consecutive symbols included in each of the 4 channel data streams are continuous in the first data stream obtained by the group interleaving. In the first data stream obtained by the group interleaving, j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0129] In some possible implementations, t=4, s=1, and the group interleaver is specifically used to: perform group interleaving on 4 channel data streams, namely the 4*i-th channel data stream, the 4*i+1-th channel data stream, the 4*i+2-th channel data stream, and the 4*i+3-th channel data stream, to obtain 1 first data stream, 0≤i≤7, the j-th symbol included in each of the 4 channel data streams, a total of 4 symbols, are continuous in the 1 first data stream obtained by the group interleaving, j≥0, and each 4 consecutive symbols in the 1 first data stream obtained by the group interleaving come from 4 different codewords.

[0130] In some possible implementations, t=8, s=1, and the group interleaver is specifically used to: perform group interleaving on 8 channel data streams, namely, the 8*i+1th channel data stream, the 8*i+2th channel data stream, the 8*i+3th channel data stream, the 8*i+4th channel data stream, the 8*i+5th channel data stream, the 8*i+6th channel data stream, and the 8*i+7th channel data stream, to obtain a first data stream, 0≤i≤3, and each of the 8 channel data streams includes 2 consecutive symbols, a total of 16 symbols, which are continuous in the first data stream obtained by the group interleaving, and each consecutive 16 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and each consecutive The 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively.

[0131] In some possible implementations, t=8, s=1, and the group interleaver is specifically used to: perform group interleaving on 8 channel data streams, namely, the 8*i+1th channel data stream, the 8*i+2th channel data stream, the 8*i+3th channel data stream, the 8*i+4th channel data stream, the 8*i+5th channel data stream, the 8*i+6th channel data stream, and the 8*i+7th channel data stream, to obtain 1 first data stream, 0≤i≤3, the jth group of 2 consecutive symbols, totaling 16 symbols, included in each of the 8 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, the jth group of 2 consecutive symbols included in each of the 8 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, j≥0, and the 1 first data stream obtained by the group interleaving is continuous. Every consecutive 16 symbols in the data stream come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords. The 0th symbol, 1st symbol, 2nd symbol and 3rd symbol of every consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively. The 4th symbol, 5th symbol, 6th symbol and 7th symbol of every consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively. The 8th symbol, 9th symbol, 10th symbol and 11th symbol of every consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively. The 12th symbol, 13th symbol, 14th symbol and 15th symbol of every consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively.

[0132] In some possible implementations, t=8, s=1, and the group interleaver is specifically configured to group and interleave eight channel data streams, namely, the 8*i-th channel data stream, the 8*i+1-th channel data stream, the 8*i+2-th channel data stream, the 8*i+3-th channel data stream, the 8*i+4-th channel data stream, the 8*i+5-th channel data stream, the 8*i+6-th channel data stream, and the 8*i+7-th channel data stream, to obtain a first data stream, 0≤i≤3, and each of the eight channel data streams includes the 8*i+1-th channel data stream. A total of 8 symbols, j symbols, are continuous in a first data stream obtained by the group interleaving, j≥0, each consecutive 8 symbols in the first data stream obtained by the group interleaving come from 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0133] In some possible implementations, n=32, the 16 consecutive channel data streams ordered first among the n channel data streams come from the same codeword, the 16 consecutive channel data streams ordered last among the n channel data streams come from the same codeword, and the 16 consecutive channel data streams ordered first and the 16 consecutive channel data streams ordered last among the n channel data streams come from different codewords.

[0134] In some possible implementations, t=2, s=1, and the group interleaver is specifically configured to: perform group interleaving on the i-th channel data stream and the i+16-th channel data stream to obtain a first data stream, where 0≤i<16. Two consecutive symbols in the i-th channel data stream and two consecutive symbols in the i+16-th channel data stream are consecutive in the first data stream obtained by the group interleaving, and each of the four consecutive symbols in the first data stream obtained by the group interleaving comes from four different codewords.

[0135] In some possible implementations, the jth bit of the 40 consecutive bits in the first data stream obtained by the group interleaving comes from the The first of 20 consecutive bits in the data stream of a channel bits, the represents rounding down, 0≤j<40, and β is 1, 2, 4, 5, 10 or 20.

[0136] In some possible implementations, t=2, s=1, and the group interleaver is specifically configured to: perform group interleaving on the i-th channel data stream and the i+16-th channel data stream to obtain a first data stream, where 0≤i<16. A j-th group of β consecutive bits in the i-th channel data stream and a j-th group of β consecutive bits in the i+16-th channel data stream are consecutive in the first data stream obtained by the group interleaving, where j≥0, β is 1, 2, 4, 5, 10, or 20, and each of four consecutive symbols in the first data stream obtained by the group interleaving comes from four different codewords.

[0137] In some possible implementations, t=2, s=2, and the group interleaver is specifically configured to: perform group interleaving on the i-th channel data stream and the i+16-th channel data stream to obtain the 2*i-th first data stream and the 2*i+1-th first data stream, where 0≤i<16. Five bits of each of four symbols, which are two consecutive symbols in the i-th channel data stream and two consecutive symbols in the i+16-th channel data stream, totaling 20 bits, are continuous in the 2*i-th first data stream, and each of the 20 consecutive bits in the 2*i-th first data stream comes from four different codewords. Another five bits of each of four symbols, which are two consecutive symbols in the i-th channel data stream and two consecutive symbols in the i+16-th channel data stream, totaling 20 bits, are continuous in the 2*i+1-th first data stream, and each of the 20 consecutive bits in the 2*i+1-th first data stream comes from four different codewords.

[0138] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0139] In some possible implementations, the fth bit in the 20 consecutive bits in the 2*i+gth first data stream comes from the The first of 20 consecutive bits in the data stream of a channel bits, 0≤f<20, 0≤g<2.

[0140] In some possible implementations, t=4, s=1, and the group interleaver is specifically used to: perform group interleaving on four channel data streams, namely the 2*i-th channel data stream, the 2*i+1-th channel data stream, the 2*i+16-th channel data stream, and the 2*i+17-th channel data stream, to obtain a first data stream, 0≤i≤7, and the consecutive 2 symbols, totaling 8 symbols, included in each of the four channel data streams are continuous in the first data stream obtained by the group interleaving, and every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, and the 0th symbol, the 1st symbol, the 2nd symbol, and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords, respectively, and the 4th symbol, the 5th symbol, the 6th symbol, and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords, respectively.

[0141] In some possible implementations, t=4, s=1, and the group interleaver is specifically used to: perform group interleaving on a 2*i-th channel data stream, a 2*i+1-th channel data stream, a 2*i+16-th channel data stream, and a 2*i+17-th channel data stream, a total of 4 channel data streams, to obtain a first data stream, 0≤i≤7, the j-th group of 2 consecutive symbols included in each of the 4 channel data streams, a total of 8 symbols, are continuous in the first data stream obtained by the group interleaving, and the j-th group of 2 consecutive symbols included in each of the 4 channel data streams Continuously in a first data stream obtained by the group interleaving, j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and every consecutive 272 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0142] In some possible implementations, t=4, s=1, and the group interleaver is specifically used to: perform group interleaving on 4 channel data streams, namely the 2*i-th channel data stream, the 2*i+1-th channel data stream, the 2*i+16-th channel data stream, and the 2*i+17-th channel data stream, to obtain 1 first data stream, 0≤i≤7, the j-th symbol included in each of the 4 channel data streams, a total of 4 symbols, are continuous in the 1 first data stream obtained by the group interleaving, j≥0, and each 4 consecutive symbols in the 1 first data stream obtained by the group interleaving come from 4 different codewords.

[0143] In some possible implementations, t=8, s=1, and the group interleaver is specifically configured to: perform group interleaving on 8 channel data streams, namely, the 4*i+1th channel data stream, the 4*i+2th channel data stream, the 4*i+3th channel data stream, the 4*i+16th channel data stream, the 4*i+17th channel data stream, the 4*i+18th channel data stream, and the 4*i+19th channel data stream, to obtain a first data stream, 0≤i≤3, and each of the 8 channel data streams includes 2 consecutive symbols, a total of 16 symbols, which are continuous in the first data stream obtained by the group interleaving, and each consecutive 16 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and each consecutive 16 symbols are from at least 4 different codewords, and each consecutive 16 symbols are from at least 4 different codewords. The consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively.

[0144] In some possible implementations, t=8, s=1, and the group interleaver is specifically used to: perform group interleaving on 8 channel data streams, namely, the 4*i+1th channel data stream, the 4*i+2th channel data stream, the 4*i+3th channel data stream, the 4*i+16th channel data stream, the 4*i+17th channel data stream, the 4*i+18th channel data stream, and the 4*i+19th channel data stream, to obtain 1 first data stream, 0≤i≤3, the jth group of 2 consecutive symbols, totaling 16 symbols, included in each of the 8 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, the jth group of 2 consecutive symbols included in each of the 8 channel data streams are continuous in the 1 first data stream obtained by the group interleaving, j≥0, and the 1 channel data stream obtained by the group interleaving is continuous. Every consecutive 16 symbols in the first data stream come from at least 4 different codewords, and every consecutive 544 symbols come from at least 4 different codewords. The 0th symbol, 1st symbol, 2nd symbol and 3rd symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively. The 4th symbol, 5th symbol, 6th symbol and 7th symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively. The 8th symbol, 9th symbol, 10th symbol and 11th symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively. The 12th symbol, 13th symbol, 14th symbol and 15th symbol of every consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0145] In some possible implementations, t=8, s=1, and the group interleaver is specifically configured to group interleave eight channel data streams, namely, the 4*i+1st channel data stream, the 4*i+2nd channel data stream, the 4*i+3rd channel data stream, the 4*i+16th channel data stream, the 4*i+17th channel data stream, the 4*i+18th channel data stream, and the 4*i+19th channel data stream, to obtain a first data stream, 0≤i≤3, and each of the eight channel data streams includes The j-th symbol, a total of 8 symbols, are continuous in a first data stream obtained by the group interleaving, j≥0, and each consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords. The 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in each consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

[0146] In some possible implementations, the convolution interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between each two adjacent delay lines is Q, each storage unit is used to store d symbols, the symbols in each channel data stream are input into the p delay lines in sequence according to the sequence numbers of the p delay lines, each delay line inputs d symbols at a time and outputs d symbols at a time, the consecutive p*d symbols in one of the second data streams include d symbols output by each delay line, and Q is an integer greater than or equal to 1.

[0147] In some possible implementations, the delay line with the largest sequence number among the p delay lines includes zero storage units, d(p*Q+1)≥L2, and L2=t / s*L1. Alternatively, the delay line with the smallest sequence number among the p delay lines includes zero storage units, d(p*Q-1)≥L2, and L2=t / s*L1.

[0148] In some possible implementations, the data processing apparatus further includes an encoder. After obtaining the m second data streams, the encoder is configured to: perform second FEC encoding on each of the m second data streams to obtain m coded data streams. Information data of length K symbols in each coded data stream comes from at most K different codewords, where K ≥ p*d.

[0149] In some possible implementations, the convolution interleaver is specifically used to: delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units of each two adjacent delay lines is Q, each storage unit is used to store 4 symbols, the symbols in each channel data stream are input into the p delay lines in sequence according to the sequence of the p delay lines, each delay line inputs 4 symbols at a time and outputs 4 symbols at a time, the consecutive p*4 symbols in a second data stream include 4 symbols output by each delay line, and Q satisfies 4(p*Q-1)≥272 or 4(p*Q+1)≥272 or 4(p*Q-1)≥544 or 4(p*Q+1)≥544.

[0150] In some possible implementations, the data processing device further includes an encoder. After obtaining m second data streams, the encoder is configured to: perform second FEC encoding on each of the m second data streams to obtain m coded data streams, wherein information data of a length of K symbols in each of the coded data streams comes from at most K different codewords, where K ≥ p*4.

[0151] In some possible implementations, the convolutional interleaver is specifically configured to delay a first data stream according to p delay lines to obtain a second data stream, where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between two adjacent delay lines is Q. Each storage unit is configured to store 34 bits, bits in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs 34 bits at a time and outputs 34 bits at a time, and the consecutive p*34 bits in the second data stream include the 34 bits output by each delay line; or each storage unit is configured to store 68 bits, bits in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs 68 bits at a time and outputs 68 bits at a time, and the consecutive p*68 bits in the second data stream include the 68 bits output by each delay line.

[0152] In some possible implementations, p=2, and each storage unit is used to store 68 bits; or, p=4, and each storage unit is used to store 34 bits.

[0153] In a seventh aspect, the present application provides a data processing method, comprising the following steps. First, n channel data streams are each delayed according to p delay lines to obtain n first data streams. Each of the n channel data streams undergoes a first forward error correction (FEC) encoding, wherein p is an integer greater than 1, each delay line comprises a different number of storage units, the delay line with the smallest number of storage units comprises 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is used to store U bits, the bits in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs U bits and outputs U bits at a time, and the consecutive p*U bits in one second data stream include the U bits output by each delay line, Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. Furthermore, the n first data streams are each subjected to a second FEC encoding to obtain n second data streams. The information data of each codeword in the second data stream after the second FEC encoding is p*U bits outputted by the p delay lines in a single pass.

[0154] In some possible embodiments, p*U=120, 136, or 160.

[0155] In an eighth aspect, the present application provides a data processing device comprising a convolutional interleaver and an encoder. The convolutional interleaver is configured to delay n channel data streams according to p delay lines to obtain n first data streams. The n channel data streams are all subjected to first forward error correction (FEC) encoding, wherein p is an integer greater than 1, each delay line comprises a different number of storage units, the delay line with the smallest number of storage units comprises 0 storage units, the difference in the number of storage units between two adjacent delay lines is Q, each storage unit is configured to store U bits, bits in each channel data stream are sequentially input into the p delay lines according to the sequence of the p delay lines, each delay line inputs U bits and outputs U bits at a time, and the consecutive p*U bits in one second data stream comprise the U bits output by each delay line, Q is an integer greater than or equal to 1, and U is an integer greater than or equal to 1. The encoder is configured to perform second FEC encoding on each of the n first data streams to obtain n second data streams. The information data of each codeword in the second data stream after the second FEC encoding is p*U bits outputted by the p delay lines in a single pass.

[0156] In some possible embodiments, p*U=120, 136, or 160.

[0157] In the ninth aspect, the present application provides a computer-readable storage medium, which stores a computer program, wherein the computer program, when executed by hardware, can implement part or all of the steps of any one of the methods in the first, third, fifth or seventh aspects above.

[0158] In an embodiment of the present application, the n-channel data streams are all codeword streams after outer code encoding. The n-channel data streams are subjected to convolution interleaving processing respectively, and the n-channel data streams after convolution interleaving are multiplexed into m-channel second data streams, which are then subjected to inner code encoding. By adopting the data interleaving and multiplexing processing scheme provided by the present application, it is possible to achieve the multiple symbols of the multiplexed m-channel data streams in the continuous output from multiple different outer code words with a shorter delay, so that the cascade FEC scheme can help reduce the delay of data interleaving while ensuring better performance. In other words, the scheme of combining convolution interleaving processing with data multiplexing in the present application makes the overall delay of the cascade FEC scheme lower, which is more suitable for application scenarios requiring low delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0159] Figure 1 A schematic diagram of a communication system used in an embodiment of the present application;

[0160] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown;

[0161] FIG3( a ) is a schematic diagram of a first data processing method of a transmitting end processing module in an embodiment of the present application;

[0162] FIG3( b ) is a schematic diagram of a second data processing method of the transmitting end processing module in an embodiment of the present application;

[0163] FIG3( c ) is a schematic diagram of a third data processing method of the transmitting end processing module in an embodiment of the present application;

[0164] FIG3( d ) is a fourth data processing diagram of the transmitting end processing module in an embodiment of the present application;

[0165] FIG3( e ) is a schematic diagram of channel data alignment processing in an embodiment of the present application;

[0166] FIG3( f ) is a schematic diagram of a fifth data processing method of the transmitting end processing module in an embodiment of the present application;

[0167] FIG3( g ) is a sixth data processing diagram of the transmitting end processing module in an embodiment of the present application;

[0168] FIG3(h) is a schematic diagram of the seventh data processing of the transmitting end processing module in an embodiment of the present application;

[0169] FIG3(i) is a schematic diagram of an eighth data processing method of the transmitting end processing module in an embodiment of the present application;

[0170] FIG4( a ) is a schematic diagram of a first data processing method for a receiving end processing module in an embodiment of the present application;

[0171] FIG4( b ) is a schematic diagram of a second data processing method for a receiving end processing module in an embodiment of the present application;

[0172] FIG4( c ) is a schematic diagram of a third data processing method for a receiving end processing module in an embodiment of the present application;

[0173] Figure 5 Schematic diagram of 32 PCS lanes of data flow using a 1×800G interface on the transmitting device;

[0174] Figure 6 Schematic diagram of 32 PCS lanes of data flow using 2×400G interfaces on the transmitting device;

[0175] Figure 7 Schematic diagram of 32 PCS lanes of data flow using a 4×200G interface on the transmitting device;

[0176] Figure 8A schematic diagram of 32 FEC channel data flows using 8×100G interfaces on the transmitting device;

[0177] Figure 9 Another diagram of 32 FEC lanes of data flow using 8x100G interfaces at the transmitting device;

[0178] Figure 10 A flowchart of a data processing method provided in an embodiment of the present application;

[0179] Figure 11 This is a structural diagram of performing convolution interleaving on n channel data streams in an embodiment of the present application;

[0180] FIG12( a ) is a schematic diagram of a first structure of a convolutional interleaver in an embodiment of the present application;

[0181] FIG12( b ) is a schematic diagram of a second structure of a convolutional interleaver in an embodiment of the present application;

[0182] Figure 13 This is a structural diagram of multiplexing n first data streams in an embodiment of the present application;

[0183] Figure 14 This is a schematic diagram of the first structure of the multiplexer in the embodiment of the present application;

[0184] Figure 15 This is a structural diagram of performing FEC encoding on m second data streams in an embodiment of the present application;

[0185] FIG16( a ) is a schematic diagram of a third structure of a convolutional interleaver in an embodiment of the present application;

[0186] FIG16( b ) is a schematic diagram of a fourth structure of a convolutional interleaver in an embodiment of the present application;

[0187] FIG17( a ) is a schematic diagram of a second structure of a multiplexer in an embodiment of the present application;

[0188] FIG17( b ) is a schematic diagram of a third structure of a multiplexer in an embodiment of the present application;

[0189] FIG17( c ) is a schematic diagram of a fourth structure of a multiplexer in an embodiment of the present application;

[0190] FIG18( a ) is a schematic diagram of a fifth structure of a convolutional interleaver according to an embodiment of the present application;

[0191] FIG18( b ) is a schematic diagram of a sixth structure of a convolutional interleaver in an embodiment of the present application;

[0192] FIG19( a ) is a schematic diagram of a seventh structure of a convolutional interleaver according to an embodiment of the present application;

[0193] FIG19( b ) is a schematic diagram of an eighth structural embodiment of a convolutional interleaver according to an embodiment of the present application;

[0194] Figure 20 This is a ninth structural diagram of a convolutional interleaver according to an embodiment of the present application;

[0195] Figure 21 This is a schematic diagram of the tenth structure of the convolutional interleaver in an embodiment of the present application;

[0196] Figure 22 This is a fifth structural diagram of the multiplexer in the embodiment of the present application;

[0197] Figure 23 This is a schematic diagram of the eleventh structure of the convolutional interleaver in an embodiment of the present application;

[0198] Figure 24 This is a sixth structural diagram of the multiplexer in the embodiment of the present application;

[0199] Figure 25 This is a twelfth structural diagram of the convolutional interleaver in an embodiment of the present application;

[0200] Figure 26 This is a thirteenth structural diagram of a convolutional interleaver in an embodiment of the present application;

[0201] FIG27( a ) is a schematic diagram of the fourteenth structure of a convolutional interleaver according to an embodiment of the present application;

[0202] FIG27( b ) is a schematic diagram of the fifteenth structure of the convolutional interleaver in an embodiment of the present application;

[0203] FIG28( a ) is a schematic diagram of the sixteenth structure of a convolutional interleaver according to an embodiment of the present application;

[0204] FIG28( b ) is a schematic diagram of the seventeenth structure of the convolutional interleaver in an embodiment of the present application;

[0205] FIG29( a ) is a schematic diagram of the eighteenth structure of a convolutional interleaver according to an embodiment of the present application;

[0206] FIG29( b ) is a schematic diagram of the nineteenth structure of the convolutional interleaver in an embodiment of the present application;

[0207] FIG30( a ) is a schematic diagram of the twentieth structure of a convolutional interleaver according to an embodiment of the present application;

[0208] FIG30( b ) is a schematic diagram of the twenty-first structure of the convolutional interleaver in an embodiment of the present application;

[0209] FIG31( a ) is a schematic diagram of the twenty-second structure of a convolutional interleaver according to an embodiment of the present application;

[0210] FIG31( b ) is a schematic diagram of the twenty-third structure of a convolutional interleaver in an embodiment of the present application;

[0211] FIG32( a ) is a schematic diagram of a structure for performing group interleaving on n first data streams in an embodiment of the present application;

[0212] FIG32( b ) is a schematic diagram of a structure of a packet interleaver according to an embodiment of the present application;

[0213] Figure 33 A schematic diagram of the structure of a data processing device in an embodiment of the present application;

[0214] Figure 34 A schematic diagram of a flow chart of the interleaving process provided in an embodiment of the present application;

[0215] Figure 35 This is a structural diagram of grouping and interleaving n first data streams in an embodiment of the present application;

[0216] Figure 36 A schematic diagram of an implementation method for group interleaving in an embodiment of the present application;

[0217] Figure 37 This is a diagram of the data stream format after lane alignment when the client-side interface is 2×400GbE.

[0218] Figure 38 Schematic diagram of an implementation method of group interleaving;

[0219] Figure 39 Schematic diagram of another implementation method of group interleaving;

[0220] Figure 40 Schematic diagram of another implementation method of group interleaving;

[0221] Figure 41 Schematic diagram of another implementation method of group interleaving;

[0222] Figure 42 Another schematic diagram of the interleaving process provided in an embodiment of the present application;

[0223] Figure 43 This is a schematic diagram of an implementation method for performing first group interleaving in an embodiment of the present application;

[0224] FIG44( a ) is a schematic diagram of an implementation method of performing second group interleaving in an embodiment of the present application;

[0225] FIG44( b ) is a schematic diagram of a specific implementation method of performing the second group interleaving in an embodiment of the present application;

[0226] FIG45( a ) is a schematic diagram illustrating an implementation of first group interleaving;

[0227] FIG45( b ) is a schematic diagram of an implementation of convolutional interleaving;

[0228] FIG45( c ) is a schematic diagram of another implementation of convolutional interleaving;

[0229] FIG45( d ) is a schematic diagram illustrating an implementation of the second group interleaving;

[0230] FIG46( a ) is a schematic diagram of another implementation of convolutional interleaving;

[0231] FIG46( b ) is a schematic diagram of another implementation of convolutional interleaving;

[0232] FIG46( c ) is a schematic diagram of another implementation of the second group interleaving;

[0233] Figure 47 A schematic diagram of another implementation method of second group interleaving;

[0234] Figure 48 A schematic diagram of another implementation method of second group interleaving;

[0235] Figure 49 A schematic diagram of another implementation method of first group interleaving;

[0236] FIG50( a ) is another schematic diagram of the structure of a data processing device according to an embodiment of the present application;

[0237] FIG50( b ) is another schematic structural diagram of a data processing device according to an embodiment of the present application;

[0238] Figure 51 Another flowchart of the data processing method provided in the embodiment of the present application;

[0239] Figure 52 This is a schematic diagram of a structure for grouping and interleaving n channel data streams in an embodiment of the present application;

[0240] Figure 53 This is a schematic diagram of an application scenario of group interleaving in an embodiment of the present application;

[0241] Figure 54 Schematic diagrams of several specific embodiments of group interleaving in the embodiments of the present application;

[0242] Figure 55 This is a schematic diagram of another application scenario of group interleaving in an embodiment of the present application;

[0243] Figure 56 Schematic diagrams of several specific embodiments of group interleaving in the embodiments of the present application;

[0244] Figure 57 This is a schematic diagram of another application scenario of group interleaving in an embodiment of the present application;

[0245] Figure 58 This is a schematic diagram of another application scenario of group interleaving in an embodiment of the present application;

[0246] Figure 59 This is a schematic diagram of another application scenario of group interleaving in an embodiment of the present application;

[0247] Figure 60 This is a schematic diagram of another application scenario of group interleaving in an embodiment of the present application;

[0248] Figure 61 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0249] Figure 62 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0250] Figure 63 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0251] Figure 64 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0252] Figure 65 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0253] Figure 66 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0254] Figure 67 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0255] Figure 68 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0256] Figure 69 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0257] Figure 70 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0258] Figure 71 This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0259] Figure 72This is a schematic diagram of another application scenario of group interleaving in the embodiment of the present application;

[0260] Figure 73 This is a structural diagram of performing convolution interleaving on m first data streams in an embodiment of the present application;

[0261] Figure 74 This is a schematic diagram of an embodiment of a convolutional interleaver in an embodiment of the present application;

[0262] Figure 75 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0263] Figure 76 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0264] Figure 77 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0265] Figure 78 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0266] Figure 79 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0267] Figure 80 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0268] Figure 81 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0269] Figure 82 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0270] Figure 83 This is a schematic diagram of another embodiment of a convolutional interleaver in an embodiment of the present application;

[0271] Figure 84 This is a schematic diagram of an implementation method of internal code encoding in an embodiment of the present application;

[0272] Figure 85 A schematic diagram of the structure of a data processing device in an embodiment of the present application;

[0273] Figure 86 Another flowchart of the data processing method provided in the embodiment of the present application;

[0274] Figure 87 This is another structural diagram of the data processing device in an embodiment of the present application;

[0275] Figure 88 This is another structural diagram of the data processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0276] The embodiments of the present application provide a data processing method and apparatus. These methods can achieve better performance of a cascaded FEC scheme in scenarios with lower latency. It should be noted that the terms "first," "second," and so on, in the specification, claims, and accompanying figures of this application are used to distinguish similar objects, rather than to define a specific order or precedence. It should be understood that the above terms are interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not necessarily limited to the steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to the process, method, product, or apparatus.

[0277] Figure 1 This is a schematic diagram of a communication system used in the embodiment of the present application. Figure 1 As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, transmitting device 01 and receiving device 05 can be devices such as switches or routers. Transmitting device 01 is also called a host chip at the transmitting end, while receiving device 05 is also called a host chip at the receiving end. Channel transmission medium 03 can be an optical fiber. The host chip is sometimes also called a host device. Transmitting device 01 and transmitting processing module 02 can be connected via an attachment unit interface (AUI), and receiving device 05 and receiving processing module 04 can be connected via an AUI. Transmitting processing module 02 and receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during transmission. For example, the processing module can be an 800LR module (a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04 and receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not specifically limited here.

[0278] Figure 2 for Figure 1The diagram below shows a process diagram of data transmission in a communication system. Figure 2 As shown, during data transmission from a transmitting device 01 to a receiving device 05, the transmitting device 01 is configured to perform outer code encoding on the data and then transmit the outer-coded data to the transmitting processing module 02. The transmitting processing module 02 is configured to perform inner code encoding on the outer-coded data to obtain outer-coded and inner-coded data, and then transmit the outer-coded and inner-coded data to the channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer-coded and inner-coded data to the receiving processing module 04. The receiving processing module 04 is configured to perform inner code decoding on the outer-coded and inner-coded data and then transmit the inner-coded data to the receiving device 05. The receiving device 05 is configured to perform outer code decoding on the inner-coded data.

[0279] It should be understood that the distinction between "inner" in inner code and "outer" in outer code is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity performing the inner code operation is closer to the channel transmission medium, while the entity performing the outer code operation is farther away. In the embodiment of the present application, after data is transmitted from transmitting device 01, it passes through transmitting processing module 02 to channel transmission medium 03, and then from channel transmission medium 03 to receiving device 05 via receiving processing module 04. The data encoded by transmitting device 01 is farther from channel transmission medium 03 than the data encoded by transmitting processing module 02, and the data decoded by receiving device 05 is farther from channel transmission medium 03 than the data decoded by receiving processing module 04. Therefore, data encoded by transmitting device 01 is referred to as data encoded with an outer code, data encoded by transmitting processing module 02 is referred to as data encoded with an inner code, data decoded by receiving device 05 is referred to as data decoded with an outer code, and data decoded by receiving processing module 04 is referred to as data decoded with an inner code. In one possible implementation, both the inner and outer codes described above employ FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the transmitting device 01 may employ Reed-Solomon (RS) code for outer code encoding, and the transmitting processing module 02 may employ Hamming code for inner code encoding. For another example, the transmitting device 01 may employ RS code for outer code encoding, and the transmitting processing module 02 may employ Bose–Chaudhuri–Hocquenghem (BCH) code for inner code encoding.

[0280] It should be noted that the above content is an illustrative description of the application scenarios of the data interleaving method provided in the embodiments of the present application, and does not constitute a limitation on the application scenarios of the data interleaving method. A person skilled in the art will know that as business needs change, its application scenarios can be adjusted according to application needs, and the embodiments of the present application do not list them one by one.

[0281] For the aforementioned transmission scheme using cascaded FEC, this application designs a data processing scheme that incorporates "convolutional interleaving" and "multiplexing" to achieve superior performance and low latency for the overall cascaded FEC scheme. This allows the cascaded FEC transmission scheme to be applied to a wide range of transmission scenarios, particularly those requiring low latency, such as low-latency data center interconnection. Data processing is implemented by the aforementioned transmitting end processing module 02.

[0282] Figure 3(a) is a schematic diagram of the first data processing method of the transmitting processing module in an embodiment of the present application. As shown in Figure 3(a), the Physical Medium Attachment (PMA) sublayer of the transmitting processing module processes data from multiple synchronized client lanes to obtain n outer-code encoded Physical Coding Sublayer (PCS) or FEC channel data streams. Alignment lock and channel data alignment are then performed to obtain n aligned channel data streams. Lane reordering is then performed on the n channel data according to the alignment markers, so that the n channel data are arranged in a specified order. The n channel data streams, after lane reordering, are sent to a designed processor including convolutional interleaving and muxing to scramble the data order and then to an inner code encoder for inner code encoding. The inner-code encoded data streams are then processed and sent to the channel transmission medium for transmission. The data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc., wherein n is a positive integer greater than 1.

[0283] Figure 3(b) illustrates a second data processing scheme for the transmitting end processing module in an embodiment of the present application. As shown in Figure 3(b), in some practical application scenarios, the n channel data streams aligned after channel data alignment already meet a specified order. In this case, no further channel reordering is required. Instead, the aligned n channel data streams are directly fed into a designed processor that includes convolutional interleaving and multiplexing for interleaving, disrupting the data order, and then fed into an inner code encoder for inner code encoding.

[0284] It should be understood that in some possible implementations, different from the data processing flow described in FIG3(a) and FIG3(b) above, the n channel data streams aligned after the channel data alignment processing may also be directly multiplexed without undergoing convolution interleaving and sent to the inner code encoder for inner code encoding.

[0285] Figure 3(c) is a schematic diagram of the third data processing method of the transmitting end processing module in the embodiment of the present application. As shown in Figure 3(c), unlike the data processing flow shown in Figure 3(a), the n channel data streams after channel reordering are not convolutionally interleaved, but are directly multiplexed and sent to the inner code encoder for inner code encoding.

[0286] Figure 3(d) is a schematic diagram of the fourth data processing step in the transmitting end processing module according to an embodiment of the present application. As shown in Figure 3(d), unlike the data processing flow shown in Figure 3(b), the n channel data streams after channel data alignment are directly multiplexed without undergoing convolution interleaving and fed into the inner code encoder for inner code encoding.

[0287] Figure 3(e) is a schematic diagram of the channel data alignment process in an embodiment of the present application. It should be understood that the above-mentioned "channel data alignment process" can be a lane de-skew process defined by existing standards, so that the data of the n channel data streams outputted are completely aligned. Alternatively, the above-mentioned "channel data alignment process" can be simply channel symbol alignment, so that the data on the n channel data streams outputted are aligned based on outer code symbols, specifically alignment based on a single outer code symbol or alignment based on multiple outer code symbols. Figure 3(e) illustrates the specific operation of the above-mentioned "channel data alignment process" using two channel data streams as an example, assuming that the outer code is an RS code and that an RS code symbol is 10 bits long. Scenario (a) in Figure 3(e) shows that the two channel data streams are 75 bits apart, with AM0 and AM1 being the alignment identifiers for channel data stream 0 and channel data stream 1, respectively. Scenario (b) in Figure 3(e) uses lane de-skew process defined by existing standards, so that the outputted channel data streams 0 and 1 are free of deviation. Scenario (c) in Figure 3(e) uses alignment based on one RS symbol, so that the RS symbol of channel data stream 0 and the RS symbol of channel data stream 1 are aligned after output. At this time, there is still a 70-bit offset between the two channels. Scenario (d) in Figure 3(e) uses alignment based on two RS symbols, so that the RS symbols of channel data stream 0 and the RS symbols of channel data stream 1 are aligned after output. At this time, there is still a 60-bit offset between the two channels.

[0288] Figure 3(f) is a schematic diagram of the fifth data processing method of the transmitting end processing module in an embodiment of the present application. As shown in Figure 3(f), the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes data from multiple synchronous client lanes to obtain n outer-code encoded Physical Coding Sublayer (PCS) or FEC channel data streams. Alignment lock and channel data alignment are then performed to obtain n aligned channel data streams. Lane reordering is then performed on the n channel data according to the alignment markers, so that the n channel data are arranged in a specified order. The n channel data streams, after lane reordering, are fed into a designed processor including convolutional interleaving and block interleaving to scramble the data order and then fed into an inner code encoder for inner code encoding. After data processing, the inner-code encoded data streams are fed into the channel transmission medium for transmission. The data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing, etc., wherein n is a positive integer greater than 1.

[0289] Figure 3(g) is a schematic diagram of the sixth data processing method of the transmitting processing module in an embodiment of the present application. As shown in Figure 3(g), the Physical Medium Attachment (PMA) sublayer of the transmitting processing module processes data from multiple synchronized client lanes to obtain n outer-code encoded Physical Coding Sublayer (PCS) or FEC channel data streams, collectively referred to as channel data streams. Alignment lock and channel data alignment are then performed to obtain n aligned channel data streams. Lane reordering is then performed on the n channel data according to the alignment markers, so that the n channel data are arranged in a specified order. The n channel data streams, after lane reordering, are fed into a designed processor comprising a first block interleaving, a convolutional interleaving, and a second block interleaving for interleaving to disrupt the data order, and then fed into an inner code encoder for inner code encoding. After data processing, the inner-code encoded data streams are fed into a channel transmission medium for transmission. The data processing may include modulation mapping (maPPing), channel interleaving (channel interleaving), polarization distribution (Polarization distribution) or DSP framing (Framing), etc., wherein n is a positive integer greater than 1.

[0290] FIG3(h) is a seventh data processing diagram of the transmitting end processing module in an embodiment of the present application. As shown in FIG3(h), after the Physical Medium Attachment (PMA) sublayer of the transmitting end processing module processes the data from multiple synchronous client lanes, n Physical Coding Sublayer (PCS) or FEC channel data streams encoded with an outer code can be obtained, and alignment lock (alignment lock) and channel data alignment processing are performed to obtain n aligned channel data streams. Then, lane reordering (lane reordering) is performed on the data of the n channels according to the alignment marker, so that the data of the n channels can be arranged in a specified order. The n channel data streams after channel reordering are sent to the designed block interleaving (block

[0291] The data stream is processed by a processor that performs convolutional interleaving and interleaving, disrupting the data order, and then fed into an inner code encoder for inner code encoding. The inner code-encoded data stream undergoes data processing and is then fed into a channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing. Here, n is a positive integer greater than 1.

[0292] Figure 3(i) is a schematic diagram of the eighth data processing method of the transmitting processing module in an embodiment of the present application. As shown in Figure 3(i), the Physical Medium Attachment (PMA) sublayer of the transmitting processing module processes data from n synchronous client lanes, such as the AUI-n interface, to obtain n outer-code encoded channel data streams. The PMA sublayer only needs to perform signal recovery operations such as clock data recovery (CDR) and PAM4 symbol demodulation on the data from each client channel to obtain a single channel data stream, eliminating the need for other complex operations such as AM locking, channel de-skew, and channel reordering. The n channel data streams are fed into a designed processor including convolutional interleaving for interleaving and disrupting the data order, and then fed into an inner code encoder for inner code encoding. After data processing, the inner-code encoded data streams are fed into the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing. Here, n is a positive integer greater than 1.

[0293] It should be understood that in some practical application scenarios, the RS outer code is encoded by two encoders and then interleaved, such as by using two-way interleavering, so that the RS symbols on the channel data stream with an even sequence number are transmitted according to "ABABAB...", and the RS symbols on the channel data stream with an odd sequence number are transmitted according to "BA BA BA...", where A and B are two RS symbols generated by different encoders. For the alignment process based on two RS symbols, one implementation effect is that the RS symbols on the channel data stream with all even sequence numbers at the same time are generated by the same encoder and the RS symbols on the channel data stream with all odd sequence numbers are generated by another identical encoder; another implementation effect is that the RS symbols on all channel data streams at the same time are generated by the same encoder. The specific method is not limited here.

[0294] Figure 4(a) is a schematic diagram of the first data processing method for the receiving processing module in an embodiment of the present application. As shown in Figure 4(a), the receiving processing module receives a data stream from the channel transmission medium. When the data stream of the transmitting processing module undergoes data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the receiving processing module first performs the corresponding data inverse processing before sending it to the inner code decoder for decoding. After inner code decoding, the data stream is sent to the convolutional deinterleaving and demultiplexing processor to obtain n channel data streams, which are then sent to the PMA sublayer. The PMA sublayer processes the data stream and sends it to the receiving device for outer code decoding. Here, the convolutional deinterleaving and demultiplexing processing in the receiving processing module are the inverse operations of the convolutional interleaving and multiplexing processing in the transmitting processing module. Convolutional deinterleaving is the inverse operation of convolutional interleaving in the transmitting processing module, and demultiplexing is the inverse operation of multiplexing in the transmitting processing module. The following describes the convolutional interleaving and multiplexing processing in the transmitting end processing module in detail. The convolutional deinterleaving and demultiplexing processing in the receiving end processing module is the inverse of the convolutional interleaving and multiplexing processing in the transmitting end processing module, as shown in Figures 3(a) and 3(b). Those skilled in the art will appreciate this and will not be described in detail here.

[0295] Figure 4(b) is a schematic diagram of the second data processing method for the receiving processing module in an embodiment of the present application. As shown in Figure 4(b), the receiving processing module receives a data stream from the channel transmission medium. When the data stream of the transmitting processing module undergoes data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the receiving processing module first performs the corresponding data inverse processing before sending it to the inner code decoder for decoding. After inner code decoding, the data stream is sent to the depacketized interleaver and deconvolution interleaver processor to obtain n channel data streams, which are then sent to the PMA sublayer. The PMA sublayer processes the data stream and sends it to the receiving device for outer code decoding. The depacketized interleaver and deconvolution interleaver processing in the receiving processing module are the inverse operations of the packetized interleaver and convolution interleaver processing in the transmitting processing module shown in Figure 3(f). Deconvolution interleaver is the inverse operation of convolution interleaver in the transmitting processing module, and depacketized interleaver is the inverse operation of packetized interleaver in the transmitting processing module.

[0296] Figure 4(c) illustrates the third data processing scheme for the receiving processing module in an embodiment of the present application. As shown in Figure 4(c), the receiving processing module receives a data stream from a channel transmission medium. When the data stream from the transmitting processing module undergoes data processing such as modulation mapping, channel interleaving, polarization distribution, or DSP framing, the receiving processing module first performs the corresponding data inverse processing before sending it to the inner code decoder for decoding. After inner code decoding, the data stream is sent to the de-second block interleaving, de-convolution interleaving, and de-first block interleaving processes to obtain n channel data streams, which are then sent to the PMA sublayer. The PMA sublayer processes the data streams and sends them to the receiving device for outer code decoding. The de-first block interleaving, de-convolution interleaving, and de-second block interleaving processes in the receiving processing module are the inverse operations of the first block interleaving, convolution interleaving, and second block interleaving processes in the transmitting processing module, respectively, as shown in Figure 3(g). The first block interleaving, convolution interleaving, and second block interleaving processes in the transmitting processing module are described in detail below. The first group deinterleaving, convolution deinterleaving and second group deinterleaving in the receiving end processing module are the inverse operations of the first group interleaving, convolution deinterleaving and second group interleaving in the transmitting end processing module, which are known to ordinary technicians in this field and will not be repeated here.

[0297] The following first provides several specific scenarios in which the embodiments of the present application can be applied. It should be noted that, for ease of introduction, the following specific scenarios are described using "channel data alignment processing" using channel deflection processing as an example.

[0298] Figure 5 The following is a diagram of the data flow of 32 PCS channels using a 1×800G interface on the transmitting device. Figure 5 As shown, the transmitting device performs KP4 RS (544, 514) outer code encoding on one 800GbE service data stream to be transmitted, resulting in 32 PCS lane data streams. PCS lane data streams 0-15 are separated by 68 symbols, totaling 16*68=1088 symbols, which contain two RS codewords. Two adjacent symbols in each PCS lane data stream come from different RS codewords, and the two symbols at the same position in two adjacent PCS lane data streams come from different RS codewords. Similarly, PCS lane data streams 16-31 are separated by 68 symbols, totaling 16*68=1088 symbols, which contain two RS codewords. Two adjacent symbols in each PCS lane data stream come from different RS codewords, and the two symbols at the same position in two adjacent PCS lane data streams come from different RS codewords. The 32 PCS channel data streams are processed by the PMA and then sent to the transmitting end processing module through the connection unit interface 800GAUI-8.

[0299] Based on the data processing diagram of the transmitting end processing module shown in Figure 3(a) above, the transmitting end processing module uses the known alignment marker of the PCS channel to perform alignment lock on the channel data stream. The known alignment markers of the 32 channels here are different (see "Ethernet Technology Consortium 800G Specification"). The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, lane reordering processing is performed on the data of n=32 channels according to the alignment marker, so that the data of n=32 channels can be arranged in the specified order. One order is to follow Figure 5 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0300] Figure 6 The diagram below shows the data flow of 32 PCS channels using 2×400G interfaces on the transmitting device. Figure 6As shown, the transmitting device performs KP4 RS (544, 514) outer encoding on two 400GbE service data streams to be transmitted, resulting in two PCS channel data streams totaling 32, each of which contains 16 PCS channel data streams. Each data stream in PCS channel data streams 0-15 or PCS channel data streams 16-31 is separated by 68 symbols, totaling 16*68=1088 symbols, which contain two RS codewords. Adjacent symbols in each PCS channel data stream come from different RS codewords, and two symbols at the same position in two adjacent PCS channel data streams come from different RS codewords. After PMA processing, the 32 PCS channel data streams are sent to the transmitting processing module via the connection unit interface 2×400GAUI-4.

[0301] Based on the data processing diagram of the transmitting end processing module shown in Figure 3(a), the transmitting end processing module uses the known alignment markers of PCS lanes 0-15 or PCS lanes 16-31 to perform alignment lock on the 16-lane data streams. Here, PCS lanes 0-15 can be considered to be PCS lanes 0-15 in 400G lane 0, and PCS lanes 16-31 can be considered to be PCS lanes 0-15 in 400G lane 1. The known alignment markers of the 16 lanes in 400G lane 0 are the same as the known alignment markers of the 16 lanes in 400G lane 1. The transmitting end processing module then performs lane de-skew processing on the 32-lane data streams to obtain aligned 32-lane data streams. Lane reordering is then performed on the 16 lanes of data based on the alignment markers of PCS lanes 0-15 or PCS lanes 16-31, ensuring that the 16 lanes of data are arranged in the specified order. Finally, the data of the 32 lanes is arranged in the specified order. One order is to follow Figure 6 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0302] Figure 7 The diagram below shows the data flow of 32 PCS channels using a 4×200G interface on the transmitting device. Figure 7As shown, the transmitting device performs KP4 RS (544,514) outer encoding on four 200GbE service data streams to be transmitted, resulting in four PCS channel data streams totaling 32, each of which consists of eight PCS channel data streams. Each data stream in PCS channel data streams 0-7, PCS channel data streams 8-15, PCS channel data streams 16-23, or PCS channel data streams 24-31 is separated by 136 symbols, totaling 8*136=1088 symbols, which contain two RS codewords. Adjacent symbols in each PCS channel data stream come from different RS codewords, and two symbols at the same position in two adjacent PCS channel data streams come from different RS codewords. After PMA processing, the 32 PCS channel data streams are sent to the transmitting processing module via the connection unit interface 4×200GAUI-2.

[0303] Based on the data processing diagram of the transmitting end processing module shown in Figure 3(a), the transmitting end processing module uses the known alignment markers of PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31 to perform alignment lock on the eight lane data streams. Here, PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31 can be considered to be PCS lanes 0-7 in the 0th, 1st, 2nd, or 3rd 200G lane, respectively. The transmitting end processing module then performs lane de-skew on the 32 lane data streams to obtain the 32 aligned lane data streams. Lane reordering is then performed on the eight lanes of data based on the alignment markers of PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31, ensuring that the eight lanes of data are arranged in the specified order. Finally, the data of 32 channels can be arranged in the specified order. One order is to follow Figure 7 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0304] Figure 8 The following is a schematic diagram of 32 FEC channel data flows using 8×100G interfaces on the transmitting device. Figure 8As shown, the transmitting device performs KP4 RS (544,514) outer encoding on eight 100GbE service data streams to be transmitted, resulting in eight FEC lane data streams totaling 32, each of which includes four FEC lane data streams. When using the "100G RS-FEC-Int" mode with two KP4 RS (544,514) codewords interleaved, each data stream in FEC lane data streams 0-3, FEC lane data streams 4-7, FEC lane data streams 8-11, FEC lane data streams 12-15, FEC lane data streams 16-19, FEC lane data streams 20-23, FEC lane data streams 24-27, or FEC lane data streams 28-31 is separated by 272 symbols, for a total of 4*272=1088 symbols, which contain two RS codewords. The two adjacent symbols in each FEC channel data stream come from different RS codewords, and the two symbols at the same position in two adjacent FEC channel data streams come from different RS codewords. After being processed by the PMA, the 32 FEC channel data streams are sent to the transmitting end processing module through the connection unit interface 8×100GAUI-1.

[0305] Figure 9 Another diagram of 32 FEC channel data flows using 8×100G interfaces on the transmitting device. Figure 9 As shown, different from the above Figure 8 In this scenario, the transmitting device uses the 100G RS-FEC mode. Each data stream in FEC channel data streams 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 is separated by 136 symbols, for a total of 4*136=544 symbols, which comprise one RS codeword. After PMA processing, these 32 FEC channel data streams are sent to the transmitting processing module via the connection unit interface 8×100GAUI-1.

[0306] Based on the data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module uses the known alignment markers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 to perform alignment lock on the four data streams. Here, FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, according to the alignment identifiers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27 or FEC channels 28-31, the data of the four channels are subjected to lane reordering processing so that the data of the four channels can be arranged in the specified order. Finally, the data of the 32 channels can be arranged in the specified order. One order is to follow Figure 8 and Figure 9 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0307] Figure 10 A flowchart of a data processing method provided in an embodiment of the present application.

[0308] 1001. Perform convolution interleaving on n channel data streams to obtain n first data streams.

[0309] In this embodiment, the channel data stream may be a PCS channel data stream or an FEC channel data stream, which is not specifically limited here. The n channel data streams are all data streams that have undergone the first FEC encoding, that is, the data streams that have undergone outer code encoding as described above, where n is an integer greater than 1. For example, the outer code encoding may adopt RS code, and the n data streams after outer code encoding may include multiple RS code words. In practical applications, other encoding methods may also be used for outer code encoding. For ease of description, RS code words are uniformly used below to represent the code words generated after outer code encoding. It should be understood that each a code words after outer code encoding are distributed in b channel data streams, where a≤b≤n, n is divisible by b, and a is an integer greater than or equal to 1. In the above Figure 5-Figure 9In different application scenarios shown in FIG, the values ​​of a and b may also be different. Figure 5 Taking the application scenario shown in the figure as an example, n=32, a=2, b=16, that is, every 2 code words are distributed in 16 channel data streams. Figure 6-Figure 9 The values ​​of a and b in several other application scenarios can be derived from the accompanying drawings and will not be described in detail here. It should be noted that the outer code length in this application is calculated in symbols, where a symbol can include one or more bits. For example, the outer code is the KP4 RS (544, 514) code, with a code length of N = 544 symbols, and one symbol contains 10 bits.

[0310] As an example, when a=1, it means that the codewords encoded by the outer code at the transmitting device 01 are not interleaved and are directly distributed in the b channel data streams. Figure 9 As shown, a=1, the codeword of N=544 symbols encoded by the outer code KP4 at the transmitting device 01 is not interleaved and is directly distributed in b=4 channel data streams. Figure 9 The 544 symbols in one dotted frame shown in are from the same KP4 code word, and in each dotted frame, consecutive N / b=544 / 4=136 symbols in one channel data stream are from the same KP4 code word.

[0311] As another example, when a>1, it means that the a code words encoded by the outer code at the transmitting device 01 are first interleaved and then distributed in the b channel data streams. Figure 8 As shown, a=2, the two codewords encoded by the outer code KP4 at the transmitting device 01, totaling aN=2*544=1088 symbols, are first subjected to two-way symbol interleavering and then distributed into b=4 channel data streams. Figure 8 The 1088 symbols in the dotted box shown in FIG are from a=2 KP4 code words. In each dotted box, 2N / b=2*544 / 4=272 consecutive symbols in a channel data stream are from a=2 KP4 code words, and two adjacent symbols are from different KP4 code words. Figure 5 As shown, a=2, the two code words encoded by the outer code KP4 at the transmitting device 01, totaling aN=2*544=1088 symbols, are first bidirectionally symbol interleaved and then distributed in b=16 channel data streams. Figure 5 The 1088 symbols shown in the dashed box are from a=2 KP4 code words. In each dashed box, 2N / b=2*544 / 16=68 consecutive symbols in a channel data stream are from a=2 KP4 code words, and two adjacent symbols are from different KP4 code words.

[0312] It should be noted that after convolution interleaving, the consecutive z symbols in each first data stream come from z different codewords, where z is an integer greater than 1. The following describes the specific implementation of convolution interleaving.

[0313] Figure 11 This is a structural diagram of performing convolution interleaving on n channel data streams in an embodiment of the present application. Figure 11 As shown, n convolution interleavers can be used to perform convolution interleaving on n channel data streams, respectively. After convolution interleaving, each channel data stream can obtain a first data stream with disrupted data order. It should be noted that in this embodiment, each convolution interleaver uses a similar method to perform convolution interleaving on the input channel data stream. Specifically, each convolution interleaver includes p delay lines, and each convolution interleaver delays the input channel data stream according to the p delay lines to obtain the first data stream. Where p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between two adjacent delay lines is Q. Each storage unit is used to store d symbols, z = p*d. The symbols in each channel data stream are input into the p delay lines in sequence according to the sequence of the p delay lines. Each delay line inputs d symbols at a time and outputs d symbols at a time. The consecutive p*d symbols in the first data stream include the d symbols output by each delay line. Wherein, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, p delay lines respectively include 0 storage units, Q storage units, 2Q storage units, ..., (p-1)Q storage units, and each storage unit is used to store d symbols. Then, the p delay lines respectively correspond to p delay values, and the delay values ​​include 0 symbols, Q×d symbols, 2Q×d symbols, ..., (p-1)Q×d symbols. It should be noted that the delay values ​​in this application are counted in units of symbols, where a symbol can include one or more bits. The more symbols the delay value of the delay line includes, the longer the delay (also called time delay) of the delay line to the data stream. It should be understood that when the delay line does not include a storage unit, the delay of the delay line is 0 symbol, that is, there is no delay in transmission.

[0314] The specific structure of the convolution interleaver is introduced below with reference to the accompanying drawings.

[0315] FIG12(a) is a schematic diagram of the first structure of the convolution interleaver in an embodiment of the present application. As shown in FIG12(a), the number of storage units in the p delay lines decreases in sequence according to the sequence number of the p delay lines. That is, delay line 0 has (p-1)Q storage units, each delay line decreases by Q storage units in sequence, and delay line p-1 has 0 storage units. FIG12(b) is a schematic diagram of the second structure of the convolution interleaver in an embodiment of the present application. As shown in FIG12(b), the number of storage units in the p delay lines increases in sequence according to the sequence number of the p delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units in sequence, and delay line p-1 has (p-1)Q storage units.

[0316] It should be noted that at the same moment, the switches for the input and output of the convolution interleaver are located on the same delay line. After the current delay line inputs d symbols and outputs d symbols at a time, the switch is switched to the next delay line to ensure that the symbols in each channel data stream are input to the p delay lines in sequence according to the sequence of the p delay lines, and the continuous p*d symbols in the first data stream include the d symbols output by each delay line. The specific data reading and writing operations are as follows: d symbols are read from the storage unit closest to the output port of the current delay line. The d symbols stored in each storage unit in the current delay line are transferred to the next storage unit. Then, d symbols are written to the storage unit closest to the input port in the current delay line. After that, switch to the next delay line and repeat the above operations, and so on. In one possible implementation, if the convolutional interleaver shown in FIG12(a) is used, the parameters of the convolutional interleaver should satisfy d(p*Q+1)≥a*N / b, where N is the length of the codeword, so that the consecutive p*d symbols in the first data stream output by the convolutional interleaver come from p*d different outer codewords, where d≤a. In another possible implementation, if the convolutional interleaver shown in FIG12(b) is used, the parameters of the convolutional interleaver should satisfy d(p*Q-1)≥a*N / b, where N is the length of the codeword, so that the consecutive p*d symbols in the first data stream output by the convolutional interleaver come from p*d different outer codewords, where d≤a.

[0317] It should be understood that when the same parameters p, Q, and d are used, the convolutional interleaving process in Figure 12(a) and the convolutional interleaving process in Figure 12(b) are inverse operations of each other. That is, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 12(a), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 12(b). Similarly, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 12(b), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 12(a).

[0318] It should also be understood that any one of the n convolutional interleavers can adopt either of Figure 12(a) or Figure 12(b). In practical applications, the n convolutional interleavers can all adopt the structure shown in Figure 12(a); alternatively, the n convolutional interleavers can all adopt the structure shown in Figure 12(b); or alternatively, some of the convolutional interleavers can adopt the structure shown in Figure 12(a), and the remaining convolutional interleavers can adopt the structure shown in Figure 12(b).

[0319] It should be noted that, in some specific application scenarios, taking n=32 as an example, the value of p can be 2, 3, 4, 6 or 8, and the value of d can be 1 or 2.

[0320] For ease of introduction, the following embodiments involving convolutional interleaving are explained using n convolutional interleavers using the structure shown in Figure 12(a) as an example. Of course, it can be simply expanded to other structures listed above. The specific implementation method is known to ordinary technicians in this field and will not be repeated here.

[0321] In some possible implementations, before performing convolution interleaving on the n channel data streams to obtain the n first data streams, the n channel data streams may be reordered so that the n data streams are arranged in a predetermined order. Taking 32 data streams as an example, the 32 data streams may be arranged from top to bottom in the order of 0 to 31. This can of course be easily extended to other orderings. The specific implementation method is known to those skilled in the art and will not be detailed here.

[0322] In some possible implementations, before performing convolution interleaving on the n channel data streams to obtain the n first data streams, channel data alignment processing may also be performed on the n channel data streams. The channel data alignment processing may be a lane de-skew processing (lane de-skew) defined by existing standards, so that the data of the n channel data streams outputted therefrom are completely aligned. Alternatively, the above-mentioned "channel data alignment processing" may also be only channel symbol alignment, so that the data on the n channel data streams outputted therefrom are based on outer code symbol alignment, specifically, it may be based on one outer code symbol alignment, or it may be based on multiple outer code symbol alignment. For a detailed introduction to the channel data alignment processing, please refer to the relevant description of FIG3(e) above, which will not be repeated here.

[0323] 1002. Multiplex every K first data streams among the n first data streams to obtain one second data stream, so as to obtain a total of m second data streams.

[0324] Figure 13 FIG. 1 is a structural diagram of multiplexing n first data streams in an embodiment of the present application. Figure 13As shown, m multiplexers can be used for multiplexing processing. Specifically, each K first data streams in the n first data streams input a multiplexer, and the multiplexer outputs one second data stream. The m multiplexers will output a total of m second data streams, where m=n / K, and k is an integer greater than 1. For convenience of description, the embodiment of the present application is described as an example where the integer n is divisible by K. It should be noted that the n first data streams include G first data stream subsets, G is an integer greater than 1, and the symbols in different first data stream subsets come from different codewords. In one possible implementation, if K≤G, one first data stream is selected from any K first data stream subsets, that is, the K first data streams input to a multiplexer come from the K first data stream subsets. In another possible implementation, if K>G, K / G first data streams are taken from each first data stream subset, that is, the K first data streams input to a multiplexer include K / G first data streams in each first data stream subset. For example, if n = 32, G = 2, K = 4, and m = 8, since K > G, it is necessary to select two first data streams from each of the two first data stream subsets to obtain four first data streams input to the multiplexer. For another example, if n = 32, G = 4, K = 2, and m = 8, since K < G, it is necessary to select two first data stream subsets from the four first data stream subsets and select one first data stream from each of the two first data stream subsets to obtain two first data streams input to the multiplexer.

[0325] It should be noted that, in some specific application scenarios, taking n=32 as an example, the value of K can be 2, 4 or 8.

[0326] It should be understood that the above-mentioned first data stream subset is a concept introduced only for the convenience of description. In actual applications, the n first data streams are a whole and there is no division. Each first data stream subset can be regarded as one or more data streams among the n first data streams.

[0327] It should be noted that since the z consecutive symbols in each multiplexed first data stream come from z different codewords, the y consecutive symbols in each multiplexed second data stream come from y different codewords, where y>z. In one possible implementation, if K≤G, then y=K*z. In another possible implementation, if K>G, then y=G*z.

[0328] For ease of description, the K first data streams input by the multiplexer are uniformly referred to as multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, ..., and multiplexed input data stream K-1.

[0329] Figure 14This is a schematic diagram of the first structure of the multiplexer in the embodiment of the present application. Figure 14 As shown, It represents Δ consecutive symbols in the multiplexed input data stream j, which come from Δ different outer code words, where 0≤j≤K-1, if K≤G, Δ is a divisor of z; if K>G, Δ=z. Represents Δ·W consecutive RS symbols in the multiplexed input data stream j. It should be noted that the second data stream output by the multiplexer includes multiple second data stream symbol subsets, each second data stream symbol subset includes K groups of symbols, and each group of symbols includes Δ symbols. Moreover, two adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets. Specifically, the j-th group of symbols in the second data stream symbol subset comes from the j-th multiplexed input data stream in the K multiplexed input data streams, where 0≤j≤K-1. It should be noted that if K>G, the two adjacent multiplexed input data streams in the K multiplexed input data streams come from different first data stream subsets. It should be further noted that if K>G, each of the G consecutive multiplexed input data streams comes from different first data stream subsets.

[0330] It should be noted that since the two adjacent groups of symbols in each second data stream symbol subset come from different first data stream subsets, the y consecutive symbols in the second data stream after multiplexing come from different y codewords, where y>z (y=K*z or y=G*z). It should be understood that if only convolution interleaving is used to obtain that the y consecutive symbols in the output data stream come from different y codewords, the required delay is relatively high. In this solution, while reducing the time occupied by convolution interleaving, combined with multiplexing processing, comparable performance can still be achieved. Moreover, the time occupied by the multiplexing processing is relatively short, and the combination of convolution interleaving and multiplexing can achieve comparable performance with a shorter delay.

[0331] It should be understood that the above-mentioned second data stream symbol subset is a concept introduced only for the convenience of description. In actual applications, the symbols in the second data stream are a whole and there is no division. Each second data stream symbol subset can be regarded as multiple symbols in the second data stream.

[0332] by Figure 14 For example, Denoted as the 0th second data stream symbol subset, Denoted as the first second data stream symbol subset,…, It is recorded as the Wth second data stream symbol subset. Taking the 0th second data stream symbol subset as an example, represents the Δ symbols in group 0, Indicates the Δ symbols in the first group, ..., represents the Δ symbols in the K-1th group. It can be seen that From the multiplexed input data stream 0, From the multiplexed input data stream From the multiplexed input data stream K-1. It should be understood that assuming Δ = z, z consecutive symbols in come from z different codewords, and should come from different subsets of the first data stream, that is, the multiplexed input data stream 0 and the multiplexed input data stream 1 come from different subsets of the first data stream. Similarly, and should come from different subsets of the first data stream, that is, the multiplexed input data stream 1 and the multiplexed input data stream 2 come from different subsets of the first data stream, and so on. In this way, every consecutive 2*z symbols in the second data stream after multiplexing come from 2*z different outer codewords. It should be noted that if K > G, every consecutive G multiplexed input data streams come from different subsets of the first data stream. Specifically, the multiplexed input data streams 0 to the multiplexed input data stream G-1 come from different subsets of the first data stream, the multiplexed input data stream G and the multiplexed input data stream 2*G-1 come from different subsets of the first data stream, and so on. In this way, every consecutive G*z symbols in the second data after multiplexing come from G*z different outer codewords.

[0333] That is to say, through the above method, the multiplexer outputs the data in the K input data streams to a second data stream in a polling manner in units of Δ symbols, that is, it outputs Δ symbols from each of the multiplexed input data streams 0 to the multiplexed input data stream K-1 in turn to generate the second data stream. The corresponding order of the second data stream data is When K ≤ G, the K first data streams selected from the first data stream subsets can correspond to the multiplexed input data streams 0 to the multiplexed input data stream K-1 of the multiplexer in any order, and Δ is a divisor of z. Any consecutive K*z symbols in the second data stream after multiplexing output come from different outer codewords. When K > G, the K first data streams selected from the first data stream subsets need to correspond to the multiplexed input data streams 0 to the multiplexed input data stream K-1 of the multiplexer according to certain rules. The specific rule is that every consecutive G multiplexed input data streams of the multiplexer come from different subsets of the first data stream. A specific method is that the multiplexed input data streams i*G to the multiplexed input data stream i*G+G-1 come from the first data stream subsets 0 to the first data stream subset G-1 respectively, where 0 ≤ i < K / G. This can make every consecutive G*z symbols in the second data stream output by the multiplexer come from different outer codewords.

[0334] 1003. Perform second FEC encoding on each of the m second data streams to obtain encoded data streams.

[0335] Figure 15 FIG. 1 is a structural diagram of performing FEC encoding on m second data streams in an embodiment of the present application. Figure 15 As shown, the m second data streams are each subjected to second FEC encoding, namely the inner code encoding mentioned above. The information bit length of the inner code encoding is less than or equal to y RS symbols. The inner code-encoded data streams are then processed and sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing. For example, the inner code-encoded data streams can be interleaved before transmission to improve the system's ability to withstand burst errors.

[0336] In an embodiment of the present application, the n-channel data streams are all codeword streams after outer code encoding. The n-channel data streams are subjected to convolution interleaving processing respectively, and the n-channel data streams after convolution interleaving are multiplexed into m-channel second data streams, which are then subjected to inner code encoding. By adopting the data interleaving and multiplexing processing scheme provided by the present application, it is possible to achieve the multiple symbols of the multiplexed m-channel data streams in the continuous output from multiple different outer code words with a shorter delay, so that the cascade FEC scheme can help reduce the delay of data interleaving while ensuring better performance. In other words, the scheme of combining convolution interleaving processing with data multiplexing in the present application makes the overall delay of the cascade FEC scheme lower, which is more suitable for application scenarios requiring low delay.

[0337] The above is described below with reference to some specific embodiments. Figure 10 The process of the described data processing method is further introduced.

[0338] Example 1: Applied to the scenario of 1×800G interface, the inner code encoding information bit length is 120 bits, 2:1, 4:1, and 8:1 multiplexers are used, and channel correction processing is adopted.

[0339] Based on the data processing diagram of the transmitting end processing module shown in Figure 3(a), the transmitting end processing module uses the known alignment marker of the PCS channel to perform alignment lock on the channel data stream. The known alignment markers of the 32 channels here are different (see "Ethernet Technology Consortium 800G Specification"). The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 fully aligned channel data streams. Then, lane reordering processing is performed on the data of n=32 channels according to the alignment marker, so that the data of n=32 channels can be arranged in the specified order. One order is to follow Figure 5 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0340] The n=32 channel data streams, after channel reordering, are fed into the designed convolutional interleaving and multiplexing processor for processing, including convolutional interleaving and multiplexing, and then into the inner code encoder for inner code encoding. After data processing, the inner code encoded data streams are fed into the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing.

[0341] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 use the same interleaving structure.

[0342] Figure 16(a) is a schematic diagram of the third structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 16(a), it includes p = 3 delay lines. These p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d = 2 symbols. In other words, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

[0343] As shown in Figure 16(a), C r (.) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (6t), C r(6t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (6t-12Q), C r (6t-12Q+1) are the two RS symbols output by delay line 0; C r (6t+2), C r (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (6t-6Q+2), C r (6t-6Q+3) are the two RS symbols output by delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (6t+4), C r (6t+5) are the two RS symbols output by delay line 2; C r (6t+6), C r (6t+7) represents the two RS symbols subsequently input to delay line 0 in the channel data stream and C r (6t-12Q+6), C r (6t-12Q+7) are the two RS symbols output by delay line 0, and so on. Figure 5 , it can be seen that when 6Q+2≥68, that is, Q≥11, the convolution interleaving output C r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r A total of (6t+5) 6 RS symbols come from 6 different RS code words.

[0344] Figure 16(b) is a schematic diagram of the fourth structure of the convolution interleaver in an embodiment of the present application. As shown in Figure 16(b), in a possible implementation, Q=11 is selected, and the specific structure of the convolution interleaver is shown in Figure 16(b). The corresponding interleaving delay is approximately 22*2*3 / 2=66 RS symbols. The convolution interleaver shown in Figure 16(b) is used to perform convolution interleaving on the 32 PCS channel data streams to obtain 32 first data streams. Reference Figure 5As shown in the PCS channel data stream, it is not difficult to understand that any RS symbol in the first data streams 0-15 and any RS symbol in the first data streams 16-31 come from different RS codewords. Therefore, the 32 first data streams include G=2 first data stream subsets, with the first data streams 0-15 being the first data stream subset 0 and the first data streams 16-31 being the first data stream subset 1. In conjunction with Figure 16(a), it is not difficult to understand that the 6 output symbols C of any data stream r_0 in the first data stream subset 0 r_0 (6t-12Q), C r_0 (6t-12Q+1), C r_0 (6t-6Q+2), C r_0 (6t-6Q+3), C r_0 (6t+4), C r_0 (6t+5) and the 6 output symbols C of any data stream r_1 in the first data stream subset 1 r_1 (6t-12Q), C r_1 (6t-12Q+1), C r_1 (6t-6Q+2), C r_1 (6t-6Q+3), C r_1 (6t+4), C r_1 (6t+5), a total of 12 RS symbols come from 12 different RS code words.

[0345] This embodiment adopts Figure 13 A possible implementation of the multiplexing processing shown is G=2, K=2, m=16, generating 16 second data streams, which includes 16 2:1 multiplexing processing modules, and randomly selecting one first data stream from the first data stream subset 0 and the first data stream subset 1 as the input of the 2:1 multiplexer.

[0346] FIG17(a) is a schematic diagram of the second structure of the multiplexer in the embodiment of the present application. As shown in FIG17(a), the two input data streams of the 2:1 multiplexer i (0≤i≤15) are the first data stream i and the first data stream i+16. The 2:1 multiplexer outputs the data from the two input data streams to the output data stream in a round-robin manner in units of 6 RS symbols. It should be noted that since K=G=2, Δ=1, 2, 3 can also make the 12 consecutive RS symbols in the multiplexer output data stream come from 12 different RS code words.

[0347] This embodiment adopts Figure 13Another possible implementation of the multiplexing process shown is G=2, K=4, and m=8, generating eight second data streams, which includes eight 4:1 multiplexers. Two first data streams are randomly selected from the first data stream subset 0 and the first data stream subset 1 as inputs to the 4:1 multiplexers.

[0348] Figure 17(b) is a schematic diagram of the third structure of the multiplexer in the embodiment of the present application. As shown in Figure 17(b), the multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, and the first data stream i+24, respectively, that is, any two consecutive multiplexed input data streams of the multiplexer come from different first data stream subsets. The 4:1 multiplexer outputs the data from the four input data streams to the output data stream in units of 6 RS symbols in a round-robin manner. The 12 consecutive RS symbols in the output data stream come from 12 different RS code words.

[0349] This embodiment adopts Figure 13 Another possible implementation of the multiplexing process shown is G=2, K=8, and m=4, generating four second data streams, which includes four 8:1 multiplexers. Four first data streams are randomly selected from the first data stream subset 0 and the first data stream subset 1 as inputs to the 8:1 multiplexers.

[0350] Figure 17 (c) is a schematic diagram of the fourth structure of the multiplexer in an embodiment of the present application. As shown in Figure 17 (c), the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, the first data stream i+24, the first data stream i+4, the first data stream i+20, the first data stream i+12, and the first data stream i+28, respectively, that is, any two consecutive multiplexed input data streams of the multiplexer come from different first data stream subsets. It should be noted that the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) can also correspond to the first data stream i, the first data stream i+16, the first data stream i+4, the first data stream i+20, the first data stream i+8, the first data stream i+24, the first data stream i+12, and the first data stream i+28, respectively, that is, any two consecutive multiplexed input data streams of the multiplexer come from different first data stream subsets. In the picture The 8:1 multiplexer outputs the data from the 8 input data streams to the output data stream in units of 6 RS symbols in a round-robin manner. The 12 consecutive RS symbols in the output data stream come from 12 different RS code words.

[0351] The above-mentioned 16, 8 or 4 second data streams are respectively inner-coded, wherein the inner-coded information bit length is 120 bits. Specifically, the inner-code encoder adds redundancy to 12 consecutive RS symbols totaling 120 bits in each second data stream to obtain an inner-code codeword data stream. In one possible implementation, Hamming (128, 120) is used for inner-code encoding, and 8 bits of redundancy are added to 12 consecutive RS symbols totaling 120 bits in each second data stream to obtain a 128-bit codeword. In another possible implementation, BCH (136, 120) is used for inner-code encoding, and 16 bits of redundancy are added to 12 consecutive RS symbols totaling 120 bits in each second data stream to obtain a 136-bit codeword.

[0352] The inner-coded data stream undergoes data processing before being sent to the channel transmission medium for transmission. This data processing may include modulation mapping, channel interleaving, polarization distribution, or DSP framing. For example, the inner-coded data stream can be interleaved to improve the system's ability to withstand burst errors.

[0353] Using the data interleaving coding scheme of Example 1, the KP4 RS (544, 514) + Hamming (128, 120) concatenated code achieves a post-correction bit error rate (BER) of 1E-15 under AWGN, with a pre-correction BER of approximately 4.5E-3. This performance approaches the optimal performance of the concatenated FEC scheme.

[0354] Example 2: Applied to the scenario of 1×800G interface, the inner code encoding information bit length is 120 bits, 2:1, 4:1, and 8:1 multiplexers are used, and channel symbol alignment is adopted.

[0355] The main difference between Example 2 and Example 1 is that Example 2 is based on the alignment of 2 RS symbols to obtain 32 channel data streams.

[0356] Specifically, based on the data processing diagram of the transmitting end processing module shown in Figure 3(a), the transmitting end processing module uses the known alignment markers of the PCS lanes to perform alignment lock on the lane data streams. The transmitting end processing module then applies two RS symbols to the 32 lane data streams to obtain 32 aligned lane data streams. Lane reordering is then performed on the 32 lanes based on the alignment markers, arranging the data in a specified order. One possible order is to sort the lane data streams from top to bottom, from 0 to 31, as in Figure 3(a). Another possible order is to arrange the 32 lanes output by the "lane reordering" process so that the first 16 lane data streams, from top to bottom, contain PCS lane data streams 0-15, and the last 16 lanes contain PCS lane data streams 16-31. It should be understood that the specific order of the first 16 lane data streams is not limited, nor is the specific order of the last 16 lane data streams. That is, the channel data stream i in FIG3( a ) does not necessarily correspond to the PCS channel data stream i.

[0357] The 32 channel data streams, after channel reordering, are fed into a designed processor that includes convolutional interleaving and multiplexing for interleaving, disrupting the data order, and then fed into an inner code encoder for inner code encoding. After data processing, the inner code-encoded data streams are fed into a channel transmission medium for transmission. It should be understood that the convolutional interleaving, multiplexing, and inner code encoding schemes employed in this embodiment are the same as those employed in Example 1.

[0358] Using the data interleaving coding scheme of Example 2, the KP4 RS (544, 514) + Hamming (128, 120) concatenated code achieves a post-correction bit error rate (BER) of 1E-15 under AWGN, corresponding to a pre-correction BER of approximately 4.5E-3. This performance is comparable to that of Example 1, with lower overall latency. However, compared to Example 1, Example 2 is less robust against system burst errors. This solution is suitable for scenarios requiring even lower latency.

[0359] Example 3: Applied to the scenario of 1×800G interface, the inner code encoding information bit length is 160 bits, 2:1, 4:1, and 8:1 multiplexers are used, and channel correction processing is adopted.

[0360] Based on Example 1, this embodiment considers an inner code with a code length of 160 bits and accordingly adopts a newly designed convolutional interleaver.

[0361] In this embodiment, the convolution interleaving process is performed as follows: Figure 11The structure shown performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 use the same interleaving structure.

[0362] FIG18( a ) is a schematic diagram of the fifth structure of the convolution interleaver in an embodiment of the present application. As shown in FIG18( a ), it includes p=4 delay lines. These four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0363] As shown in Figure 18(a), C r (.) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in channel data stream r and C r (8t-24Q), C r (8t-24Q+1 are the two RS symbols output by delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (8t-16Q+2), C r (8t-16Q+3) are the two RS symbols output by delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (8t-8Q+4), C r (8t-8Q+5) are the two RS symbols output by delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream and C r (8t+6), C r (8t+7) are the two RS symbols output by delay line 3, and so on. Figure 5 , it can be seen that when 8Q+2≥68, that is, Q≥9, the convolution interleaving output C r (8t-24Q), C rCr(8t-24Q+1, Cr(8t-16Q+2, Cr(8t-16Q+3, Cr(8t-8Q+4, Cr(8t-8Q+5, Cr(8t+6, Cr(8t+7, a total of 8 RS symbols come from 8 different RS code words.

[0364] Figure 18(b) is a schematic diagram of the sixth structure of the convolution interleaver in an embodiment of the present application. As shown in Figure 18(b), in a possible implementation, Q=9 is selected, and the specific structure of the convolution interleaver is shown in Figure 18(b). The corresponding interleaving delay is approximately 27*2*4 / 2=108 RS symbols. The convolution interleaver shown in Figure 18(b) is used to perform convolution interleaving on the 32 PCS channel data streams to obtain 32 first data streams. Reference Figure 5 As shown in the PCS channel data stream, it is not difficult to understand that any RS symbol in the first data streams 0-15 and any RS symbol in the first data streams 16-31 come from different RS codewords. Therefore, the 32 first data streams include G=2 first data stream subsets, with the first data streams 0-15 being the first data stream subset 0 and the first data streams 16-31 being the first data stream subset 1. In conjunction with Figure 18(a), it is not difficult to understand that the 8 output symbols C of any data stream r_0 in the first data stream subset 0 r_0 (8t-24Q), C r_0 (8t-24Q+1), C r_0 (8t-16Q+2), C r_0 (8t-16Q+3), C r_0 (8t-8Q+4), C r_0 (8t-8Q+5), C r_0 (8t+6), C r_0 (8t+7), and 8 output symbols C of any data stream r_1 in the first data stream subset 1 r_1 (8t-24Q), C r_1 (8t-24Q+1), C r_1 (8t-16Q+2), C r_1 (8t-16Q+3), C r1 (8t-8Q+4), C r_1 (8t-8Q+5), C r_1 (8t+6), C r_1 (8t+7), a total of 16 RS symbols come from 16 different RS code words.

[0365] This embodiment adopts Figure 13A possible implementation of the multiplexing process shown is G = 2, K = 2, m = 16, generating 16 second data streams, which includes 16 2:1 multiplexing processing modules, each of which randomly selects one first data stream from the first data stream subset 0 and the first data stream subset 1 as the input of the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17 (a), where the two input data streams of the 2:1 multiplexer i (0≤i≤15) are the first data stream i and the first data stream i+16. j x The 2:1 multiplexer outputs the data from the two input data streams to the output data stream in a round-robin manner in units of 8 RS symbols, i.e., the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words. It should be noted that K=G=2, Δ=1, 2, 4 can also make the 16 consecutive RS symbols in the multiplexer output data stream come from 16 different RS code words.

[0366] This embodiment adopts Figure 13 Another possible implementation of the multiplexing process shown is G=2, K=4, m=8, generating 8 second data streams, which includes 8 4:1 multiplexers, and arbitrarily selects 2 first data streams from the first data stream subset 0 and the first data stream subset 1 as the input of the 4:1 multiplexer. A specific implementation of the corresponding 4:1 multiplexer is shown in Figure 17(b). The multiplexed input data stream 0, multiplexed input data stream 1, multiplexed input data stream 2, and multiplexed input data stream 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, and the first data stream i+24, respectively, that is, any two consecutive multiplexed input data of the multiplexer come from different first data symbol subsets. In the figure The 4:1 multiplexer outputs the data from the four input data streams to the output data stream in units of 8 RS symbols in a round-robin manner. The 16 consecutive RS symbols in the output data stream come from 16 different RS code words.

[0367] This embodiment adopts Figure 13Another possible implementation of the multiplexing process shown is G=2, K=8, m=4, producing 4 second data streams, which includes 4 8:1 multiplexers. Four first data streams are randomly selected from the first data stream subset 0 and the first data stream subset 1 as the input of the 8:1 multiplexer. A specific implementation of the corresponding 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) correspond to the first data stream i, the first data stream i+16, the first data stream i+4, the first data stream i+20, the first data stream i+8, the first data stream i+24, the first data stream i+12, and the first data stream i+28 respectively. In the figure The 8:1 multiplexer outputs the data from the 8 input data streams to the output data stream in a round-robin manner in units of 8 RS symbols, i.e., the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words.

[0368] The 16, 8, or 4 second data streams are each inner-coded, wherein the inner-coded information bit length is 160 bits. Specifically, the inner-code encoder adds redundancy to 16 consecutive RS symbols (a total of 160 bits) in the second data stream to obtain an inner-code codeword data stream. In one possible implementation, Hamming (170, 160) is used for inner-code encoding, and 10 bits of redundancy are added to 16 consecutive RS symbols (a total of 160 bits) in each second data stream to obtain a 170-bit codeword. In another possible implementation, BCH (176, 160) is used for inner-code encoding, and 16 bits of redundancy are added to 16 consecutive RS symbols (a total of 160 bits) in each second data stream to obtain a 176-bit codeword. The inner-coded data stream is then processed and sent to the channel transmission medium for transmission.

[0369] Using the data interleaving coding scheme of this embodiment, when the inner code uses Hamming (170, 160), the KP4 RS (544, 514) + Hamming (170, 160) concatenated code achieves a pre-correction BER of approximately 4.3E-3 to achieve a post-correction BER of 1E-15 under AWGN, approaching the optimal performance of this concatenated FEC scheme. When the inner code uses BCH (176, 160), the KP4 RS (544, 514) + BCH (176, 160) concatenated code achieves a pre-correction BER of approximately 8.3E-3 to achieve a post-correction BER of 1E-15 under AWGN, approaching the optimal performance of this concatenated FEC scheme.

[0370] Example 4: Applied to the scenario of 1×800G interface, the inner code encoding information bit length is 160 bits, 2:1, 4:1, and 8:1 multiplexers are used, and channel symbol alignment is adopted.

[0371] The main difference between Example 4 and Example 3 is that Example 4 is based on the alignment of 2 RS symbols to obtain aligned 32 channel data streams.

[0372] Specifically, based on the data processing diagram of the transmitting end processing module shown in Figure 3(a), the transmitting end processing module uses the known alignment markers of the PCS lanes to perform alignment lock on the lane data streams. The transmitting end processing module then applies two RS symbols to the 32 lane data streams to obtain 32 aligned lane data streams. Lane reordering is then performed on the 32 lanes based on the alignment markers, arranging the data in a specified order. One possible order is to sort the lane data streams from top to bottom, from 0 to 31, as in Figure 3(a). Another possible order is to arrange the 32 lanes output by the "lane reordering" process so that the first 16 lane data streams, from top to bottom, contain PCS lane data streams 0-15, and the last 16 lanes contain PCS lane data streams 16-31. It should be understood that the specific order of the first 16 lane data streams is not limited, nor is the specific order of the last 16 lane data streams. That is, the channel data stream i in FIG3( a ) does not necessarily correspond to the PCS channel data stream i.

[0373] The 32 channel data streams, after channel reordering, are fed into a processor designed to perform convolutional interleaving and multiplexing, where they are interleaved to disrupt the data order and then fed into an inner code encoder for inner code encoding. After data processing, the inner code-encoded data streams are fed into a channel transmission medium for transmission. It should be understood that the convolutional interleaving, multiplexing, and inner code encoding schemes employed in this embodiment all follow those of Example 3.

[0374] Using the data interleaving coding scheme of Example 4, its KP4 RS (544, 514) + Hamming (160, 120) concatenated code achieves a post-correction bit error rate (BER) of 1E-15 under AWGN, corresponding to a pre-correction BER of approximately 4.5E-3. This performance is comparable to that of Example 3, with lower overall latency. However, compared to Example 3, the scheme of Example 4 is less robust against system burst errors. This scheme is suitable for scenarios requiring even lower latency.

[0375] Using the data interleaving coding scheme of Example 4, when the inner code uses Hamming (170, 160), the KP4RS (544, 514) + Hamming (170, 160) concatenated code achieves a pre-correction BER of approximately 4.3E-3 to achieve a post-correction BER of 1E-15 under AWGN, approaching the optimal performance of the concatenated FEC scheme. When the inner code uses BCH (176, 160), the KP4RS (544, 514) + BCH (176, 160) concatenated code achieves a pre-correction BER of approximately 8.3E-3 to achieve a post-correction BER of 1E-15 under AWGN, approaching the optimal performance of the concatenated FEC scheme. It should be understood that, using the same inner code scheme as Example 3, the performance of Example 4 is the same as that of Example 3, but is inferior in combating system burst errors. This scheme is suitable for scenarios requiring lower latency.

[0376] Example 5: Applied to the scenario of 2×400G interface, the inner code encoding information bit length is 120 or 160 bits, 2:1, 4:1, and 8:1 multiplexers are used, and channel correction processing is adopted.

[0377] Different from Examples 1-4, this embodiment considers a client-side interface of 2×400G with each channel of 100Gb / s. The interface details are shown in "IEEE Std 802.3ckTM / D3.0".

[0378] Specifically, based on the data processing diagram of the transmitting end processing module shown in FIG3(a) above, the transmitting end processing module uses the known alignment markers (Alignment marker) of PCS channels 0-15 or PCS channels 16-31 to perform alignment lock on the 16 channel data streams. The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, lane reordering processing is performed on the data of the 16 channels according to the alignment markers of PCS channels 0-15 or PCS channels 16-31, so that the data of the 16 channels can be arranged in the specified order. Finally, the data of the 32 channels can be arranged in the specified order. One order is to follow Figure 6 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0379] The 32 channel data streams after channel reordering are sent to the designed processor including convolution interleaving and multiplexing for interleaving and disrupting the data order, and then sent to the inner code encoder for inner code encoding. The inner code encoded data streams are processed and sent to the channel transmission medium for transmission.

[0380] In one possible implementation, when the processor including convolution interleaving and multiplexing, and the inner code encoding used in this embodiment 5 are the same as those in embodiment 1, the performance and delay of the cascaded FEC solution are the same as those in embodiment 1.

[0381] In another possible implementation, when the processor including convolution interleaving and multiplexing, and the inner code encoding used in this embodiment 5 are the same as those in embodiment 3, the performance and delay of the cascaded FEC scheme are the same as those in embodiment 3.

[0382] Example 6: Applied to the scenario of 2×400G interface, the inner code encoding information bit length is 120 or 160 bits, 2:1, 4:1, and 8:1 multiplexers are used, channel symbol alignment is used, and channel reordering is not performed.

[0383] Based on the solution in Example 5, Example 6 provides an implementation solution with lower latency.

[0384] Specifically, based on the data processing diagram of the transmitting processing module shown in Figure 3(b), the transmitting processing module uses known alignment markers for PCS channels 0-15 or PCS channels 16-31 to perform alignment lock on the 16 channel data streams. The transmitting processing module then performs alignment on the 32 channel data streams using two RS symbols, resulting in 32 aligned channel data streams. These 32 aligned channel data streams are then directly fed into a designed processor that includes convolutional interleaving and multiplexing for interleaving and disrupting the data order. The data streams are then fed into an inner code encoder for inner code encoding. After data processing, the inner code encoded data streams are fed into the channel transmission medium for transmission.

[0385] In one possible implementation, when the processor including convolution interleaving and multiplexing and the inner code encoding used in this embodiment 6 are the same as those in embodiment 2, the performance and delay of the cascaded FEC scheme are the same as those in embodiment 2.

[0386] In another possible implementation, when the processor including convolution interleaving and multiplexing, and the inner code encoding used in this embodiment 6 are the same as those in embodiment 4, the performance and delay of the cascaded FEC scheme are the same as those in embodiment 4.

[0387] Example 7: Applied to the scenario of 4×200G interface, the inner code encoding information bit length is 120 or 160 bits, a 4:1 or 8:1 multiplexer is used, and channel correction processing is adopted.

[0388] This embodiment considers that the client-side interface is 4×200G with each channel of 100 Gb / s. The interface details can be found in "IEEE Std 802.3ckTM / D3.0".

[0389] Based on the data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module uses the known alignment markers of PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31 to perform alignment lock on the eight lane data streams. Here, PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31 can be considered to represent PCS lanes 0-7 in the 0th, 1st, 2nd, or 3rd 200G lane, respectively. The transmitting processing module then performs lane de-skew on the 32 lane data streams to obtain the 32 aligned lane data streams. Lane reordering is then performed on the eight lanes based on the alignment markers of PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31, ensuring that the eight lanes of data are arranged in the specified order. Finally, the data of 32 channels can be arranged in the specified order. One order is to follow Figure 7 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0390] The 32 channel data streams after channel reordering are sent to the designed processor including convolution interleaving and multiplexing for interleaving and disrupting the data order, and then sent to the inner code encoder for inner code encoding. The inner code encoded data streams are processed and sent to the channel transmission medium for transmission.

[0391] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 use the same interleaving structure.

[0392] Figure 19(a) is a schematic diagram of the seventh structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 19(a), it includes p = 2 delay lines. These two delay lines include Q storage units and 0 storage units, respectively, and each storage unit is used to store d = 2 symbols. In other words, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbols, that is, no delay.

[0393] As shown in Figure 19(a), C r(·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (4t), C r (4t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream and C r (4t-4Q), C r (4t-4Q+1) are the two RS symbols output by delay line 0; C r (4t+2), C r (4t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (4t+2), C r (4t+3) are the two RS symbols output by delay line 1; C r (4t+4), C r (4t+5) represents the next two RS symbols input to delay line 0 in the channel data stream and C r (4t-4Q+4), C r (4t-4Q+5) are the two RS symbols output by delay line 0, and so on. Figure 7 , it can be seen that when 4Q+2≥136, that is, Q≥34, the four consecutive RS symbols C output by convolution interleaving r (4t-4Q), C r (4t-4Q+1), C r (4t+2), C r (4t+3) come from 4 different RS code words.

[0394] Figure 19(b) is a schematic diagram of the eighth structure of the convolution interleaver in the embodiment of the present application. As shown in Figure 19(b), in one possible implementation, Q=34 is selected, and the specific structure of the convolution interleaver is shown in Figure 19(b). The corresponding interleaving delay is approximately 34*2*2 / 2=68 RS symbols. The convolution interleaver shown in Figure 19(b) is used to perform convolution interleaving on the 32 PCS channel data streams to obtain 32 first data streams. Reference Figure 7 As can be readily understood from the PCS channel data streams shown, any RS symbol in first data streams 0-7, any RS symbol in first data streams 8-15, any RS symbol in first data streams 16-23, and any RS symbol in first data streams 24-31 all originate from different RS codewords. Therefore, the 32 first data streams comprise G = 4 first data stream subsets: first data streams 0-7 constitute first data stream subset 0, first data streams 8-15 constitute first data stream subset 1, first data streams 16-23 constitute first data stream subset 2, and first data streams 24-31 constitute first data stream subset 3.

[0395] This embodiment adopts Figure 13 One possible implementation of the multiplexing process shown is G = 4, K = 4, and m = 8, comprising eight 4:1 multiplexers. Each multiplexer multiplexes four first data streams into one second data stream, generating a total of eight second data streams. One first data stream is randomly selected from each of first data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3 as input to the 4:1 multiplexer.

[0396] A specific implementation of the corresponding 4:1 multiplexer is shown in FIG17(b). The multiplexed input data stream 0, the multiplexed input data stream 1, the multiplexed input data stream 2, and the multiplexed input data stream 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, and the first data stream i+24, respectively. It should be noted that the multiplexed input data stream 0, the multiplexed input data stream 1, the multiplexed input data stream 2, and the multiplexed input data stream 3 of the 4:1 multiplexer i (0≤i≤7) can also correspond to the first data stream i, the first data stream i+8, the first data stream i+16, and the first data stream i+24, respectively. In this embodiment, as shown in FIG17(b), C j x Indicates that the 4:1 multiplexer's multiplexed input data stream j (0≤j≤3) has Δ=4 consecutive RS symbols, which come from 4 different outer code RS code words. The 4:1 multiplexer outputs the data from the 4 input data streams to the output data stream in a polling manner according to the unit of 4 RS symbols, that is, the output data sequence is The 16 consecutive RS symbols in the output data stream come from 16 different RS codewords. Note that since K = G = 4, one first data stream each from the first data stream subsets 0 to 3 can correspond in any order to the multiplexed input data streams 0 to 3 of 4:1 multiplexer i (0 ≤ i ≤ 7). Δ = 1, 2 can still ensure that the 16 consecutive RS symbols in the second data stream come from 16 different RS codewords.

[0397] This embodiment adopts Figure 13 Another possible implementation of the multiplexing process shown is G = 4, K = 8, and m = 4, which includes four 8:1 multiplexers. Each multiplexer multiplexes eight first data streams into one second data stream, generating a total of four second data streams. Two first data streams are randomly selected from each of first data stream subset 0, first data stream subset 1, first data stream subset 2, and first data stream subset 3 as inputs to the 8:1 multiplexers.

[0398] A specific implementation of the corresponding 8:1 multiplexer is shown in Figure 17(c). The multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, the first data stream i+24, the first data stream i+4, the first data stream i+20, the first data stream i+12, and the first data stream i+28, respectively, which makes any consecutive Q=4 multiplexed input data streams of the multiplexer come from different first data stream subsets. It should be noted that the multiplexed input data streams 0 to 7 of the 8:1 multiplexer i (0≤i≤3) can also correspond to the first data stream i, the first data stream i+8, the first data stream i+16, the first data stream i+24, the first data stream i+4, the first data stream i+12, the first data stream i+20, and the first data stream i+28, respectively. In the figure Indicates that the 8:1 multiplexer's multiplexed input data stream j (0≤j≤7) has Δ=4 consecutive RS symbols, which come from 4 different outer code RS code words. The 8:1 multiplexer outputs the data from the 8 input data streams to the output data stream in a polling manner according to the unit of 4 RS symbols, that is, the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words.

[0399] The above 8 or 4 second data streams are respectively inner-coded, and their inner-code coding scheme can adopt the coding scheme given in Example 1 to obtain performance equivalent to that of Example 1; or they can adopt the coding scheme given in Example 3 to obtain performance equivalent to that of Example 3, which will not be repeated here.

[0400] Example 8: Applied to the scenario of 4×200G interface, the inner code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and channel correction processing is adopted.

[0401] Based on Example 7, this embodiment considers adopting a 2:1 multiplexer and correspondingly adopting a newly designed convolutional interleaver.

[0402] Specifically, based on the data processing diagram of the transmitting end processing module shown in Figure 3(a), the transmitting end processing module uses the known alignment markers of PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31 to perform alignment lock on the eight lane data streams. Here, PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31 can be considered to be PCS lanes 0-7 in the 0th, 1st, 2nd, or 3rd 200G lane, respectively. The transmitting end processing module then performs lane de-skew processing on the 32 lane data streams to obtain 32 aligned lane data streams. Lane reordering is then performed on the eight lanes of data based on the alignment markers of PCS lanes 0-7, PCS lanes 8-15, PCS lanes 16-23, or PCS lanes 24-31, ensuring that the eight lanes of data are arranged in the specified order. Finally, the data of 32 channels can be arranged in the specified order. One order is to follow Figure 7 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0403] The 32 channel data streams after channel reordering are sent to the designed processor including convolution interleaving and multiplexing for interleaving and disrupting the data order, and then sent to the inner code encoder for inner code encoding. The inner code encoded data streams are processed and sent to the channel transmission medium for transmission.

[0404] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown in FIG16 is used to perform convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 adopt the same interleaving structure. FIG16(a) shows a convolution interleaver structure, which includes p=3 delay lines. These three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, that is, there is no delay.

[0405] As shown in Figure 16(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (6t), C r (6t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream and C r (6t-12Q), Cr (6t-12Q+1) are the two RS symbols output by delay line 0; C r (6t+2), C r (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (6t-6Q+2), C r (6t-6Q+3) are the two RS symbols output by delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (6t+4), C r (6t+5) are the two RS symbols output by delay line 2; C r (6t+6), C r (6t+7) represents the two RS symbols subsequently input to delay line 0 in the channel data stream and C r (6t-12Q+6), C r (6t-12Q+7) are the two RS symbols output by delay line 0, and so on. Figure 7 , it can be seen that when 6Q+2≥136, that is, Q≥23, the convolution interleaving output C r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r A total of (6t+5) 6 RS symbols come from 6 different RS code words.

[0406] Figure 20 FIG. 9 is a ninth structural diagram of a convolution interleaver according to an embodiment of the present application. Figure 20 As shown, in a possible implementation, Q=23 is selected, and the specific structure of the convolution interleaver is as follows Figure 20 As shown in the figure, the corresponding interleaving delay is about 46*2*3 / 2=138 RS symbols. Figure 20 The convolution interleaver shown performs convolution interleaving on 32 PCS channel data streams to obtain 32 first data streams. Figure 7For the PCS channel data stream shown, it is not difficult to understand that any RS symbol in the first data stream 0 - 7, any RS symbol in the first data stream 8 - 15, any RS symbol in the first data stream 16 - 23, and any RS symbol in the first data stream 24 - 31 all come from different RS codewords. Therefore, the 32 first data streams contain G = 4 first data stream subsets. The first data stream 0 - 7 is the first data stream subset 0, the first data stream 8 - 15 is the first data stream subset 1, the first data stream 16 - 23 is the first data stream subset 2, and the first data stream 24 - 31 is the first data stream subset 3.

[0407] One possible implementation of the multiplexing process adopted in this embodiment is G = 4, K = 2, m = 16. It includes 16 2:1 multiplexers. Each multiplexer multiplexes 2 first data streams to obtain 1 second data stream, generating a total of 16 second data streams. Arbitrarily take 1 first data stream from each of any 2 first data stream subsets among the first data stream subset 0, the first data stream subset 1, the first data stream subset 2, and the first data stream subset 3 as the inputs of the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Fig. 17(a). The multiplexed input data stream 0 and input data stream 1 of the 2:1 multiplexer i (0 ≤ i ≤ 15) respectively correspond to the first data stream i and the first data stream i + 16. In the figure Figure 13 represents Δ = 6 consecutive RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 1) of the 2:1 multiplexer, which come from 6 different outer code RS codewords. The 2:1 multiplexer outputs the data in the 2 input data streams to the output data stream in a polling manner in units of 6 RS symbols, that is, the output data order is 12 consecutive RS symbols in the output data stream come from 12 different RS codes. It should be noted that since K < G, then Δ = 1, 2, 3 can still make 12 consecutive RS symbols in the second data stream come from 12 different RS codes.

[0408] The above 16 second data streams are respectively subjected to inner code encoding. The inner code encoding scheme can adopt the encoding scheme given in Embodiment 1 to obtain performance equivalent to that in Embodiment 1, which will not be elaborated here.

[0409] Embodiment 9: Applied to the scenario of a 4×200G interface, the length of the inner code encoding information bits is 160 bits, a 2:1 multiplexer is adopted, and channel deviation correction processing is adopted.

[0410] Based on Embodiment 8, this embodiment considers an inner code with a code length of 160 bits and correspondingly adopts a newly designed convolutional interleaver.

[0411] Specifically, this embodiment adopts the convolutional interleaver structure shown in Figure 18(a), which includes p = 4 delay lines. These four delay lines include 3Q storage cells, 2Q storage cells, Q storage cells, and 0 storage cells, respectively, with each storage cell being used to store d = 2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0412] As shown in Figure 18(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream and C r (8t-24Q), C r (8t-24Q+1) are the two RS symbols output by delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (8t-16Q+2), C r (8t-16Q+3) are the two RS symbols output by delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (8t-8Q+4), C r (8t-8Q+5) are the two RS symbols output by delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream and C r (8t+6), C r (8t+7) are the two RS symbols output by delay line 3, C r (8t+8), C r (8t+9) represents the two RS symbols subsequently input to delay line 0 in the channel data stream and C r (8t-24Q+8), C r (8t-24Q+9) are the two RS symbols output by delay line 0, and so on. Figure 7 , it can be seen that when 8Q+2≥136, that is, Q≥17, the convolution interleaving output C r (8t-24Q), C r (8t-24Q+1), Cr (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r A total of 8 RS symbols (8t+7) come from 8 different RS code words.

[0413] Figure 21 FIG. 1 is a schematic diagram of the tenth structure of the convolution interleaver in the embodiment of the present application. Figure 21 As shown, in a possible implementation, Q=17 is selected, and the specific structure of the convolution interleaver is as follows Figure 21 The corresponding interleaving delay is approximately 51*2*4 / 2=204 RS symbols.

[0414] Use Figure 21 The convolution interleaver shown performs convolution interleaving on 32 PCS channel data streams to obtain 32 first data streams. Figure 7 As can be readily understood from the PCS channel data streams shown, any RS symbol in first data streams 0-7, any RS symbol in first data streams 8-15, any RS symbol in first data streams 16-23, and any RS symbol in first data streams 24-31 all originate from different RS codewords. Therefore, the 32 first data streams comprise G = 4 first data stream subsets: first data streams 0-7 constitute first data stream subset 0, first data streams 8-15 constitute first data stream subset 1, first data streams 16-23 constitute first data stream subset 2, and first data streams 24-31 constitute first data stream subset 3.

[0415] This embodiment adopts Figure 13 A possible implementation of the multiplexing process shown is G=4, K=2, m=16, which includes 16 2:1 multiplexers, each of which multiplexes two first data streams to obtain one second data stream, generating a total of 16 second data streams. One first data stream is randomly selected from any two first data stream subsets among the first data stream subset 0, the first data stream subset 1, the first data stream subset 2 and the first data stream subset 3 as the input of the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17(a), where the multiplexed input data stream 0 and the multiplexed input data stream 1 of the 2:1 multiplexer i (0≤i≤15) correspond to the first data stream i and the first data stream i+16, respectively. In the figure Denote consecutive Δ = 8 RS symbols in the multiplexed input data stream j (0 ≤ j ≤ 1) of the 2:1 multiplexer, which are from 8 different outer code RS codewords. The 2:1 multiplexer outputs the data in the two input data streams to the output data stream in a polling manner in units of 8 RS symbols, that is, the output data order is Sixteen consecutive RS symbols in the output data stream are from 16 different RS codewords. It should be noted that since K < G, Δ = 1, 2, or 4 can still make sixteen consecutive RS symbols in the second data stream be from 16 different RS codes.

[0416] The above 16 second data streams are respectively subjected to inner code encoding. The inner code encoding scheme can adopt the encoding scheme given in Embodiment 3 to obtain performance equivalent to that of Embodiment 3, which will not be elaborated here.

[0417] Embodiment 10: Applied to the scenario of a 4×200G interface, the length of the inner code encoded information bits is 160 bits, and channel symbol alignment is adopted.

[0418] Based on any of the embodiments in Embodiments 7 - 9, this embodiment gives a lower latency implementation scheme.

[0419] Based on the data processing schematic diagram of the transmitting end processing module shown in Fig. 3(d), the transmitting end processing module uses the known alignment markers (Alignment marker) of PCS channels 0 - 7, PCS channels 8 - 15, PCS channels 16 - 23, or PCS channels 24 - 31 to perform alignment lock (alignment lock) on the 8-channel data streams. Here, PCS channels 0 - 7, PCS channels 8 - 15, PCS channels 16 - 23, or PCS channels 24 - 31 can be respectively regarded as PCS channels 0 - 7 in the 0th, 1st, 2nd, or 3rd 200G. The transmitting end processing module then performs alignment on the 32-channel data streams based on the alignment of 2 RS symbols to obtain 32 aligned channel data streams. Then directly send the 32 aligned channel data streams into the designed processor containing multiplexing for processing and then send them into the inner code encoder for inner code encoding. The data stream after inner code encoding is processed and then sent into the channel transmission medium for transmission.

[0420] In a possible implementation manner, when both the multiplexing processing and the inner code encoding scheme of this embodiment adopt the scheme of Embodiment 7, the performance of its concatenated code under AWGN is equivalent to that of the scheme of Embodiment 7, and it has a lower overall latency. However, compared with the scheme of Embodiment 7, the scheme of this embodiment is worse in combating system burst errors. This scheme is applicable to some scenarios with lower latency requirements.

[0421] In another possible implementation, when both the multiplexing process and the inner code encoding scheme of this embodiment adopt the scheme of Example 8, the performance of the concatenated code under AWGN is comparable to that of the scheme of Example 8, and has lower overall latency. However, compared with Example 8, the scheme of this embodiment is less robust against system burst errors. This scheme is suitable for scenarios requiring lower latency.

[0422] In another possible implementation, when both the multiplexing process and the inner code encoding scheme of this embodiment adopt the scheme of Example 9, the performance of the concatenated code under AWGN is comparable to that of the scheme of Example 9, and has lower overall latency. However, compared with Example 9, the scheme of this embodiment is less robust against system burst errors. This scheme is suitable for scenarios requiring lower latency.

[0423] Example 11: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits or 160 bits, an 8:1 multiplexer is used, and channel correction processing is adopted.

[0424] This embodiment considers that the client-side interface is 8×100G with each channel of 100Gb / s and adopts the "100G RS-FEC-Int" mode. The interface details are shown in "IEEE Std 802.3ckTM / D3.0".

[0425] Based on the data processing diagram of the transmitting processing module shown in Figure 3(c), the transmitting processing module uses the known alignment markers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 to perform alignment lock on the four data streams. Here, FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, according to the alignment identifiers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27 or FEC channels 28-31, the data of the four channels are subjected to lane reordering processing so that the data of the four channels can be arranged in the specified order. Finally, the data of the 32 channels can be arranged in the specified order. One order is to follow Figure 11 The same channel data streams are sorted from top to bottom, from 0 to 31. The 32 reordered channel data streams are not convolutionally interleaved but directly multiplexed to produce a total of 16 second data streams. These are then sent to the inner code encoder for inner code encoding. After data processing, the inner code encoded data streams are sent to the channel transmission medium for transmission.

[0426] refer to Figure 8It is not difficult to understand the PCS channel data stream shown. Any RS symbol in channel data streams 0-3, any RS symbol in channel data streams 4-7, any RS symbol in channel data streams 8-11, any RS symbol in channel data streams 12-15, any RS symbol in channel data streams 16-19, any RS symbol in channel data streams 20-23, any RS symbol in channel data streams 24-27, and any RS symbol in channel data streams 28-31 all come from different RS codewords. Since the channel data streams are not convolutionally interleaved, channel data streams 0-31 are equivalent to the first data stream 0-31. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0427] This embodiment adopts Figure 13 One possible implementation of the multiplexing process shown is G = 8, K = 8, and m = 4, which multiplexes 32 channel data streams to obtain four second data streams. Among them, one of the first data stream subset 0, one of the first data stream subset 1, one of the first data stream subset 2, one of the first data stream subset 3, one of the first data stream subset 4, one of the first data stream subset 5, one of the first data stream subset 6, and one of the first data stream subset 7, a total of eight channel data streams, serve as eight input data streams for an 8:1 multiplexer i (0≤i≤3). A specific implementation is shown in FIG17(c). Multiplexer i (0≤i≤3) converts the first data stream i, the first data stream i+16, the first data stream i+8, the first data stream i+24, the first data stream i+4, the first data stream i+20, the first data stream i+12, and the first data stream i+28 to the multiplexed input data streams 0 to 7 of the 8:1 multiplexer, respectively. Indicates that the consecutive Δ=2 RS symbols in the multiplexed input data stream j (0≤j≤7) of the 8:1 multiplexer come from two different outer code RS code words. The 8:1 multiplexer outputs the data in the 8 input data streams to the output data stream in a polling manner according to the unit of 2 RS symbols, that is, the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words. It should be noted that since K≤G, Δ=1 can still make the 16 consecutive RS symbols in the second data stream come from 16 different RS codes.

[0428] Figure 22 This is a fifth structural diagram of the multiplexer in the embodiment of the present application. Figure 22 As shown, multiplexer i (0≤i≤3) converts the first data stream i, the first data stream i+4, the first data stream i+8, the first data stream i+12, the first data stream i+16, the first data stream i+20, the first data stream i+24, and the first data stream i+28 into the multiplexed input data streams 0 to 7 of the 8:1 multiplexer, respectively. Indicates that the consecutive Δ=2 RS symbols in the multiplexed input data stream j (0≤j≤7) of the 8:1 multiplexer come from two different outer code RS code words. The 8:1 multiplexer outputs the data in the 8 input data streams to the output data stream in a polling manner according to the unit of 2 RS symbols, that is, the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words. It should be noted that since K≤G, Δ=1 can still make the 16 consecutive RS symbols in the second data stream come from 16 different RS codes.

[0429] The above four second data streams are respectively inner-coded, and their inner-code coding scheme can adopt the coding scheme given in Example 1 to obtain performance equivalent to that of Example 1; or they can adopt the coding scheme given in Example 3 to obtain performance equivalent to that of Example 3, which will not be repeated here.

[0430] Example 12: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits or 160 bits, a 4:1 multiplexer is used, and channel correction processing is adopted.

[0431] Based on the solution in Example 11, this embodiment provides a solution for achieving the second lowest latency when the multiplexing process uses a 4:1 multiplexer.

[0432] Based on the data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module uses the known alignment markers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 to perform alignment lock on the four data streams. Here, FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, according to the alignment identifiers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27 or FEC channels 28-31, the data of the four channels are subjected to lane reordering processing so that the data of the four channels can be arranged in the specified order. Finally, the data of the 32 channels can be arranged in the specified order. One order is to follow Figure 11 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0433] The 32 channel data streams after channel reordering are sent to the designed processor including convolution interleaving and multiplexing for interleaving and disrupting the data order, and then sent to the inner code encoder for inner code encoding. The inner code encoded data streams are processed and sent to the channel transmission medium for transmission.

[0434] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown in FIG19 is a convolution interleaver structure that performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 adopt the same interleaving structure. FIG19(a) shows a convolution interleaver structure that includes p=2 delay lines. These two delay lines include Q storage units and 0 storage units, respectively, and each storage unit is used to store d=2 symbols. That is, the delay value of delay line 0 is 2Q symbols, and the delay value of delay line 1 is 0 symbols, that is, there is no delay.

[0435] As shown in Figure 19(a), C r(·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (4t), C r (4t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream and C r (4t-4Q), C r (4t-4Q+1) are the two RS symbols output by delay line 0; C r (4t+2), C r (4t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (4t+2), C r (4t+3) are the two RS symbols output by delay line 1; C r (4t+4), C r (4t+5) represents the next two RS symbols input to delay line 0 in the channel data stream and C r (4t-4Q+4), C r (4t-4Q+5) are the two RS symbols output by delay line 0, and so on. Figure 8 , it can be seen that when 4Q+2≥272, that is, Q≥68, the four consecutive RS symbols C output by convolution interleaving r (4t-4Q), C r (4t-4Q+1), C r (4t+2), C r (4t+3) come from 4 different RS code words.

[0436] Figure 23 FIG. 11 is a schematic diagram of the eleventh structure of the convolution interleaver in the embodiment of the present application. Figure 23 As shown, in a possible implementation, Q=68 is selected, and the specific structure of the convolution interleaver is as follows Figure 23 The corresponding interleaving delay is approximately 68*2*2 / 2=136 RS symbols.

[0437] Use Figure 23 The convolution interleaver shown performs convolution interleaving on 32 PCS channel data streams to obtain 32 first data streams. Figure 8It is not difficult to understand the PCS channel data streams shown in that any RS symbol in channel data streams 0-3, any RS symbol in channel data streams 4-7, any RS symbol in channel data streams 8-11, any RS symbol in channel data streams 12-15, any RS symbol in channel data streams 16-19, any RS symbol in channel data streams 20-23, any RS symbol in channel data streams 24-27, and any RS symbol in channel data streams 28-31 all come from different RS codewords. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0438] This embodiment adopts Figure 13 A possible implementation of the multiplexing process shown is G=8, K=4, m=8, which includes 8 4:1 multiplexers, each of which multiplexes 4 first data streams to obtain 1 second data stream, generating a total of 8 second data streams. From any 4 first data stream subsets in the first data stream subsets 0-7, any 1 first data stream is selected as the input of the 4:1 multiplexer. A specific implementation is shown in Figure 17(b). The multiplexed input data streams 0 to 3 of the 4:1 multiplexer i (0≤i≤7) correspond to the first data stream i, the first data stream i+16, the first data stream i+8, and the first data stream i+24, respectively. In the figure The 4:1 multiplexer outputs the data from the four input data streams to the output data stream in a round-robin manner in units of four RS symbols, i.e., the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words. It should be noted that since K≤G, Δ=1,2 can still make the 16 consecutive RS symbols in the second data stream come from 16 different RS codes.

[0439] Figure 24 This is a sixth structural diagram of the multiplexer in the embodiment of the present application. Figure 24 As shown, multiplexer i (0≤i≤3) converts the first data stream i, the first data stream i+8, the first data stream i+16, and the first data stream i+24 into the multiplexed input data streams 0 to 3 of the 4:1 multiplexer, respectively. The 4:1 multiplexer outputs the data from the four input data streams to the output data stream in a round-robin manner in units of four RS symbols, i.e., the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words. It should be noted that since K≤G, Δ=1,2 can still make the 16 consecutive RS symbols in the second data stream come from 16 different RS codes.

[0440] The above 8 second data streams are respectively inner-coded, and their inner-code coding scheme can adopt the coding scheme given in Example 1 to obtain performance equivalent to that of Example 1; or they can adopt the coding scheme given in Example 3 to obtain performance equivalent to that of Example 3, which will not be repeated here.

[0441] Example 13: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and channel correction processing is adopted.

[0442] On the basis of Example 12, this embodiment considers the multiplexing process using a 2:1 multiplexer and an inner code with an information length of 120 bits, and correspondingly adopts a newly designed convolutional interleaver and multiplexing process.

[0443] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown in FIG16 is a convolution interleaver structure that performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 adopt the same interleaving structure. FIG16(a) shows a convolution interleaver structure that includes p=3 delay lines. These three delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=2 symbols. That is, the delay value of delay line 0 is 4Q symbols, the delay value of delay line 1 is 2Q symbols, and the delay value of delay line 2 is 0 symbols, i.e., no delay.

[0444] As shown in Figure 16(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (6t), C r (6t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream and C r (6t-12Q), C r (6t-12Q+1) are the two RS symbols output by delay line 0; C r (6t+2), Cr (6t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (6t-6Q+2), C r (6t-6Q+3) are the two RS symbols output by delay line 1; C r (6t+4), C r (6t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (6t+4), C r (6t+5) are the two RS symbols output by delay line 2; C r (6t+6), C r (6t+7) represents the two RS symbols subsequently input to delay line 0 in the channel data stream and C r (6t-12Q+6), C r (6t-12Q+7) are the two RS symbols output by delay line 0, and so on. Figure 8 , it can be seen that when 6Q+2≥272, that is, Q≥45, the convolution interleaving output C r (6t-12Q), C r (6t-12Q+1), C r (6t-6Q+2), C r (6t-6Q+3), C r (6t+4), C r A total of (6t+5) 6 RS symbols come from 6 different RS code words.

[0445] Figure 25 This is a twelfth structural diagram of the convolution interleaver in the embodiment of the present application. Figure 25 As shown, in a possible implementation, Q=45 is selected, and the specific structure of the convolution interleaver is as follows Figure 25 The corresponding interleaving delay is approximately 90*2*3 / 2=270 RS symbols.

[0446] Use Figure 25 The convolution interleaver shown performs convolution interleaving on 32 PCS channel data streams to obtain 32 first data streams. Figure 8It is not difficult to understand the PCS channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0447] This embodiment adopts Figure 13 A possible implementation of the multiplexing process shown is G=8, K=2, m=16, that is, it includes 16 2:1 multiplexers, each multiplexer multiplexes two first data streams to obtain one second data stream, and generates a total of 16 second data streams. From any two first data stream subsets in the first data stream subsets 0-7, one first data stream is randomly selected as the input of the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and the multiplexed input data stream 1 of the 2:1 multiplexer i (0≤i≤15) correspond to the first data stream i and the first data stream i+16 respectively. In the figure The 2:1 multiplexer outputs the data from the two input data streams to the output data stream in a round-robin manner in units of 6 RS symbols, i.e., the output data order is The 12 consecutive RS symbols in the output data stream come from 12 different RS code words. It should be noted that since K≤G, Δ=1, 2, 3 can still make the 12 consecutive RS symbols in the second data stream come from 12 different RS codes.

[0448] The encoding scheme for the 16 second data streams output by the multiplexing process can all adopt the scheme in Example 1, and obtain performance equivalent to that of Example 1, which will not be described in detail here.

[0449] Example 14: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 160 bits, a 2:1 multiplexer is used, and channel correction processing is adopted.

[0450] On the basis of Example 12, this embodiment considers the use of a 2:1 multiplexer for multiplexing processing and an inner code with an information length of 160 bits, and accordingly adopts a newly designed convolutional interleaver and multiplexing processing.

[0451] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown in FIG18 is used to perform convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolution interleaving 0, convolution interleaving 1, convolution interleaving 2, ..., and convolution interleaving 31 use the same interleaving structure. FIG18(a) shows a convolution interleaver structure, which includes p=4 delay lines. These four delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=2 symbols. That is, the delay value of delay line 0 is 6Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 2Q symbols, and the delay value of delay line 3 is 0 symbols, that is, no delay.

[0452] As shown in Figure 18(a), C r () represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (8t), C r (8t+1) represents the two RS symbols currently input to delay line 0 in the channel data stream and C r (8t-24Q), C r (8t-24Q+1) are the two RS symbols output by delay line 0; C r (8t+2), C r (8t+3) represents the next two RS symbols input to delay line 1 in the channel data stream and C r (8t-16Q+2), C r (8t-16Q+3) are the two RS symbols output by delay line 1; C r (8t+4), C r (8t+5) represents the next two RS symbols input to delay line 2 in the channel data stream and C r (8t-8Q+4), C r (8t-8Q+5) are the two RS symbols output by delay line 2; C r (8t+6), C r (8t+7) represents the two RS symbols subsequently input to delay line 3 in the channel data stream and C r (8t+6), C r (8t+7) are the two RS symbols output by delay line 3, C r(8t+8), C r (8t+9) represents the two RS symbols subsequently input to delay line 0 in the channel data stream and C r (8t-24Q+8), C r (8t-24Q+9) are the two RS symbols output by delay line 0, and so on. Figure 8 , it can be seen that when 8Q+2≥272, that is, Q≥34, the convolution interleaving output C r (8t-24Q), C r (8t-24Q+1), C r (8t-16Q+2), C r (8t-16Q+3), C r (8t-8Q+4), C r (8t-8Q+5), C r (8t+6), C r A total of 8 RS symbols (8t+7) come from 8 different RS code words.

[0453] Figure 26 This is the thirteenth structural diagram of the convolution interleaver in the embodiment of the present application. Figure 26 As shown, in a possible implementation, Q=34 is selected, and the specific structure of the convolution interleaver is as follows Figure 26 The corresponding interleaving delay is approximately 102*2*4 / 2=408 RS symbols.

[0454] Use Figure 26 The convolution interleaver shown performs convolution interleaving on 32 PCS channel data streams to obtain 32 first data streams. Figure 8 It is not difficult to understand the PCS channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0455] This embodiment adopts Figure 13 A possible implementation of the multiplexing process shown is G=8, K=2, m=16, that is, it includes 16 2:1 multiplexers, each multiplexer multiplexes two first data streams to obtain one second data stream, and generates a total of 16 second data streams. From any two first data stream subsets in the first data stream subsets 0-7, one first data stream is randomly selected as the input of the 2:1 multiplexer. A specific implementation of the corresponding 2:1 multiplexer is shown in Figure 17(a). The multiplexed input data stream 0 and the multiplexed input data stream 1 of the 2:1 multiplexer i (0≤i≤15) correspond to the first data stream i and the first data stream i+16 respectively. In the figure The 2:1 multiplexer outputs the data from the two input data streams to the output data stream in a round-robin manner in units of 8 RS symbols, i.e., the output data order is The 16 consecutive RS symbols in the output data stream come from 16 different RS code words. It should be noted that since K≤G, Δ=1, 2, 4 can still make the 16 consecutive RS symbols in the second data stream come from 16 different RS codes.

[0456] The inner code encoding scheme for the 16 second data streams output by the multiplexing process can adopt the inner code encoding scheme in Example 3, which can achieve performance equivalent to that of Example 3 and will not be described in detail here.

[0457] Example 15: Applied to the scenario of 8×100G interface, channel symbol alignment is adopted.

[0458] Based on any of Examples 11-14, this embodiment provides an implementation solution with lower latency.

[0459] Based on the data processing diagram of the transmitting processing module shown in Figure 3(b), the transmitting processing module uses known alignment markers for FEC channels 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, or 28-31 to perform alignment lock on the four channel data streams. The transmitting processing module then applies two RS symbols to the 32 channel data streams to create 32 aligned channel data streams. These 32 channel data streams are convolutionally interleaved to produce 32 first data streams. These first data streams are then multiplexed to produce four, eight, or 16 second data streams, which are then fed into an inner code encoder for inner code encoding. After data processing, the inner code-encoded data streams are fed into the channel transmission medium for transmission.

[0460] In this embodiment, when the processor including convolutional interleaving and multiplexing and the inner code encoding are the same as those in Example 11, the concatenated code has comparable performance under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0461] In this embodiment, when the processor including convolutional interleaving and multiplexing and the inner code encoding are the same as those in Example 12, the concatenated code has comparable performance under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0462] In this embodiment, when the processor including convolutional interleaving and multiplexing and the inner code encoding are the same as those in Example 13, the concatenated code has comparable performance under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0463] In this embodiment, when the processor including convolutional interleaving and multiplexing and the inner code encoding are the same as those in Example 14, the concatenated code has comparable performance under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0464] Example 16: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits or 160 bits, an 8:1 multiplexer is used, and channel correction processing is adopted.

[0465] This embodiment considers that the client-side interface is 8×100G with each channel of 100Gb / s and adopts the "100G RS-FEC" mode. The interface details are shown in "IEEE Std 802.3ckTM / D3.0".

[0466] Based on the data processing diagram of the transmitting processing module shown in Figure 3(a), the transmitting processing module uses the known alignment markers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 to perform alignment lock on the four data streams. Here, FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 can be considered as FEC channels 0-3 in the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, or 7th 100G channel, respectively. The transmitting end processing module then performs lane de-skew processing on the 32 channel data streams to obtain 32 aligned channel data streams. Then, according to the alignment identifiers of FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27 or FEC channels 28-31, the data of the four channels are subjected to lane reordering processing so that the data of the four channels can be arranged in the specified order. Finally, the data of the 32 channels can be arranged in the specified order. One order is to follow Figure 9 The same channel data stream is sorted from 0 to 31 from top to bottom.

[0467] The 32 channel data streams after channel reordering are sent to the designed processor including convolution interleaving and multiplexing for interleaving and disrupting the data order, and then sent to the inner code encoder for inner code encoding. The inner code encoded data streams are processed and sent to the channel transmission medium for transmission.

[0468] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown performs convolution interleaving on n=32 FEC channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 adopt the same interleaving structure.

[0469] Figure 27(a) is a schematic diagram of the fourteenth structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 27(a), it includes p = 2 delay lines. These two delay lines include Q storage units and 0 storage units, respectively, each storage unit is used to store d = 1 symbol. In other words, the delay value of delay line 0 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0470] As shown in Figure 27(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (2t) represents the RS symbol currently input to delay line 0 in the channel data stream and C r (2t-2Q) is one RS symbol output by delay line 0; C r (2t+1) represents the next RS symbol input to delay line 1 in the channel data stream and C r (2t+1) is an RS symbol output by delay line 1; C r (2t+2) represents the next RS symbol input to delay line 0 in the channel data stream and C r (2t-2Q+2) is one RS symbol output by delay line 0, and so on. Figure 9 , it can be seen that when 2Q+1≥136, that is, Q≥68, the two consecutive RS symbols C output by convolution interleaving r (2t-2Q), C r (2t+1) comes from 2 different RS code words.

[0471] Figure 27(b) is a schematic diagram of the fifteenth structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 27(b), in one possible implementation, Q = 68 is selected, and the specific structure of the convolutional interleaver is shown in Figure 27(b). The corresponding interleaving delay is approximately 68*2 / 2 = 68 RS symbols.

[0472] The convolution interleaver shown in FIG27( b ) is used to perform convolution interleaving on the 32 FEC channel data streams to obtain 32 first data streams. Figure 9It is not difficult to understand the FEC channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0473] This embodiment adopts the 8:1 multiplexing processing structure in Embodiment 11, and can obtain 4 second data streams, and the 16 consecutive RS symbols in each second data stream all come from 16 different RS code words.

[0474] The above four second data streams are respectively inner-coded. The inner-coding scheme can adopt the coding scheme given in Example 1 to obtain performance equivalent to that of Example 1; or the coding scheme given in Example 3 can be adopted to obtain performance equivalent to that of Example 3, which will not be repeated here.

[0475] Example 17: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits, a 4:1 multiplexer is used, and channel correction processing is adopted.

[0476] Based on the solution of Example 16, this embodiment provides that the inner code information length is 120 bits, and when a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing process are correspondingly used.

[0477] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 use the same interleaving structure.

[0478] FIG28( a ) is a schematic diagram of the sixteenth structure of the convolutional interleaver in an embodiment of the present application. As shown in FIG28( a ), it includes p = 3 delay lines. These p = 3 delay lines include 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d = 1 symbol. In other words, the delay value of delay line 0 is 2Q symbols, the delay value of delay line 1 is Q symbols, and the delay value of delay line 1 is 0 symbols, i.e., no delay.

[0479] As shown in Figure 28(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (3t) represents the RS symbol currently input to delay line 0 in the channel data stream and C r (3t-6Q) is an RS symbol output by delay line 0; C r (3t+1) represents the next RS symbol input to delay line 1 in the channel data stream and C r (3t-3Q+1) is an RS symbol output by delay line 1; C r (3t+2) represents the next RS symbol input to delay line 2 in the channel data stream and C r (3t+2) is an RS symbol output by delay line 2; C r (3t+3) represents the RS symbol that is subsequently input to delay line 0 in the channel data stream and C r (3t-6Q+3) is one RS symbol output by delay line 0, and so on. Figure 9 , it can be seen that when 3Q+1≥136, that is, Q≥45, the convolution interleaving output C r (3t-6Q), C r (3t-3Q+2), C r A total of (3t+2) 3 RS symbols come from 3 different RS code words.

[0480] Figure 28(b) is a schematic diagram of the seventeenth structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 28(b), in one possible implementation, Q = 45 is selected, and the specific structure of the convolutional interleaver is shown in Figure 28(b). The corresponding interleaving delay is approximately 90*3 / 2 = 135 RS symbols.

[0481] The convolution interleaver shown in FIG28( b ) is used to perform convolution interleaving on the 32 FEC channel data streams to obtain 32 first data streams. Figure 9It is not difficult to understand the FEC channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0482] This embodiment adopts the multiplexing processing structure in Embodiment 12, and Δ=1,3 can obtain 8 second data streams, and the 12 consecutive RS symbols in each second data stream all come from 12 different RS code words.

[0483] The encoding scheme for the eight second data streams output by the multiplexing process can all adopt the scheme in Example 1, and obtain performance equivalent to that of Example 1, which will not be described in detail here.

[0484] Example 18: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 160 bits, a 4:1 multiplexer is used, and channel correction processing is adopted.

[0485] Based on the solution in Example 16, this embodiment provides a second-lowest latency implementation solution when the inner code information length is 160 bits and a 4:1 multiplexer is used for multiplexing, and a newly designed interleaver and multiplexing process are correspondingly used.

[0486] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown in FIG. 1 performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams. Convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, and convolution interleaver 31 use the same interleaving structure.

[0487] FIG29( a ) is a schematic diagram of the eighteenth structure of the convolution interleaver in an embodiment of the present application. As shown in FIG29( a ), it includes p=4 delay lines. These p=4 delay lines include 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=1 symbol. That is, the delay value of delay line 0 is 3Q symbols, the delay value of delay line 1 is 2Q symbols, the delay value of delay line 2 is Q symbols, and the delay value of delay line 3 is 0 symbols, i.e., no delay.

[0488] As shown in Figure 29(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (4t) represents the RS symbol currently input to delay line 0 in the channel data stream and C r (4t-12Q) is one RS symbol output by delay line 0; C r (4t+1) represents the next RS symbol input to delay line 1 in the channel data stream and C r (4t-8Q+1) is an RS symbol output by delay line 1; C r (4t+2) represents the next RS symbol input to delay line 2 in the channel data stream and C r (4t-4Q+2) is an RS symbol output by delay line 2; C r (4t+3) represents the next RS symbol input to delay line 3 in the channel data stream and C r (4t+3) is an RS symbol output by delay line 3; C r (4t+4) represents the RS symbol that is subsequently input to delay line 0 in the channel data stream and C r (4t-12Q+4) is one RS symbol output by delay line 0, and so on. Figure 9 , it can be seen that when 4Q+1≥136, that is, Q≥34, the convolution interleaving continuous output C r (4t-12Q), C r (4t-8Q+1),C r (4t-4Q+2), C r A total of 4 RS symbols (4t+3) come from 4 different RS code words.

[0489] Figure 29(b) is a schematic diagram of the nineteenth structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 29(b), in one possible implementation, Q = 34 is selected, and the specific structure of the convolutional interleaver is shown in Figure 29(b). The corresponding interleaving delay is approximately 102*4 / 2 = 204 RS symbols.

[0490] The convolution interleaver shown in FIG29( b ) is used to perform convolution interleaving on the 32 FEC channel data streams to obtain 32 first data streams. Figure 9 It is not difficult to understand the FEC channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0491] This embodiment adopts the multiplexing processing structure in Embodiment 13, and when Δ=1, 2, 4, 8 second data streams can be obtained, and the 16 consecutive RS symbols in each second data stream all come from 16 different RS code words.

[0492] The eight second data streams are respectively inner-coded, and the inner-coding scheme thereof can adopt the inner-coding scheme of Example 3, which can achieve performance equivalent to that of Example 3, and will not be described in detail here.

[0493] Example 19: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits, a 2:1 multiplexer is used, and channel correction processing is adopted.

[0494] Based on the solution of Example 16, this embodiment provides that the inner code information length is 120 bits, and when a 4:1 multiplexer is used for multiplexing, a newly designed convolutional interleaver and multiplexing process are correspondingly used.

[0495] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 use the same interleaving structure.

[0496] FIG30( a ) is a schematic diagram of the twentieth structure of the convolution interleaver in an embodiment of the present application. As shown in FIG30( a ), it includes p=6 delay lines. These p=6 delay lines include 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=1 symbols. That is, the delay value of delay line 0 is 5Q symbols, the delay value of delay line 1 is 4Q symbols, the delay value of delay line 2 is 3Q symbols, the delay value of delay line 3 is 2Q symbols, the delay value of delay line 4 is Q symbols, and the delay value of delay line 5 is 0 symbols, i.e., no delay.

[0497] As shown in Figure 30(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (6t) represents the RS symbol currently input to delay line 0 in the channel data stream and C r (6t-30Q) is an RS symbol output by delay line 0; C r (6t+1) represents the next RS symbol input to delay line 1 in the channel data stream and C r (6t-24Q+1) is an RS symbol output by delay line 1; C r (6t+2) represents the next RS symbol input to delay line 2 in the channel data stream and C r (6t-18Q+2) is an RS symbol output by delay line 2; C r (6t+3) represents the next RS symbol input to delay line 3 in the channel data stream and C r (6t-12Q+3) is an RS symbol output by delay line 3; C r (6t+4) represents the next RS symbol input to delay line 4 in the channel data stream and C r (6t-6Q+4) is an RS symbol output by delay line 4; C r (6t+5) represents the next RS symbol input to delay line 5 in the channel data stream and C r (6t+5) is an RS symbol output by delay line 5; C r (6t+6) represents the RS symbol that is subsequently input to delay line 0 in the channel data stream and C r (6t-30Q+6) is one RS symbol output by delay line 0, and so on. Figure 9 , it can be seen that when 6Q+1≥136, that is, Q≥23, the convolution interleaving continuous output C r (6t-30Q), C r(6t-24Q+1), C r (6t-18Q+2), C r (6t-12Q+3), C r (6t-6Q+4), C r A total of (6t+5) 6 RS symbols come from 6 different RS code words.

[0498] Figure 30(b) is a schematic diagram of the twenty-first structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 30(b), in one possible implementation, Q = 23 is selected, and the specific structure of the convolutional interleaver is shown in Figure 30(b). The corresponding interleaving delay is approximately 23*5*6 / 2 = 345 RS symbols.

[0499] The convolution interleaver shown in FIG30( b ) is used to perform convolution interleaving on the 32 FEC channel data streams to obtain 32 first data streams. Figure 9 It is not difficult to understand the FEC channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0500] This embodiment adopts the multiplexing processing structure in Embodiment 13, and 16 second data streams can be obtained when Δ=1, 2, 3, 6, and the 12 consecutive RS symbols in each second data stream all come from 12 different RS code words.

[0501] The 16 second data streams are respectively inner-coded, and their coding scheme can adopt the inner-coding scheme in Example 1, and can achieve performance equivalent to that of Example 1, which will not be described in detail here.

[0502] Example 20: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 160 bits, a 2:1 multiplexer is used, and channel correction processing is adopted.

[0503] Based on the solution of Example 16, this embodiment provides that the inner code information length is 160 bits, and when a 2:1 multiplexer is used for multiplexing processing, a newly designed convolutional interleaver and multiplexing processing are correspondingly used.

[0504] In this embodiment, the convolution interleaving process is performed as follows: Figure 11 The structure shown performs convolution interleaving on n=32 PCS channel data streams to obtain n=32 first data streams, wherein convolution interleaver 0, convolution interleaver 1, convolution interleaver 2, ..., convolution interleaver 31 use the same interleaving structure.

[0505] FIG31( a ) is a schematic diagram of the twenty-second structure of the convolution interleaver in an embodiment of the present application. As shown in FIG31( a ), it includes p=8 delay lines. These p=8 delay lines include 7Q storage units, 6Q storage units, 5Q storage units, 4Q storage units, 3Q storage units, 2Q storage units, Q storage units, and 0 storage units, respectively, and each storage unit is used to store d=1 symbol. That is, the delay value of delay line 0 is 7Q symbols, the delay value of delay line 1 is 6Q symbols, the delay value of delay line 2 is 5Q symbols, the delay value of delay line 3 is 4Q symbols, the delay value of delay line 4 is 3Q symbols, the delay value of delay line 5 is 2Q symbols, the delay value of delay line 6 is Q symbols, and the delay value of delay line 7 is 0 symbols, i.e., no delay.

[0506] As shown in Figure 31(a), C r (·) represents an RS symbol in the channel data stream r (0≤r≤n-1). For example, C r (8t) represents the RS symbol currently input to delay line 0 in the channel data stream and C r (8t-56Q) is an RS symbol output by delay line 0; C r (8t+1) represents the next RS symbol input to delay line 1 in the channel data stream and C r (8t-48Q+1) is an RS symbol output by delay line 1; C r (8t+2) represents the next RS symbol input to delay line 2 in the channel data stream and C r (8t-40Q+2) is an RS symbol output by delay line 2; C r (8t+3) represents the next RS symbol input to delay line 3 in the channel data stream and C r (8t-32Q+3) is an RS symbol output by delay line 3; C r (8t+4) represents the next RS symbol input to delay line 4 in the channel data stream and Cr (8t-24Q+4) is an RS symbol output by delay line 4; C r (8t+5) represents the next RS symbol input to delay line 5 in the channel data stream and C r (8t-16Q+5) is an RS symbol output by delay line 5; C r (8t+6) represents the next RS symbol input to delay line 6 in the channel data stream and C r (8t-8Q+6) is an RS symbol output by delay line 6; C r (8t+7) represents the next RS symbol input to delay line 7 in the channel data stream and C r (8t+7) is an RS symbol output by delay line 7; C r (8t+8) represents the RS symbol that is subsequently input to delay line 0 in the channel data stream and C r (8t-56Q+8) is one RS symbol output by delay line 0, and so on. Figure 9 , it can be seen that when 8Q+1≥136, that is, Q≥17, the convolution interleaving continuous output C r (8t-56Q), C r (8t-48Q+1),C r (8t-40Q+2), C r (8t-32Q+3),C r (8t-24Q+4), C r (8t-16Q+5),C r (8t-8Q+6),C r A total of 8 RS symbols (8t+7) come from 8 different RS code words.

[0507] Figure 31(b) is a schematic diagram of the twenty-third structure of the convolutional interleaver in an embodiment of the present application. As shown in Figure 31(b), in one possible implementation, Q = 17 is selected, and the specific structure of the convolutional interleaver is shown in Figure 31(b). The corresponding interleaving delay is approximately 17*7*8 / 2 = 476 RS symbols.

[0508] The convolution interleaver shown in FIG31( b ) is used to perform convolution interleaving on the 32 FEC channel data streams to obtain 32 first data streams. Figure 9It is not difficult to understand the FEC channel data stream shown that any RS symbol in the first data stream 0-3, any RS symbol in the first data stream 4-7, any RS symbol in the first data stream 8-11, any RS symbol in the first data stream 12-15, any RS symbol in the first data stream 16-19, any RS symbol in the first data stream 20-23, any RS symbol in the first data stream 24-27, and any RS symbol in the first data stream 28-31 all come from different RS code words. Therefore, the 32 first data streams include G=8 first data stream subsets, first data streams 0-3 are first data stream subset 0, first data streams 4-7 are first data stream subset 1, first data streams 8-11 are first data stream subset 2, first data streams 12-15 are first data stream subset 3, first data streams 16-19 are first data stream subset 4, first data streams 20-23 are first data stream subset 5, first data streams 24-27 are first data stream subset 6, and first data streams 28-31 are first data stream subset 7.

[0509] This embodiment adopts the multiplexing processing structure in Embodiment 13, and 16 second data streams can be obtained when Δ=1, 2, 4, 8, and the 16 consecutive RS symbols in each second data stream all come from 16 different RS code words.

[0510] The 16 second data streams are respectively inner-coded, and the inner-coding scheme thereof can adopt the inner-coding scheme of Example 3, which can achieve performance equivalent to that of Example 3 and will not be described in detail here.

[0511] Example 21: Applied to the scenario of 8×100G interface, the inner code encoding information bit length is 120 bits or 160 bits, and channel symbol alignment is used.

[0512] Based on any of the embodiments in Examples 16-20, this embodiment provides an implementation solution with lower latency.

[0513] Based on the data processing diagram of the transmitting processing module shown in Figure 3(d), the transmitting processing module uses known alignment markers for FEC channels 0-3, FEC channels 4-7, FEC channels 8-11, FEC channels 12-15, FEC channels 16-19, FEC channels 20-23, FEC channels 24-27, or FEC channels 28-31 to perform alignment lock on the four channel data streams. The transmitting processing module then applies single-Relative Synchronous Resonance (RS) symbol alignment to the 32 channel data streams, resulting in 32 aligned channel data streams. These 32 channel data streams are convolutionally interleaved to produce 32 first data streams. These first data streams are then multiplexed to produce four, eight, or 16 second data streams, which are then fed into an inner code encoder for inner code encoding. After data processing, the inner code-encoded data streams are fed into the channel transmission medium for transmission.

[0514] It should be understood that the multiplexing and inner code encoding schemes adopted in this embodiment all adopt the schemes given in any of Examples 16-20.

[0515] When the processor and inner code used in this embodiment are the same as those in Example 16, the concatenated code performs similarly under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0516] When the processor and inner code used in this embodiment are the same as those in Example 17, the concatenated code performs similarly under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0517] When the processor and inner code used in this embodiment are the same as those in Example 18, the concatenated code performs similarly under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0518] When the processor and inner code used in this embodiment are the same as those in Example 19, the concatenated code performs similarly under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0519] When the processor and inner code used in this embodiment are the same as those in Example 20, the concatenated code performs similarly under AWGN, but is slightly inferior in combating system burst errors. This solution is suitable for scenarios requiring lower latency.

[0520] It should be noted that, in some possible implementations, the multiplexing process described in the above embodiments may also be replaced by group interleaving, which will be described below in conjunction with a specific embodiment.

[0521] Figure 32(a) is a schematic diagram of a structure for performing group interleaving of n first data streams in an embodiment of the present application. As shown in Figure 32(a), group interleaving can be performed using m parallel group interleaving modules. Specifically, each group interleaver generates a second data stream by group interleaving the K input first data streams, resulting in a total of m second data streams. The method for selecting the K first data streams input to each group interleaver is consistent with the method for selecting the K input multiplexed data streams input to the multiplexer in the above-mentioned embodiments, and will not be repeated here.

[0522] FIG32( b ) is a schematic diagram of a structure of a packet interleaver in an embodiment of the present application. As shown in FIG32( b ), the first data stream i k The consecutive Δ RS symbols in the symbol subset are called S k (.) represents, where 0≤k≤K-1. Therefore, S k (0),S k (1),…,S k (W) represents the first data stream i k The output is a continuous W symbol subset. The continuous Δ RS symbols in the second data stream are a symbol subset, which is represented by S(.). W symbol subsets are obtained from each of the K first data streams input to form a first symbol matrix with K rows and W columns. Each element in the first symbol matrix is ​​a symbol subset, then S k (w) corresponds to the element in the kth row and wth column of the first symbol matrix, where 0≤k≤K-1, 0≤w≤W-1. The first symbol matrix with K rows and W columns is interleaved by group to obtain a second symbol matrix with 1 row and C columns, where C=K*W. Each element in the second symbol matrix is ​​also a symbol subset, and S(c) represents the element in the cth column of the second symbol matrix, where 0≤c≤C. Group interleaving S(c) and S k The mapping between (w) can be expressed as: c = K*w + k. The second symbol matrix S(0), S(0), ..., S(K*W-1) after group interleaving corresponds to the information bits of Q inner codes. After inner code encoding, Q inner codes are obtained. If the inner code length is D symbols, then K*W*Δ = Q*D.

[0523] It should be noted that the above-mentioned symbol subsets are concepts introduced only for ease of description. In actual applications, the first data stream and the second data stream are both integrated and not divided. Each symbol subset can be regarded as one or more symbols in the first data stream or the second data stream. In addition, in actual applications, the above-mentioned first symbol matrix and second symbol matrix may not be presented in matrix form. For example, the first symbol matrix is ​​presented as a first symbol set, and the first symbol set includes K*W symbol subsets, which respectively correspond to K rows and W columns of elements in the first symbol matrix. The second symbol matrix is ​​presented as a second symbol set, and the second symbol set includes C symbol subsets, which respectively correspond to 1 row and C columns of elements in the second symbol matrix.

[0524] As an example, based on the convolutional interleaver given in Implementation 1, a specific implementation of the corresponding group interleaving is G=2, K=2, m=16. The input first data stream i0 and the first data stream i1 of the group interleaver i correspond to the first data stream i and the first data stream i+16, respectively. Taking the group interleaver structure shown in Figure 32(b) as an example, the parameters of the group interleaver can be Δ=6, W=1, Q=1; or Δ=3, W=2, Q=1. The second symbol matrix is ​​mapped into information data with an inner code of 120 bits. The inner code encoding scheme in Implementation 1 can be used to achieve comparable performance.

[0525] As another example, based on the convolution interleaver given in Implementation 1, another specific implementation of the corresponding group interleaving is G=2, K=4, m=16. The input first data stream i0 to the first data stream i3 of the group interleaver i correspond to the first data stream i, the first data stream i+16, the first data stream i+8, and the first data stream i+24, respectively. Taking the group interleaver structure shown in Figure 32(b) as an example, the parameters of the group interleaver can be Δ=6, W=1, Q=2. The second symbol matrix is ​​mapped into information data with 2 information length bits of 120 bits of inner code. The inner code encoding scheme in Implementation 1 can be used to achieve comparable performance.

[0526] As another example, based on the convolution interleaver given in Example 1, another specific implementation of the corresponding group interleaving is G=2, K=8, m=16. The input first data stream i0 to the first data stream i7 of the group interleaver i correspond to the first data stream i, the first data stream i+16, the first data stream i+8, the first data stream i+24, the first data stream i+4, the first data stream i+20, the first data stream i+12, and the first data stream i+28, respectively. Taking the group interleaver structure shown in Figure 32(b) as an example, the parameters of the group interleaver can be Δ=6, W=1, and Q=4. The second symbol matrix is ​​mapped into information data of 4 inner codes with an information bit length of 120 bits. The inner code encoding scheme in Example 1 can be used to achieve comparable performance.

[0527] It should be understood that the corresponding group interleaving implementation methods can also be derived based on the convolutional interleaving and inner code encoding schemes of other embodiments, which are not listed one by one here.

[0528] The above describes the data processing method provided in the embodiment of the present application. The following describes the data processing device provided in the embodiment of the present application.

[0529] Figure 33 FIG. 1 is a structural diagram of a data processing device in an embodiment of the present application. Figure 33 As shown, the data processing device includes a convolution interleaver 101 and a multiplexer 102. The convolution interleaver 101 is configured to perform the operation described in the above-mentioned data processing method of performing convolution interleaving on each of the n channel data streams to obtain n first data streams. The multiplexer 201 is configured to perform the operation described in the above-mentioned data processing method of multiplexing each of the K first data streams among the n first data streams to obtain one second data stream, thereby obtaining a total of m second data streams. For details, please refer to the relevant description of the convolution interleaving and multiplexing operations in the above-mentioned data processing method, and will not be repeated here.

[0530] It should be understood that the device provided in this application can also be implemented in other ways. For example, the unit division in the above-mentioned device is only a logical functional division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0531] It should be noted that, in addition to the data processing method described in the above embodiment, this application also provides another data processing method, which is described in detail below.

[0532] In this embodiment, the n channel data streams are first interleaved to obtain m target data streams. Then, the m target data streams are respectively subjected to the second FEC encoding to obtain the encoded data streams. The manner of performing the second FEC encoding on the m target data streams is the same as that described above. Figure 10 The manner of introducing step 1003 in the illustrated embodiment is similar and will not be repeated here.

[0533] In this embodiment, the channel data stream may be a PCS channel data stream or an FEC channel data stream, which is not specifically limited here. The n channel data streams are all data streams that have undergone the first FEC encoding, that is, the data streams that have undergone outer code encoding as described above, where n is an integer greater than 1 and a multiple of 4. For example, the outer code encoding may adopt RS code, and the n data streams after outer code encoding may include multiple RS code words. In practical applications, other encoding methods may also be used for outer code encoding. For ease of description, RS code words are uniformly used below to represent the code words generated after outer code encoding. It should be understood that each a code words after outer code encoding are distributed in b channel data streams, where a≤b≤n, n is divisible by b, and a is an integer greater than or equal to 1. In the above Figure 5-Figure 9 In different application scenarios shown in FIG, the values ​​of a and b may also be different. Figure 5 Taking the application scenario shown in the figure as an example, n=32, a=2, b=16, that is, every 2 code words are distributed in 16 channel data streams. Figure 6-Figure 9 The values ​​of a and b in several other application scenarios can be derived from the accompanying drawings and will not be described here one by one. Therefore, the maximum value of b is 16 and the minimum value is 4. It should be noted that the outer code length in this application is calculated in symbols, where a symbol can include one or more bits. For example, the outer code is the KP4 RS (544, 514) code used, with a code length of N = 544 symbols, and one symbol contains 10 bits.

[0534] It should be understood that the consecutive F symbols in each target data stream come from F different codewords, F> a. The consecutive F symbols in each target data stream come from at least K1 different channel data streams, and the consecutive F symbols in each target data stream come from at most K2 symbols among the n symbols aligned by n channel data streams, K1 and K2 are divisors of n, and K2 is a divisor of K1. Among them, the n symbols aligned by n channel data streams refer to the n symbols located at the same position in each channel data stream, with the above Figure 5-Figure 9 Taking the different application scenarios shown as an example, the n symbols in each column of n channel data streams are aligned, that is, the n symbols aligned by the n channel data streams can be the n symbols of one of the n channel data streams. It should also be understood that at most K3 of the consecutive F symbols in each target data stream come from the same channel data stream. An integer representing the quotient of F / K1 rounded upwards, where any two of the K3 symbols are separated by at least K4 symbols on the same channel data stream, and K4 ≥ a*N*K2 / n, where N is the codeword length. In this embodiment, b has a maximum value of 16 and a minimum value of 4. Therefore, in some possible implementations, K1 = n / 4 and K2 = n / 16.

[0535] In some possible implementations, before interleaving the n channel data streams to obtain the m target data streams, the n channel data streams may be reordered so that the n data streams are arranged in a predetermined order. For example, with 32 data streams, the 32 data streams may be arranged in a top-to-bottom order from 0 to 31. This can be easily extended to other orderings. The specific implementation is known to those skilled in the art and will not be detailed here.

[0536] In some possible implementations, before interleaving the n channel data streams to obtain the m target data streams, the n channel data streams may also be subjected to channel data alignment. The channel data alignment may be a lane de-skew process defined by existing standards, so that the data of the n channel data streams outputted therefrom are completely aligned. Alternatively, the above-mentioned "channel data alignment process" may be only channel symbol alignment, so that the data on the n channel data streams outputted therefrom are based on outer code symbol alignment, specifically, alignment based on one outer code symbol, or alignment based on multiple outer code symbols. For a detailed introduction to the channel data alignment process, please refer to the relevant description of FIG3(e) above, which will not be repeated here.

[0537] It should be noted that the interleaving process in this embodiment can be implemented in a variety of specific ways, which are introduced below respectively.

[0538] Figure 34 A flowchart of the interleaving process provided in an embodiment of the present application.

[0539] 3401. Perform convolution interleaving on n channel data streams to obtain n first data streams.

[0540] In this embodiment, after convolutional interleaving, the z consecutive symbols in each first data stream come from at least e different codewords, where z is an integer greater than 1, a≤e≤F, and e*k2≥F. At most k1 / k2 of the z consecutive symbols in each first data stream come from the same codeword.

[0541] It should be noted that the implementation method of convolution interleaving in this embodiment is the same as that in the above Figure 10The convolution interleaving method introduced in the illustrated embodiment is similar and will not be described in detail here. In one possible implementation, if the convolution interleaver shown in FIG12(a) above is adopted, the parameters of the convolution interleaver should satisfy d(p*Q+1)≥K4, so that the consecutive z=p*d symbols in the first data stream output by the convolution interleaver come from at least e different outer code words, where N is the codeword length of the outer code. In another possible implementation, if the convolution interleaver shown in FIG12(b) above is adopted, the parameters of the convolution interleaver should satisfy d(p*Q-1)≥K4, so...

Claims

1. A data processing method, characterized in that: include: Each t channel data stream among n channel data streams is grouped and interleaved to obtain s first data streams, so as to obtain a total of m first data streams, n=q*t, m=q*s, wherein n is an integer greater than 1, and n is divisible by q, and q is an integer greater than or equal to 1, and t is an integer greater than or equal to 1, and s is an integer greater than or equal to 1, and the n channel data streams are all subjected to the first forward error correction FEC encoding, and each a codeword after the first FEC encoding is distributed in b channel data streams, and a≤b≤n, and n is divisible by b, and a is greater than or an integer equal to 1, each consecutive a symbols in each channel data stream come from a different codewords, and each consecutive L1 symbols in each channel data stream come from at least a different codewords, L1=N*a / b, wherein N represents the length of the codeword, the t channel data streams include a consecutive a symbols in each channel data stream, a total of t*a symbols, the t*a symbols include Δ bits in each symbol, a total of D bits, D=Δ*t*a, the D bits are continuous in any first data stream among the s first data streams, Δ=M / s, wherein M represents the number of bits contained in a symbol; Convolution interleaving is performed on the m first data streams to obtain m second data streams.

2. The data processing method according to claim 1, characterized in that: Each consecutive d symbols in each of the first data streams come from v different codewords, and each consecutive L2 symbols in each of the first data streams come from at least v different codewords, where v is divisible by a, L2=t / s*L1, and d=D / M.

3. The method according to claim 1 or 2, characterized in that: Where n=32, 16 channel data streams located in odd channels among the n channel data streams come from the same codeword, 16 channel data streams located in even channels among the n channel data streams come from the same codeword, and the data streams located in odd channels and the data streams located in even channels among the n channel data streams come from different codewords.

4. The method according to claim 3, characterized in that Where t=8, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: Performing group interleaving on 8 channel data streams, namely, the 8*i th channel data stream, the 8*i+1 th channel data stream, the 8*i+2 th channel data stream, the 8*i+3 th channel data stream, the 8*i+4 th channel data stream, the 8*i+5 th channel data stream, the 8*i+6 th channel data stream, and the 8*i+7 th channel data stream, to obtain a first data stream, 0≤i≤3, 2 consecutive symbols, a total of 16 symbols, included in each channel data stream of the 8 channel data streams are continuous in the first data stream obtained by the group interleaving, and each consecutive 16 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and each consecutive 544 symbols come from at least 4 different codewords, The 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of each of the 16 consecutive symbols in the first data stream obtained by the group interleaving come from different code words respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of each of the 16 consecutive symbols in the first data stream obtained by the group interleaving come from different code words respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of each of the 16 consecutive symbols in the first data stream obtained by the group interleaving come from different code words respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of each of the 16 consecutive symbols in the first data stream obtained by the group interleaving come from different code words respectively.

5. The method according to claim 3, characterized in that: Where t=8, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: Performing group interleaving on 8 channel data streams, namely, the 8*i th channel data stream, the 8*i+1 th channel data stream, the 8*i+2 th channel data stream, the 8*i+3 th channel data stream, the 8*i+4 th channel data stream, the 8*i+5 th channel data stream, the 8*i+6 th channel data stream, and the 8*i+7 th channel data stream, to obtain a first data stream, 0≤i≤3, the j th group of 2 consecutive symbols, a total of 16 symbols, included in each of the 8 channel data streams are continuous in the first data stream obtained by the group interleaving, the j th group of 2 consecutive symbols included in each of the 8 channel data streams are continuous in the first data stream obtained by the group interleaving, j≥0, and each of the 16 consecutive symbols in the first data stream obtained by the group interleaving comes from at least 4 different codewords, and each consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of each consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

6. The method according to claim 3, characterized in that Where t=8, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: The 8*i-th channel data stream, the 8*i+1-th channel data stream, the 8*i+2-th channel data stream, the 8*i+3-th channel data stream, the 8*i+4-th channel data stream, the 8*i+5-th channel data stream, the 8*i+6-th channel data stream, and the 8*i+7-th channel data stream, a total of 8 channel data streams, are grouped and interleaved to obtain a first data stream, 0≤i≤3, and the j-th symbol of each channel data stream in the 8 channel data streams, a total of 8 symbols, is obtained in the grouped interleaving , j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

7. The method according to claim 1 or 2, characterized in that: Where n=32, the 16 consecutive channel data streams ordered in front of the n channel data streams come from the same code word, the 16 consecutive channel data streams ordered in the back of the n channel data streams come from the same code word, and the 16 consecutive channel data streams ordered in front of the n channel data streams and the 16 consecutive channel data streams ordered in the back come from different code words.

8. The method according to claim 7, characterized in that Where t=2, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: The i-th channel data stream and the i+16-th channel data stream are grouped and interleaved to obtain a first data stream, 0≤i<16, 2 consecutive symbols in the i-th channel data stream and 2 consecutive symbols in the i+16-th channel data stream are consecutive in the first data stream obtained by the group interleaving, and every 4 consecutive symbols in the first data stream obtained by the group interleaving come from 4 different codewords.

9. The method according to claim 7, characterized in that: Where t=2, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: The i-th channel data stream and the i+16-th channel data stream are grouped and interleaved to obtain a first data stream, 0≤i<16, the j-th group of β consecutive bits in the i-th channel data stream and the j-th group of β consecutive bits in the i+16-th channel data stream are continuous in the first data stream obtained by the group interleaving, j≥0, β is 1, 2, 4, 5, 10 or 20, and every 4 consecutive symbols in the first data stream obtained by the group interleaving come from 4 different codewords.

10. The method according to claim 7, characterized in that Where t=2, s=2, and each t channel data streams in the n channel data streams are grouped and interleaved to obtain s first data streams, including: The i-th channel data stream and the i+16-th channel data stream are grouped and interleaved to obtain the 2*i-th first data stream and the 2*i+1-th first data stream, 0≤i<16, 5 bits of each of the 4 symbols (including 2 consecutive symbols in the i-th channel data stream and 2 consecutive symbols in the i+16-th channel data stream) are continuous in the 2*i-th first data stream, and each of the 20 consecutive bits in the 2*i-th first data stream comes from 4 different codewords, and the other 5 bits of each of the 4 symbols (including 2 consecutive symbols in the i-th channel data stream and 2 consecutive symbols in the i+16-th channel data stream) are continuous in the 2*i+1-th first data stream, and each of the 20 consecutive bits in the 2*i+1-th first data stream comes from 4 different codewords.

11. The method according to claim 7, characterized in that Where t=8, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: A first data stream is obtained by performing group interleaving on 8 channel data streams, namely, the 4*i th channel data stream, the 4*i+1 th channel data stream, the 4*i+2 th channel data stream, the 4*i+3 th channel data stream, the 4*i+16 th channel data stream, the 4*i+17 th channel data stream, the 4*i+18 th channel data stream and the 4*i+19 th channel data stream, 0≤i≤3, 2 consecutive symbols, a total of 16 symbols, included in each channel data stream of the 8 channel data streams are continuous in the first data stream obtained by the group interleaving, and each consecutive 16 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, and each consecutive 544 symbols come from at least 4 different codewords. The 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords.

12. The method according to claim 7, characterized in that Where t=8, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: A total of 8 channel data streams, namely, the 4*i th channel data stream, the 4*i+1 th channel data stream, the 4*i+2 th channel data stream, the 4*i+3 th channel data stream, the 4*i+16 th channel data stream, the 4*i+17 th channel data stream, the 4*i+18 th channel data stream and the 4*i+19 th channel data stream, are grouped and interleaved to obtain a first data stream, 0≤i≤3, the j-th group of 2 consecutive symbols, totaling 16 symbols, included in each of the 8 channel data streams are continuous in the first data stream obtained by the grouping and interleaving, the j-th group of 2 consecutive symbols included in each of the 8 channel data streams are continuous in the first data stream obtained by the grouping and interleaving, j≥0, and each continuous 16 symbols in the first data stream obtained by the grouping and interleaving are from to at least 4 different codewords, and each consecutive 544 symbols come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, the 8th symbol, the 9th symbol, the 10th symbol and the 11th symbol of each consecutive 16 symbols in a first data stream obtained by the group interleaving come from different codewords respectively, and the 12th symbol, the 13th symbol, the 14th symbol and the 15th symbol of each consecutive 16 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

13. The method according to claim 7, characterized in that Where t=8, s=1, grouping and interleaving each t channel data streams among the n channel data streams to obtain s first data streams includes: A total of 8 channel data streams, namely, the 4*i th channel data stream, the 4*i+1 th channel data stream, the 4*i+2 th channel data stream, the 4*i+3 th channel data stream, the 4*i+16 th channel data stream, the 4*i+17 th channel data stream, the 4*i+18 th channel data stream and the 4*i+19 th channel data stream, are grouped and interleaved to obtain a first data stream, 0≤i≤3, and the j th symbol of each channel data stream in the 8 channel data streams, a total of 8 symbols, are included in the grouped interleaved , j≥0, every consecutive 8 symbols in the first data stream obtained by the group interleaving come from at least 4 different codewords, the 0th symbol, the 1st symbol, the 2nd symbol and the 3rd symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively, and the 4th symbol, the 5th symbol, the 6th symbol and the 7th symbol in every consecutive 8 symbols in the first data stream obtained by the group interleaving come from different codewords respectively.

14. The method according to claim 1 or 2, characterized in that: Convolutionally interleaving a first data stream to obtain a second data stream includes: A second data stream is obtained by delaying a first data stream according to p delay lines, wherein p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units of each two adjacent delay lines is Q. Each storage unit is used to store d symbols. The symbols in each channel data stream are sequentially input into the p delay lines according to the sequence numbers of the p delay lines. Each delay line inputs d symbols at a time and outputs d symbols at a time. The continuous p*d symbols in the second data stream include d symbols output by each delay line, and Q is an integer greater than or equal to 1.

15. The method according to claim 1 or 2, characterized in that: Convolutionally interleaving a first data stream to obtain a second data stream includes: A second data stream is obtained by delaying a first data stream according to p delay lines, where p is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units of each two adjacent delay lines is Q. Each storage unit is used to store 4 symbols. The symbols in each channel data stream are sequentially input into the p delay lines according to the sequence numbers of the p delay lines. Each delay line inputs 4 symbols at a time and outputs 4 symbols at a time. The continuous p*4 symbols in one of the second data streams include 4 symbols output by each delay line, and Q satisfies 4(p*Q-1)≥272 or 4(p*Q+1)≥272 or 4(p*Q-1)≥544 or 4(p*Q+1)≥544.

16. The method according to claim 15, characterized in that After performing convolution interleaving on the m first data streams to obtain m second data streams, the method further includes: The m second data streams are respectively subjected to second FEC encoding to obtain m coded data streams, and information data with a length of K symbols in each of the coded data streams comes from at most K different code words, K≥p*4.

17. The method according to claim 1 or 2, characterized in that: Convolutionally interleaving a first data stream to obtain a second data stream includes: Delaying a first data stream according to p delay lines to obtain a second data stream, wherein p is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between two adjacent delay lines is Q; Each storage unit is used to store 34 bits, and the bits in each channel data stream are sequentially input into the p delay lines according to the sequence numbers of the p delay lines, each delay line inputs 34 bits at a time and outputs 34 bits at a time, and the continuous p*34 bits in one second data stream include the 34 bits output by each delay line; or, each storage unit is used to store 68 bits, and the bits in each channel data stream are sequentially input into the p delay lines according to the sequence numbers of the p delay lines, each delay line inputs 68 bits at a time and outputs 68 bits at a time, and the continuous p*68 bits in one second data stream include the 68 bits output by each delay line.

18. A data processing device, configured to execute the method according to any one of claims 1 to 17.

19. A chip, used for executing the method according to any one of claims 1 to 17.

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