An in-memory atomic operation circuit based on SRAM and a control method thereof

Abstract

The application discloses an in-memory atomic operation circuit based on an SRAM type and a control method thereof. The circuit comprises an 8T SRAM array, a switch control circuit, near-memory computing logic, a data driving control circuit and an SRAM peripheral circuit. The control method comprises the following steps: obtaining an operation instruction type; if the operation instruction type is a normal memory instruction, switching the control mode of the circuit to an SRAM mode; if the operation instruction type is an atomic operation instruction, switching the control mode of the circuit to an atomic operation mode; if the control mode of the circuit is the atomic operation mode, performing an in-memory atomic operation until the in-memory atomic operation is completed, switching the control mode of the circuit to the SRAM mode, and performing a normal memory instruction operation. The embodiment of the application can directly complete calculation in a storage array, reduce data transmission between a storage unit and a calculation unit, improve atomic operation processing efficiency and reduce energy consumption required by data transmission. The application can be widely applied to the technical field of integrated circuit design.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to an SRAM-based in-memory atomic operation circuit and its control method. Background Technology

[0002] Current intelligent computing systems, such as CPUs, GPUs, and NPUs, primarily utilize the von Neumann architecture, which separates memory and computation units. In the von Neumann architecture, atomic operations are constrained by the memory wall problem, where a speed difference exists between memory and the processor. Memory access is slower than processor processing speed, especially for atomic operations that require frequent memory access. The slow memory access speed causes the processor to waste significant time waiting for memory data transfers. Furthermore, atomic operations frequently involve data movement and modification across multiple memory hierarchies, limiting overall system performance. Therefore, during the execution of atomic operations, due to the frequent reading, modification, and writing of data across processors and multiple memory hierarchies, traditional computing architectures and circuits are no longer sufficient to meet the demands for efficient atomic operations on large-scale data.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose an SRAM-based in-memory atomic operation circuit and its control method, which can perform calculations directly in the memory array, reduce the transmission of data between storage and computing units, improve the efficiency of atomic operation processing, and reduce the energy consumption required for data transmission.

[0005] To achieve the above objectives, one aspect of this application proposes an in-memory atomic operation circuit based on SRAM. The in-memory atomic operation circuit includes an 8T SRAM array, a switch control circuit, near-memory computation logic, a data drive control circuit, and SRAM peripheral circuitry. The SRAM peripheral circuitry includes an SRAM interface circuit, a control circuit, a row decoder, and a precharge circuit. The first output terminal of the control circuit is connected to the input terminal of the precharge circuit, the second output terminal of the control circuit is connected to the input terminal of the row decoder, the output terminal of the row decoder is connected to the input terminal of the switch control circuit, the output terminal of the switch control circuit is connected to the first input terminal of the 8T SRAM array, the output terminal of the near-memory computation logic is connected to the input terminal of the data drive control circuit, the output terminal of the data drive control circuit is connected to the second input terminal of the 8T SRAM array, and the precharge circuit is interconnected with the 8T SRAM array.

[0006] The 8T SRAM array is used to store the data generated by in-memory atomic operations and to control the calculation of the in-memory atomic operations;

[0007] The switch control circuit is used to control the switching between SRAM mode and atomic operation mode;

[0008] The near-memory computation logic is used to control the carry calculation of the in-memory atomic operations;

[0009] The data-driven control circuit is used to control several of the in-memory atomic operations.

[0010] The SRAM peripheral circuitry is used to control the data reading of the atomic operations within the memory, the data calculation of the atomic operations within the memory, and the data storage of the atomic operations within the memory.

[0011] In some embodiments, the 8T SRAM array includes a plurality of 8T SRAM cells, each 8T SRAM cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the first transistor, the drain of the fifth transistor, the drain of the eighth transistor, and the gate of the second transistor are connected. The gate of the third transistor, the source of the seventh transistor, the drain of the sixth transistor, the source of the eighth transistor, and the gate of the fourth transistor are connected. The source of the first transistor, the drain of the seventh transistor, and the drain of the second transistor are connected. The drain of the third transistor, the source of the eighth transistor, and the drain of the fourth transistor are connected.

[0012] In some embodiments, the switch control circuit includes a first NOT gate, a second NOT gate, a first NAND gate, a second NAND gate, a first delay element, and a first multiplexer. The input terminal of the first NOT gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the first input terminal of the second NAND gate, the output terminal of the first NOT gate is connected to the input terminal of the second NAND gate, the output terminal of the first NAND gate, the input terminal of the first delay element, and the first input terminal of the first multiplexer are connected, and the output terminal of the second NAND gate, the second input terminal of the first multiplexer, and the input terminal of the second NOT gate are connected.

[0013] In some embodiments, the near-memory computation logic is formed by cascading a plurality of near-memory computation units. Each near-memory computation unit includes a third NAND gate, a fourth NAND gate, a fifth NAND gate, a first AND gate, a second AND gate, and a third XNOR gate. The output of the first AND gate, the input of the third XNOR gate, and the input of the third NAND gate are connected. The output of the second AND gate is connected to the input of the fourth NAND gate. The output of the third NAND gate is connected to the first input of the fifth NAND gate, and the output of the fourth NAND gate is connected to the second input of the fifth NAND gate.

[0014] In some embodiments, the data-driven control circuit includes a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a first XOR gate, and a second XOR gate. The output of the first XOR gate is connected to the input of the third multiplexer; the input of the second multiplexer is connected to the input of the third multiplexer; the output of the second multiplexer is connected to the first input of the fourth multiplexer; the output of the third multiplexer is connected to the second input of the fourth multiplexer; the output of the fourth multiplexer, the input of the sixth multiplexer, and the input of the second XOR gate are connected; and the output of the second XOR gate is connected to the input of the fifth multiplexer.

[0015] To achieve the above objectives, another aspect of this application proposes a control method based on an SRAM-type in-memory atomic operation circuit, the control method comprising the following steps:

[0016] Get the operation instruction type;

[0017] The operation instruction type is determined. If the operation instruction type is a normal memory access instruction, the control mode of the switching circuit is SRAM mode. If the operation instruction type is an atomic operation instruction, the control mode of the switching circuit is atomic operation mode.

[0018] If the control mode of the circuit is atomic operation mode, perform in-memory atomic operations until the in-memory atomic operations are completed, then switch the control mode of the circuit to SRAM mode and perform normal memory access instruction operations.

[0019] In some embodiments, the atomic operation modes include in-memory atomic logical AND operation, in-memory atomic logical OR operation, in-memory atomic logical XOR operation, in-memory atomic arithmetic addition operation, in-memory atomic arithmetic maximum value operation, in-memory atomic arithmetic minimum value operation, and in-memory atomic arithmetic swap operation.

[0020] In some embodiments, the atomic operation control methods for the in-memory atomic AND operation, the in-memory atomic OR operation, and the in-memory atomic XOR operation are the same, as detailed below:

[0021] The first input signal, the second input signal and the first switching control signal are pulled low, and the internal atomic operation circuit is in the on state. QB and Q are both 0, where Q represents the data storage node and QB represents the inverting node.

[0022] The second switching control signal is pulled low, the first input signal is restored to the ground state, the second input signal is restored to the high level state, and both QB and Q are 0.

[0023] The first switching control signal is pulled high to charge QB, where QB is 1 and Q is 0.

[0024] The second switching control signal is pulled high to keep QB at 1 and Q at 0. The in-memory atomic operation circuit is in latch state to complete the in-memory atomic logic AND operation, the in-memory atomic logic OR operation, and the in-memory atomic logic XOR operation.

[0025] In some embodiments, the atomic operation control method for the in-memory atomic arithmetic addition operation is specifically as follows:

[0026] Get the first operand and the second operand;

[0027] The first operand is stored in the Mth row of an 8T SRAM array;

[0028] Perform an in-memory atomic logic XOR operation on the first operand and the second operand to obtain the operand XOR calculation result;

[0029] Obtain the XOR result of the operands and the inverse result of the XOR result of the operands, and obtain the output signal calculation result of the near-memory logic of the atomic addition operation through near-memory logic calculation;

[0030] The in-memory atomic arithmetic addition operation is completed by performing an XOR operation between the output signal calculation result of the near-memory logic of the atomic addition operation and the XOR calculation result of the operand.

[0031] In some embodiments, the atomic operation control methods for the in-memory atomic arithmetic maximum value operation and the in-memory atomic arithmetic minimum value operation are the same, as detailed below:

[0032] Based on the first operand and the second operand, perform an atomic XOR operation to obtain the result of the atomic XOR operation of the two operands;

[0033] The result of the atomic XOR operation of the two operands and the inverse result of the atomic XOR operation of the two operands are obtained, and the BMAX signal is obtained by near-memory logic calculation.

[0034] Based on the BMAX signal and the atomic maximum value operation indication signal (AMO_MAX), an XOR operation is performed to complete the in-memory atomic arithmetic maximum value operation and the in-memory atomic arithmetic minimum value operation.

[0035] The embodiments of this application include at least the following beneficial effects: This application provides an in-memory atomic operation circuit and its control method based on SRAM. The scheme includes an 8T SRAM array with storage and computing functions, and control and auxiliary circuits mainly including a switch control circuit, a data drive control circuit, and near-memory computing logic. When writing to the 8T SRAM array, data can be easily written by simply stopping the latching state of two inverters. The atomic operation of "read-modify-write" on the same memory unit can be completed without additional storage space, reducing the transmission of data between storage and computing units and improving the efficiency of atomic operation processing. The in-memory atomic operation circuit based on field-memory SRAM completes the calculation directly in the storage array, avoiding frequent data movement across the memory hierarchy in atomic operations, reducing the energy consumption required for data transmission, and achieving energy optimization and saving. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of an SRAM-based in-memory atomic operation circuit provided in an embodiment of this application;

[0037] Figure 2 This is a flowchart illustrating the steps of a control method for an SRAM-based in-memory atomic operation circuit provided in an embodiment of this application.

[0038] Figure 3 This is a schematic diagram illustrating the principle of in-memory atomic operations of SRAM provided in the embodiments of this application;

[0039] Figure 4 This is a schematic diagram of the switch control circuit provided in the embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the data-driven control circuit provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram of the near-memory computing logic circuit provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of in-memory atomic AND, OR, and XOR logic operations provided in the embodiments of this application;

[0043] Figure 8 This is a schematic diagram of the in-memory atomic addition operation provided in an embodiment of this application;

[0044] Figure 9 This is a schematic diagram of the in-memory arithmetic maximum value operation and the in-memory arithmetic minimum value operation provided in the embodiments of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0046] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0047] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0049] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0050] With the widespread adoption of new parallel applications such as artificial intelligence (AI) algorithms, atomic operations have become increasingly important as a key means of achieving concurrent processing in AI algorithms. In these new parallel applications, atomic operations play a crucial role in multithreading, concurrent programming, and distributed systems. In AI algorithms, especially in multithreaded environments, concurrent processing of multiple tasks or computational entities is essential. Because atomic operations ensure the atomicity of operations on shared data—either all operations succeed or all fail—they can be used to control concurrent access to shared resources, ensuring correct collaboration between multiple tasks and preventing data corruption or inconsistencies. Therefore, in parallel computing, atomic operations can be used to synchronize concurrently executing tasks or threads, guaranteeing the correctness of computations and the accuracy of results. This is crucial for maintaining data consistency and avoiding race conditions, especially in large-scale data processing and distributed computing.

[0051] However, with the increasing demand for atomic operations in fields such as big data and artificial intelligence, traditional computing architectures and circuits are struggling to meet the requirements for efficient atomic operations on large-scale data. Firstly, the difference in data transfer speed between the processor and memory (the memory wall) creates a bottleneck, limiting the improvement of atomic operation speed. Secondly, the frequent data transfers and computations in traditional computing architectures consume a significant amount of energy.

[0052] In view of this, this application provides an SRAM-based in-memory atomic operation circuit, which aims to integrate the storage unit and the computing unit to improve the efficiency and energy consumption of data processing. It designs an 8T SRAM in-memory computing unit to adapt to the indivisible "read-modify-write" characteristics of atomic operations, supports flexible switching between SRAM mode and atomic operation mode, fully supports in-situ storage and in-memory computation of various atomic operations, realizes comprehensive in-memory atomic logic operations and in-memory atomic arithmetic operations, and reuses near-memory computing logic, significantly improving the execution efficiency of atomic operations, reducing circuit area cost, and enhancing overall performance, system flexibility, and functionality. It can be applied to various processor architecture designs.

[0053] Reference Figure 1 , Figure 1 A flowchart of an SRAM-based in-memory atomic operation circuit is provided as an embodiment of the present invention, referring to... Figure 1The circuit includes an 8T SRAM array, a switch control circuit, near-memory computing logic, a data drive control circuit, and SRAM peripheral circuits. The SRAM peripheral circuits include an SRAM interface circuit, a control circuit, a row decoder, and a precharge circuit. The first output of the control circuit is connected to the input of the precharge circuit, the second output of the control circuit is connected to the input of the row decoder, the output of the row decoder is connected to the input of the switch control circuit, the output of the switch control circuit is connected to the first input of the 8T SRAM array, the output of the near-memory computing logic is connected to the input of the data drive control circuit, the output of the data drive control circuit is connected to the second input of the 8T SRAM array, and the precharge circuit is interconnected with the 8T SRAM array.

[0054] In this embodiment, the in-memory atomic operation circuit structure based on field-accessible SRAM constructed by this invention has a size of 256x512 and is divided into SRAM mode and atomic operation mode (AMO mode). The circuit includes an 8T SRAM array, a switching control circuit, near memory computation logic, a data-driven control circuit, and conventional SRAM peripheral circuitry. The conventional SRAM peripheral circuitry includes an SRAM interface circuit, a control circuit, a row decoder, and a precharge circuit. The 8T SRAM cells are responsible for storing the data for atomic operations and performing in-memory atomic operations; the switching control circuit is responsible for switching between SRAM mode and AMO mode. The near memory computation logic handles carry calculations during atomic addition, atomic maximum value calculation, and atomic minimum value calculation. The data-driven control circuit manages the memory array to support various atomic operations. The SRAM peripheral circuitry is responsible for controlling and managing the in-memory computation operations of the computation unit, ensuring the correct reading, calculation, and storage of data.

[0055] Specifically, such as Figure 3As shown, in AMO mode, it supports seven atomic operations: in-memory atomic AND, in-memory atomic OR, in-memory atomic XOR, in-memory atomic arithmetic addition, in-memory atomic arithmetic maximum value, in-memory atomic arithmetic minimum value, and in-memory atomic arithmetic swap. According to the RI SC-V manual's description of atomic operations, in this mode, the word at address x[rs1] in memory is marked as t. A specified operation is performed on t and x[rs2], the result is updated to the address of x[rd], and x[rd] is set to the sign-extended t. In atomic mode, the circuit receives 16 x[rs2] (x[rs2]0~x[rs2]15) from external input. Based on the selected atomic operation instruction, it performs the corresponding atomic operation on the 16 words at address x[rs1] in the memory location and updates the result to the address of x[rs1].

[0056] in, Figure 3 The meanings of the input and output signals are shown in Table 1:

[0057] Table 1. Meaning of Data Signals in Memory Atomic Operation Circuit

[0058]

[0059]

[0060] An 8T SRAM array is used to store data generated by in-memory atomic operations and to control the computation of in-memory atomic operations;

[0061] In this embodiment, the 8T SRAM array includes several 8T SRAM cells. Each 8T SRAM cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the first transistor, the drain of the fifth transistor, the drain of the eighth transistor, and the gate of the second transistor are connected. The gate of the third transistor, the source of the seventh transistor, the drain of the sixth transistor, the source of the eighth transistor, and the gate of the fourth transistor are connected. The source of the first transistor, the drain of the seventh transistor, and the drain of the second transistor are connected. The drain of the third transistor, the source of the eighth transistor, and the drain of the fourth transistor are connected.

[0062] Specifically, in the circuit, the field-memory 8T SRAM cell is as follows: Figure 1The area highlighted in the center is shown. This cell adds two NMOS transistors (M7 and M8) to a conventional 6T SRAM cell to control the switching between SRAM mode and AMO mode, controlled by Ctrl_L and Ctrl_R. Furthermore, IN1 and IN2 are connected to the source or drain of M3 and M4 respectively for implementing internal logic operations. Unlike traditional 6T SRAM, the two coupled inverters in this field-accessible 8T SRAM are controlled by M7 and M8. During a write operation, data can be easily written simply by terminating the latching state of the two inverters. All eight transistors are of minimum size.

[0063] When the circuit is in SRAM mode, IN1 and IN2 are held at VDD and VSS respectively, and Ctrl_L and Ctrl_R are both logic "1", turning on the two middle NMOS transistors of the 8-transistor unit. Based on the input address, a single 512-bit data read / write operation can be completed.

[0064] The switch control circuit is used to control the switching between SRAM mode and atomic operation mode;

[0065] In this embodiment, the switch control circuit includes a first NOT gate (NOT1), a second NOT gate (NOT2), a first NAND gate (NAND1), a second NAND gate (NAND2), a first delay element (DELAY), and a first multiplexer (MUX1). The input terminal of the first NOT gate is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is connected to the first input terminal of the second NAND gate, the output terminal of the first NOT gate is connected to the input terminal of the second NAND gate, the output terminal of the first NAND gate, the input terminal of the first delay element, and the first input terminal of the first multiplexer are connected, and the output terminal of the second NAND gate, the second input terminal of the first multiplexer, and the input terminal of the second NOT gate are connected.

[0066] Specifically, such as Figure 4 As shown, the switch control circuit controls Ctrl_L and Ctrl_R in the memory array to switch between SRAM mode and AMO mode, supporting flexible mode configuration. AMO_MODE is a short pulse input signal provided by the control circuit. The components of the switch control circuit mainly include AND gates, OR gates, NAND gates, delay elements, and multiplexers. These perform logical operations and selection on the input signals, ultimately outputting the switch control signal. Figure 4 The meanings of the input and output signals are shown in Table 2.

[0067] Table 2. Meaning of Data Signals in Switch Control Circuit

[0068]

[0069]

[0070] Near-memory computation logic is used to control carry calculations in in-memory atomic operations;

[0071] In this embodiment, the near-memory computation logic is formed by cascading several near-memory computation units. The near-memory computation unit includes a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a first AND gate SA1, a second AND gate SA2, and a third XNOR gate XNOR3. The output of the first AND gate, the input of the third XNOR gate, and the input of the third NAND gate are connected. The output of the second AND gate is connected to the input of the fourth NAND gate. The output of the third NAND gate is connected to the first input of the fifth NAND gate. The output of the fourth NAND gate is connected to the second input of the fifth NAND gate.

[0072] Specifically, the data-driven control circuit is used to manage IN1 and IN2 in the memory array to support various atomic operations. The data-driven control circuit supporting 32-bit atomic operation calculations includes, for example,... Figure 6 As shown. The main components of the data-driven control circuit include AND gates, OR gates, inverters, and multiplexers. These select the input signal, perform logical operations on the signal, and ultimately control the output signal. Figure 6 The meanings of the input and output signals are shown in Table 3.

[0073] Table 3. Meaning of Data Signals in Data-Driven Control Circuit

[0074]

[0075]

[0076] The data-driven control circuit is used to control IN1 and IN2. The functions of OP2, CIN, and OP1_B in different operations are as follows:

[0077] OP2 is used for: single-cycle logic operations (AND / OR / XOR); XORing in the first cycle of ADD / MAX / MIN operations; if the comparison result in MAX / MIN is OP1, then OP2 needs to be XORed again in the third cycle, that is, OP1 = OP1^OP2^OP2.

[0078] CIN is used to perform an XOR operation on the third cycle of the ADD operation, completing A^B^CIN = SUM.

[0079] OP1_B is used in MAX / MIN. If the comparison result is OP2, then OP2 needs to be XORed again in the third cycle, that is, OP2 = OP1^OP2_B^OP1_B.

[0080] The data-driven control circuit is used to control several in-memory atomic operations;

[0081] In this embodiment, the data-driven control circuit includes a second multiplexer MUX2, a third multiplexer MUX3, a fourth multiplexer MUX4, a fifth multiplexer MUX5, a sixth multiplexer MUX6, a first XNOR gate XNOR1, and a second XNOR gate XNOR2. The output of the first XNOR gate is connected to the input of the third multiplexer, the input of the second multiplexer is connected to the input of the third multiplexer, the output of the second multiplexer is connected to the first input of the fourth multiplexer, the output of the third multiplexer is connected to the second input of the fourth multiplexer, the output of the fourth multiplexer, the input of the sixth multiplexer, and the input of the second XNOR gate are connected. The output of the second XNOR gate is connected to the input of the fifth multiplexer.

[0082] Specifically, such as Figure 5 As shown, the component structure of the near-in-memory computing logic circuit includes combinations of multiple NAND gates, AND gates, OR gates, and inverters, forming a cascaded connection of multiple CCL_1b units, used to perform carry calculations during atomic addition or atomic comparison operations. The signals are shown in Table 4.

[0083] Table 4. Meaning of Data Signals in Data-Driven Control Circuit

[0084]

[0085] SRAM peripheral circuitry is used to control data reading, data computation, and data storage of atomic operations within the memory.

[0086] Please see Figure 2 This application also provides a control method for an SRAM-based in-memory atomic operation circuit, which can implement the above-mentioned SRAM-based in-memory atomic operation circuit. The control method includes the following steps:

[0087] S100, Obtain the operation instruction type;

[0088] S200. Determine the type of operation instruction. If the operation instruction type is a normal memory access instruction, the control mode of the switching circuit is SRAM mode. If the operation instruction type is an atomic operation instruction, the control mode of the switching circuit is atomic operation mode.

[0089] It should be noted that in some embodiments, atomic operation modes include in-memory atomic logical AND operation, in-memory atomic logical OR operation, in-memory atomic logical XOR operation, in-memory atomic arithmetic addition operation, in-memory atomic arithmetic maximum value operation, in-memory atomic arithmetic minimum value operation, and in-memory atomic arithmetic swap operation.

[0090] When the external signal AMO<2:0> equals 000, the circuit is in SRAM mode and can perform read and write operations. The operations corresponding to AMO<2:0> are shown in Table 5.

[0091] Table 5 External Signal Operation Table

[0092]

[0093] Additionally, it should be noted that the SRAM circuit mode is the same as that of conventional SRAM. The main focus of this embodiment is the implementation of AMO mode. In AMO mode, AND, OR, XOR, and SWAP operations are all completed in one cycle. The SWAP operation can be simply considered as writing operand 2 to the address; SWAP is writing operand 2 to the corresponding address, thus also requiring one cycle to complete the write operation. ADD, MAX, and MIN operations, however, require three cycles to complete. This design aims to achieve efficient support for different operations, ensuring the flexibility and performance of the circuit.

[0094] In some specific embodiments, step S200 may include:

[0095] S210. The first input signal, the second input signal, and the first switching control signal are pulled low, and the in-memory atomic operation circuit is in the conducting state, with QB and Q both being 0, where Q represents the data storage node and QB represents the inverting node; the second switching control signal is pulled low, the first input signal is restored to the ground state, and the second input signal is restored to the high-level state, with QB and Q both being 0; the first switching control signal is pulled high, charging QB, making QB 1 and Q 0; the second switching control signal is pulled high, maintaining the state of QB being 1 and Q being 0, and the in-memory atomic operation circuit is in the latching state, completing the in-memory atomic logic AND operation, the in-memory atomic logic OR operation, and the in-memory atomic logic XOR operation.

[0096] In this embodiment, during logic operations, different IN1 (the first input signal) and IN2 (the second input signal) correspond to different operations, as shown in Table 6. Figure 7 Here's an example of an atomic AND operation, where operand 1 is 1 and operand 2 is 0. Therefore, Q needs to be replaced from 1 to 0, which is the result of the 1 AND 0 operation. The operation flow is as follows... Figure 7 As shown. The process for other logical operations (AND / OR / XOR) is the same, and all logical operations are completed within one cycle.

[0097] Table 6. Examples of Atoms and Operations

[0098]

[0099] Reference Figure 7 When performing an Atomic AND (1 AND 0 = 0) operation, it is divided into four stages, during which the word line is in the off state.

[0100] Figure 7 The number ① in the diagram indicates that both IN1 and IN2 are pulled low, and CTRL_L, the first switching control signal, is pulled low. Since QB is 0, the PMOS in the upper right corner is turned on, and the SRAM latch state is disrupted, causing point Q to discharge to IN1, resulting in Q becoming 0.

[0101] Figure 7 The sequence number ② in the text indicates: Next, pull CTRL_R low, which is the second switching control signal. At this time, CTRL_L and CTRL_R are both low level, and IN1 and IN2 are restored to VDD and VSS respectively. At this time, the state is two independent inverters, and Q and QB are both 0.

[0102] Figure 7 The number ③ in the text means: when CTRL_L is pulled high and CTRL_R is kept low, QB will be charged to 1 by VDD, so Q is 0 and QB is 1;

[0103] Figure 7 In the sequence number ④, it means: pull CTRL_R high. At this time, both CTRL_L and CTRL_R are high, restoring the latch state of SRAM. Q is 0 and QB is 1, completing the function 1AND 0=0, and successfully rewriting the value stored in SRAM.

[0104] S220. Obtain the first operand and the second operand; set the first operand to be stored in the Mth row of the 8T SRAM array; perform an in-memory atomic logic XOR operation on the first operand and the second operand to obtain the operand XOR calculation result; obtain the operand XOR calculation result and the inverted result of the operand XOR calculation result, and obtain the output signal calculation result of the near-memory logic of the atomic addition operation through near-memory logic calculation; perform an XOR operation between the output signal calculation result of the near-memory logic of the atomic addition operation and the operand XOR calculation result to complete the in-memory atomic arithmetic addition operation.

[0105] In this embodiment, the addition operation requires 3 cycles to complete, such as Figure 8 As shown.

[0106] Assume that A, the first operand, is stored in the m-th row.

[0107] The first cycle completes A^B through an atomic XOR operation, where B represents the second operand and A^B represents the result of the operand XOR calculation.

[0108] The second cycle completes the CIN calculation. Specifically, it reads A^B and ~(A^B) and completes the CIN calculation for each column through the near-memory logic. ~(A^B) represents the inverted result of the operand XOR calculation. The CIN calculation represents the calculation result of the output signal of the near-memory logic of the atomic addition operation.

[0109] In the third cycle, CIN is XORed with A^B in the m-th row to obtain Sum = A^B^Cin.

[0110] S230. Based on the first operand and the second operand, perform an atomic XOR operation to obtain the result of the atomic XOR operation of the two operands; obtain the result of the atomic XOR operation of the two operands and the inverse result of the result of the atomic XOR operation of the two operands, and obtain the BMAX signal through near-memory logic calculation, wherein the BMAX signal is a larger value indicator signal, and when the value is 1, it indicates that the second operand B is the larger value at this time; according to the BMAX signal and the atomic maximum value operation indicator signal (AMO_MAX), perform an XOR operation to complete the in-memory atomic arithmetic maximum value operation and the in-memory atomic arithmetic minimum value operation.

[0111] In this embodiment, when performing atomic MAX / MIN operations, we use signed subtraction to implement the comparison. First, we invert each bit of the input OP2 and set CIN[0] to 1, so that the addition operation is transformed into the subtraction operation OP1-OP2.

[0112] When finding the maximum value, B is larger in the following two cases, otherwise A is larger. The opposite is true when finding the minimum value.

[0113] The first case is when A

[31] ^~B

[31] =0 and ~B

[31] =1, that is, the sign bit of A is 1 and the sign bit of B is 0.

[0114] The second case is when A

[31] ^~B

[31] =1 and CIN

[31] =0, that is, the sign bits are the same, and SUM

[31] =A

[31] ^~B

[31] ^CIN

[31] =1, which means that the subtraction result is negative, that is, OP2 is larger.

[0115] The operation of finding the maximum / minimum value of an atom requires three cycles to complete, such as... Figure 9 As shown.

[0116] The first cycle performs an atomic XOR operation to obtain A^~B.

[0117] The second cycle completes the CIN calculation, reads A^~B and ~(A^~B), calculates the CIN corresponding to each column through near-memory logic, and obtains the BMAX signal. A signal of 1 indicates that B is larger.

[0118] The third cycle performs an XOR operation on BMAX signal and AMO_MAX (1 represents atom MAX, 0 represents atom MIN) to ~B or ~A, because A^~B^~A=B, A^~B^~B=A.

[0119] S300. If the control mode of the circuit is atomic operation mode, execute in-memory atomic operations until the in-memory atomic operations are completed, then switch the control mode of the circuit to SRAM mode and execute ordinary memory access instruction operations.

[0120] Therefore, the control method of the in-memory atomic operation circuit of the present invention is specifically as follows:

[0121] 1) Receiving operation instructions: First, the operation instruction type is received from the processor, which can be divided into atomic operation instructions and ordinary memory access instructions.

[0122] 2) Mode Determination and Switching: Based on the type of operation instruction, the system determines the required mode for the current operation: whether it's the standard SRAM mode or AMO (Atomic Operation) mode. The switch control circuit then switches between SRAM and AMO modes via control signals (Ctrl_L and Ctrl_R) based on the determination result. This process ensures that the circuit can flexibly switch between different modes, supporting various types of operations.

[0123] 3) Executing Atomic Operations: After entering AMO mode, the data-driven control circuit receives specific atomic operation instructions (such as atomic logical AND, atomic increment, atomic compare and swap, etc.). The data-driven control circuit controls M7 and M8 in the 8T SRAM cells to execute the corresponding logical operations. IN1 and IN2 are connected to the source or drain terminals of M3 and M4 to cooperate with the control and realize the logical operations. The near-memory calculation logic generates carry and comparison signals as needed to assist in the execution of atomic arithmetic operations.

[0124] 4) Operation Execution and Result Return: During the execution of atomic operations, the indivisibility of the operation is ensured; it either succeeds completely or fails completely, avoiding partial execution. After the atomic operation is completed, the result is written back to the original storage unit to ensure data consistency and integrity.

[0125] 5) Mode Recovery and Operation Completion: After the operation is completed, the switch control circuit switches the mode back to the normal SRAM mode, restoring the system to normal operation. After the operation is completed, the system can continue to process subsequent regular read / write operations or other atomic operations.

[0126] In summary, the embodiments of the present invention differ from the prior art in the following technical aspects:

[0127] 1) In view of the characteristic that atomic operations need to read data, perform calculations and then write the results back to the original address, this embodiment of the invention designs an 8T SRAM storage unit and its control and auxiliary circuits. The calculation results can be stored in the bit unit in the field without the need for additional storage space. This feature is designed to efficiently complete various complex atomic operations.

[0128] 2) In this embodiment of the invention, two NMOS transistors are added to the conventional 6T SRAM cell to support the switching between SRAM mode and atomic operation mode (AMO mode). The conventional SRAM mode and atomic operation mode can be flexibly configured without affecting the conventional functions of the original SRAM array.

[0129] 3) This invention provides full support for common atomic operation types in SRAM memory arrays, including a series of in-memory atomic logic operations and in-memory atomic arithmetic operations. In-memory atomic arithmetic operations such as in-memory arithmetic addition, in-memory arithmetic maximum / minimum value calculation, and in-memory arithmetic swapping can be completed in just three cycles, while in-memory logical AND, logical OR, and logical XOR operations can be completed in a single cycle. Furthermore, the circuit reuses near-memory computation logic to implement in-memory logical AND operations, in-memory arithmetic maximum / minimum value calculations, etc., reducing circuit area overhead and improving overall performance and efficiency.

[0130] The embodiments of the present invention have the following beneficial effects:

[0131] 1) In terms of computational efficiency, the in-memory atomic operation circuit based on field-of-storage SRAM integrates data storage and computation functions, reduces data transfer between storage and computation units, and improves atomic operation processing efficiency.

[0132] 2) In terms of energy consumption optimization, the in-memory atomic operation circuit based on field-of-memory SRAM performs calculations directly in the memory array, avoiding frequent data movement across the memory hierarchy for atomic operations, reducing the energy consumption required for data transmission, and achieving energy consumption optimization and saving.

[0133] 3) In terms of computing density, the in-memory atomic operation circuit based on field-accessible SRAM achieves higher computing density, that is, more computing and storage units are integrated in a unit area, thereby improving the utilization of hardware resources.

[0134] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0135] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. An in-memory atomic operation circuit based on SRAM type, characterized by, The in-memory atomic operation circuit comprises an 8T SRAM array, a switch control circuit, near-memory computing logic, a data driving control circuit and an SRAM peripheral circuit, the SRAM peripheral circuit comprises an SRAM interface circuit, a control circuit, a row decoder and a precharge circuit, a first output end of the control circuit is connected with an input end of the precharge circuit, a second output end of the control circuit is connected with an input end of the row decoder, an output end of the row decoder is connected with an input end of the switch control circuit, an output end of the switch control circuit is connected with a first input end of the 8T SRAM array, an output end of the near-memory computing logic is connected with an input end of the data driving control circuit, an output end of the data driving control circuit is connected with a second input end of the 8T SRAM array, and the precharge circuit and the 8T SRAM array are connected with each other, wherein: The 8T SRAM array is used for storing data generated by in-memory atomic operation and controlling the calculation of the in-memory atomic operation; The switch control circuit is used for controlling the switching between the SRAM mode and the atomic operation mode; The near-memory computing logic is used for controlling the carry calculation of the in-memory atomic operation; The data driving control circuit is used for controlling a plurality of in-memory atomic operations; The SRAM peripheral circuit is used for controlling the data reading of the in-memory atomic operation, controlling the data calculation of the in-memory atomic operation and controlling the data storage of the in-memory atomic operation; The near-memory computing logic is formed by cascading a plurality of near-memory computing units, and each near-memory computing unit comprises a third NAND gate, a fourth NAND gate, a fifth NAND gate, a first AND gate, a second AND gate and a third NOR gate, wherein an output end of the first AND gate, an input end of the third NOR gate and an input end of the third NAND gate are connected, an output end of the second AND gate and an input end of the fourth NAND gate are connected, an output end of the third NAND gate and a first input end of the fifth NAND gate are connected, and an output end of the fourth NAND gate and a second input end of the fifth NAND gate are connected.

2. The in-memory atomic operation circuit of claim 1, wherein, The 8T SRAM array comprises a plurality of 8T SRAM units, and each 8T SRAM unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, wherein a gate of the first transistor, a drain of the fifth transistor, a drain of the eighth transistor and a gate of the second transistor are connected, a gate of the third transistor, a source of the seventh transistor, a drain of the sixth transistor, a source of the eighth transistor and a gate of the fourth transistor are connected, a source of the first transistor, a drain of the seventh transistor and a drain of the second transistor are connected, and a drain of the third transistor, a source of the eighth transistor and a drain of the fourth transistor are connected.

3. The in-memory atomic operation circuit of claim 1, wherein, The switch control circuit comprises a first NOT gate, a second NOT gate, a first NAND gate, a second NAND gate, a first delay element and a first multiplexer, an input end of the first NOT gate is connected with a first input end of the first NAND gate, a second input end of the first NAND gate is connected with a first input end of the second NAND gate, an output end of the first NOT gate is connected with an input end of the second NAND gate, an output end of the first NAND gate, an input end of the first delay element and a first input end of the first multiplexer are connected, an output end of the second NAND gate, a second input end of the first multiplexer and an input end of the second NOT gate are connected.

4. The in-memory atomic operation circuit of claim 1, wherein, The data driving control circuit comprises a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a first NOR gate and a second NOR gate, wherein an output end of the first NOR gate is connected with an input end of the third multiplexer, an input end of the second multiplexer is connected with an input end of the third multiplexer, an output end of the second multiplexer is connected with a first input end of the fourth multiplexer, an output end of the third multiplexer is connected with a second input end of the fourth multiplexer, an output end of the fourth multiplexer, an input end of the sixth multiplexer and an input end of the second NOR gate are connected, an output end of the second NOR gate is connected with an input end of the fifth multiplexer.

5. A control method applied to the in-memory atomic operation circuit based on the SRAM type according to any one of claims 1 to 4, characterized in that, The control method comprises the following steps: acquiring an operation instruction type; judging the operation instruction type, if the operation instruction type is a normal memory access instruction, switching the control mode of the circuit to an SRAM mode, if the operation instruction type is an atomic operation instruction, switching the control mode of the circuit to an atomic operation mode; if the control mode of the circuit is the atomic operation mode, performing an in-memory atomic operation until the in-memory atomic operation is completed, switching the control mode of the circuit to the SRAM mode and performing a normal memory access instruction operation.

6. The method of claim 5, wherein, The atomic operation mode comprises an in-memory atomic logical AND operation, an in-memory atomic logical OR operation, an in-memory atomic logical XOR operation, an in-memory atomic arithmetic addition operation, an in-memory atomic arithmetic maximum value operation, an in-memory atomic arithmetic minimum value operation and an in-memory atomic arithmetic exchange operation.

7. The method of claim 6, wherein, The atomic operation control modes of the in-memory atomic logical AND operation, the in-memory atomic logical OR operation and the in-memory atomic logical XOR operation are the same, and are as follows: performing pull-down processing on a first input signal, a second input signal and a first switch control signal, the in-memory atomic operation circuit is in a conduction state, QB and Q are both 0, wherein Q represents a data storage node and QB represents an inverted node; performing pull-down processing on a second switch control signal, the first input signal returns to a ground state, the second input signal returns to a high voltage level state, QB and Q are both 0; performing pull-up processing on the first switch control signal, charging QB, QB is 1 and Q is 0; The second switch control signal is pulled high, keeping QB at 1 and Q at 0, and the in-memory atomic operation circuit is in a latching state, completing the in-memory atomic logic and operation, the in-memory atomic logic or operation and the in-memory atomic logic exclusive or operation.

8. The method of claim 6, wherein, The atomic operation control mode of the in-memory atomic arithmetic addition operation is specifically as follows: Obtain a first operand and a second operand; Set the first operand to be stored in the Mth row of the 8T SRAM array; Perform an in-memory atomic logic exclusive or operation on the first operand and the second operand to obtain an operand exclusive or calculation result; Obtain the operand exclusive or calculation result and the negation result of the operand exclusive or calculation result, and perform near-memory logic calculation to obtain the output signal calculation result of the near-memory logic of the atomic addition operation; Perform an exclusive or operation on the output signal calculation result of the near-memory logic of the atomic addition operation and the operand exclusive or calculation result to complete the in-memory atomic arithmetic addition operation.

9. The method of claim 8, wherein, The atomic operation control modes of the in-memory atomic arithmetic maximum value operation and the in-memory atomic arithmetic minimum value operation are the same, and are specifically as follows: Based on the first operand and the second operand, perform an atomic exclusive or operation to obtain an atomic exclusive or operation result of the two operands; Obtain the atomic exclusive or operation result of the two operands and the negation result of the atomic exclusive or operation result of the two operands, and perform near-memory logic calculation to obtain a BMAX signal; According to the BMAX signal and an atomic maximum value operation instruction signal, perform an exclusive or operation to complete the in-memory atomic arithmetic maximum value operation and the in-memory atomic arithmetic minimum value operation.

Images