A packaging substrate and packaging device

Abstract

This application provides a packaging substrate and a packaging device. The packaging substrate includes multiple conductive layers stacked together and an insulating layer formed between two adjacent conductive layers. Multiple conductive vias in the insulating layer connect to two adjacent conductive layers. The distance between the conductive side and the reference side of each conductive layer varies in an ascending and descending order along a predetermined direction, which is the same as the direction from the printed circuit board to the die. The packaging substrate can balance the current on the solder balls of the ball grid array in the die-covered and non-die-covered areas, improving the solder ball utilization rate of the ball grid array in the non-die-covered area.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and packaging device. Background Technology

[0002] In chip packaging design, the die is connected to the top of the package substrate via die bumps, and the bottom of the package substrate is connected to the printed circuit board (PCB) via a ball grid array (BGA). However, the current on the solder balls in different areas of the ball grid array varies. When the current on the solder balls in the non-differentiated areas of the ball grid array is too high, those solder balls may melt, leading to short circuits and other contact problems.

[0003] In related technologies, the packaging substrate includes multiple conductive layers stacked together, with an insulating layer between adjacent conductive layers. This insulating layer has conductive vias for connecting the two adjacent conductive layers. However, since the die is the load terminal, the total thickness of the conductive and insulating layers and the density of conductive vias in the die-covered area are typically greater than those in the non-die-covered area. This results in a lower impedance of the packaging substrate in the die-covered area and a higher impedance in the non-die-covered area. Consequently, the current on the solder balls in the ball grid array is higher in the die-covered area, while the current on the solder balls in the non-die-covered area is lower. Therefore, the utilization rate of the solder balls in the non-die-covered area of ​​the ball grid array is low. Summary of the Invention

[0004] The purpose of this application is to provide a packaging substrate and packaging device to improve the utilization rate of solder balls in the non-die-covered area of ​​the ball grid array while balancing the current on the solder balls in the die-covered and non-die-covered areas of the ball grid array.

[0005] In a first aspect, this application provides a packaging substrate. The packaging substrate includes: a plurality of conductive layers stacked together and an insulating layer formed between two adjacent conductive layers. The insulating layer has a plurality of conductive vias, which connect to two adjacent conductive layers.

[0006] The lowest conductive layer among the multiple conductive layers is used to connect with the printed circuit board on which the power supply device is provided, a portion of the uppermost conductive layer among the multiple conductive layers is used to connect with the die, each conductive layer has a conductive side facing the direction of the power supply device, and the power supply device has a reference side facing the direction of the multiple conductive layers.

[0007] The distance between the conductive side and the reference side of each conductive layer varies along a preset direction in an order of increasing and then decreasing, and the preset direction is the same as the direction from the printed circuit board to the bare die.

[0008] When the above technical solution is adopted, the packaging substrate includes multiple conductive layers stacked together, and an insulating layer is disposed between two adjacent conductive layers. The insulating layer has multiple conductive vias that can connect to two adjacent conductive layers. Therefore, when the lowest conductive layer among the multiple conductive layers is used to connect with a printed circuit board with a power supply device, and a portion of the uppermost conductive layer among the multiple conductive layers of the packaging substrate is used to connect with a die, the power supply device can supply power to the die through the conductive vias between each conductive layer and two adjacent conductive layers.

[0009] When each conductive layer has a conductive side facing the direction of the power supply device, and the power supply device has a reference side facing the directions of multiple conductive layers, the related technologies use a scheme where each conductive layer is laid out across the entire horizontal surface of the package substrate. This application reduces the overall area of ​​the solder balls projected onto the conductive layers in the non-die-covered areas (i.e., the sum of the projected areas of the solder balls in the non-die-covered areas across all conductive layers) by limiting the distance between the conductive side and the reference side of each conductive layer to vary along a preset direction in an order from small to large and then from large to small. In this case, the overall impedance of the solder balls in the non-die-covered areas of the ball grid array increases, thereby causing the current in the solder balls in both the die-covered and non-die-covered areas of the ball grid array to tend to be balanced.

[0010] Meanwhile, compared to the scheme where the distance between the conductive side and the reference side of each conductive layer varies from large to small along a preset direction, in this application, when the distance between the conductive side and the reference side of each conductive layer varies from small to large and then from large to small along a preset direction, the overall area of ​​the solder balls in the non-die-covered area projected onto the conductive layer (i.e., the sum of the projected areas of the solder balls in the non-die-covered area onto each conductive layer) can be increased, the impedance of the solder balls in the non-die-covered area can be reduced, thereby increasing the current on the solder balls in the non-die-covered area of ​​the ball grid array and improving the utilization rate of the solder balls in the non-die-covered area of ​​the ball grid array.

[0011] In one possible implementation, the plurality of conductive layers include a reference conductive layer, at least one lower conductive layer, and at least one upper conductive layer. The at least one lower conductive layer, the reference conductive layer, and the at least one upper conductive layer are stacked along a predetermined direction, and the distance between the conductive side and the reference side of the reference conductive layer is minimized. The upper conductive layer of the at least one upper conductive layer, which faces away from the reference conductive layer, is used for bonding with a printed circuit board, and the lower conductive layer of the at least one lower conductive layer, which faces away from the reference conductive layer, is used for bonding with a die.

[0012] In one possible implementation, there are multiple insulating layers, with the reference conductive layer adjacent to the thickest insulating layer among the multiple insulating layers.

[0013] The thickest insulating layer among the multiple insulating layers in this application can be used as the core layer of the packaging substrate. When the reference conductive layer is adjacent to the thickest insulating layer among the multiple insulating layers, the upper and lower conductive layers can be symmetrically distributed on the two surfaces of the reference conductive layer (i.e., the surface facing the die and the surface facing the printed circuit board). This structure can increase the overall projection area of ​​the solder balls in the non-die-covered area on the lower conductive layer (i.e., the sum of the projection areas of the solder balls in the non-die-covered area on each conductive layer). Since the lower conductive layer is closer to the solder balls in the non-die-covered area, the solder balls in the non-die-covered area are transferred from the lower conductive layer to the upper conductive layer with lower impedance and larger on-ball current, thereby further improving the utilization rate of the ball grid array in the non-die-covered area.

[0014] In one possible implementation, the difference between the number of lower conductive layers and the number of upper conductive layers is less than a preset difference. This structure allows adjustment of the overall area of ​​the solder balls projected onto the lower conductive layer in the non-die-covered area (i.e., the sum of the projected areas of the solder balls in the non-die-covered area across all conductive layers), controlling the degree of impedance reduction and the magnitude of current increase in the solder balls in the non-die-covered area. This ensures that the current on the solder balls in the die-covered area and the non-die-covered area of ​​the non-ball grid array is as balanced as possible.

[0015] In one possible implementation, the number of lower conductive layers is equal to the number of upper conductive layers, and each lower conductive layer and its corresponding upper conductive layer are symmetrical about a reference conductive layer.

[0016] In one possible implementation, the distance between the conductive side and the reference side of each lower conductive layer is equal to a first distance, and the distance between the conductive side and the reference side of each upper conductive layer is equal to a second distance; there are multiple lower conductive layers and multiple upper conductive layers, and the difference between the first distances of two adjacent lower conductive layers is equal to the difference between the second distances of two adjacent upper conductive layers.

[0017] In one possible implementation, the distance between the conductive side surface of each lower conductive layer and the reference side surface is equal to a first distance, and the distance between the conductive side surface of the upper conductive layer corresponding to each lower conductive layer and the reference side surface is equal to a second distance; the first distance is less than the second distance, and the distance difference between each lower conductive layer and the upper conductive layer corresponding to each lower conductive layer to the reference conductive layer is within a preset distance range.

[0018] When the distance between the conductive side and the reference side of each conductive layer changes in a preset direction from small to large and then from large to small, since the first distance is smaller than the second distance, the length of the lower conductive layer in the non-projection coverage area is greater than the length of the corresponding upper conductive layer in the non-projection coverage area. Therefore, if the number of lower and upper conductive layers is the same, the overall area of ​​the solder balls in the projection area of ​​the lower conductive layer in the non-die coverage area is larger than the overall area of ​​the solder balls in the projection area of ​​the upper conductive layer. This further reduces the solder ball impedance in the non-die coverage area and increases the solder ball current in the non-die coverage area, thereby improving the utilization rate of the solder balls in the non-die coverage area.

[0019] In one possible implementation, the distance between the conductive side of the lowest conductive layer and the reference side is equal to a third distance, and the distance between the conductive side of the highest conductive layer and the reference side is equal to a fourth distance, wherein the fourth distance is greater than or equal to the third distance.

[0020] When the distance between the conductive side and the reference side of each conductive layer changes in a preset direction from small to large and then from large to small, if the third distance is greater than the fourth distance, then the bottom conductive layer has the largest area among all conductive layers. This can effectively reduce the solder ball overcurrent capacity in the non-die-covered area and improve the solder ball utilization rate in the non-die-covered area.

[0021] In one possible implementation, each conductive layer has a first projected coverage area and a first non-projected coverage area, which are distributed along a direction close to the power supply device.

[0022] The first projected coverage area is the projection area of ​​the die onto the surface of the conductive layer, and the first non-projected coverage area is the area where the die's projection onto the surface of the conductive layer is not covered. The areas of different conductive layers in the first non-projected coverage area vary along a preset direction in an order from large to small and then from small to large. In this case, the distance between the conductive side and the reference side of each conductive layer varies along a preset direction in an order from small to large and then from large to small, thereby balancing the current on the solder balls of the ball grid array in the die-covered and non-die-covered areas while improving the solder ball utilization rate of the ball grid array in the non-die-covered area.

[0023] In one possible implementation, there are multiple insulating layers, and the number of conductive vias in each insulating layer varies along a predetermined direction in an order of increasing and then decreasing. In this case, the number of conductive vias in each insulating layer can match the area of ​​the adjacent conductive layer, providing sufficient current channels for the two adjacent conductive layers and ensuring the connectivity between them.

[0024] In one possible implementation, each insulating layer has a second projected coverage area and a second non-projected coverage area. The second projected coverage area is the area projected onto the surface of the insulating layer by the die, and the second non-projected coverage area is the area where the die's projection on the surface of the insulating layer is not covered.

[0025] When the conductive via distribution density of the insulating layer in the second projection coverage area is less than the first preset density, the solder ball impedance of the ball grid array in the die coverage area can be increased, and the current on the solder balls in the die coverage area can be reduced. When the conductive via distribution density of the insulating layer in the second non-projection coverage area is greater than the second preset density, the solder ball impedance of the ball grid array in the non-die coverage area can be reduced, and the current on the solder balls in the non-die coverage area can be increased. This not only improves the solder ball utilization rate in the non-die coverage area, but also balances the current on the solder balls in the die coverage area and the non-die coverage area.

[0026] Secondly, this application provides a packaging device, including: a bare die, a packaging substrate, a printed circuit board, and a power supply device disposed on the printed circuit board. The packaging substrate is the packaging substrate described in the first aspect of this application or any possible implementation thereof. The lowest conductive layer among the plurality of conductive layers included in the packaging substrate is connected to the printed circuit board, and a portion of the uppermost conductive layer among the plurality of conductive layers is used for connection with the bare die.

[0027] The beneficial effects of the technical solution of the second aspect provided in this application can be referred to the beneficial effects of the first aspect or any possible implementation of the first aspect, which will not be elaborated here. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0029] Figure 1 A side view schematic diagram of a packaged device in the related art is shown;

[0030] Figure 2 A schematic diagram of a PDN system is shown.

[0031] Figure 3 A schematic diagram of an equivalent model of a PDN system is shown.

[0032] Figure 4 A side view schematic diagram of a packaged device using a nine-layer packaged substrate as an example is shown;

[0033] Figure 5AThis invention illustrates a packaging schematic diagram using a nine-layer packaging substrate as an example, according to an embodiment of this application.

[0034] Figure 5B This paper shows a simplified side view of a packaging substrate and a power supply device according to an embodiment of this application.

[0035] Figure 5C This diagram illustrates the positional relationship between the conductive layer and the power supply device in an embodiment of this application.

[0036] Figure 6 This illustration shows another simplified side view of the packaging substrate and power supply device according to an embodiment of this application;

[0037] Figure 7 This illustration shows another simplified side view of the packaging substrate and power supply device according to an embodiment of this application;

[0038] Figure 8 A simplified schematic diagram of the distance difference between two adjacent conductive layers and the power supply device in an embodiment of this application is shown. Detailed Implementation

[0039] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0040] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0041] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0043] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] Figure 1 A side view of a packaged device in the related art is shown. (Example) Figure 1 As shown, in this packaging device 100, the lower surface of the packaging substrate 102 is connected to the printed circuit board 101 (PCB) via a ball grid array 100A, while the die 103 can be connected to the upper surface of the packaging substrate 102 via a bump array 100B.

[0045] from Figure 1 As can be seen, the power supply device 104 is disposed on the printed circuit board 101, and it can supply power to the bare die 103 through the printed circuit board 101 and the packaging substrate 102. However, the power consumption of different areas of the bare die 103 is different during operation, resulting in uneven current distribution on the solder balls of the ball grid array in different areas. Moreover, since the closer the power supply device 104 is to the solder balls, the greater the current flowing through the solder balls, and the farther the power supply device 104 is from the solder balls, the smaller the current flowing through the solder balls. Therefore, during the process of power supply device 104 supplying power to the bare die 103, as the distance between the solder balls included in the ball grid array 100A and the power supply device 104 increases, the current on the different solder balls included in the ball grid array 100A gradually decreases.

[0046] like Figure 1 As shown, when the power supply current of the power supply device 104 increases continuously, the current on the solder balls near the power supply device 104 becomes too large, which may cause the solder balls to melt, resulting in short circuits and other contact problems. Therefore, the current sharing problem on the balls of the package device 100 is extremely important for the design.

[0047] like Figure 1 As shown, when the die 103 is connected to the upper surface of the package substrate 102 via the bump array 100B, the die is not connected to the entire surface of the package substrate 102, but only to a portion of the surface. Therefore, from a spatial projection perspective, both the package substrate 102 and the ball grid array 100A can be divided into a die-covered area and a non-die-covered area. Since the distance between the solder balls in the die-covered area of ​​the ball grid array 100A and the power supply device 104 is greater, while the distance between the solder balls in the non-die-covered area is closer, the current on the solder balls in the die-covered area of ​​the ball grid array 100A is lower, while the current on the solder balls in the non-die-covered area is higher.

[0048] In addition, when there is a capacitor placement requirement at the bottom of the die coverage area of ​​the package substrate 102, the solder balls of the ball grid array 100A in the die coverage area can be removed to provide space for the capacitor. However, this results in higher current on the solder balls of the ball grid array 100A located in the non-die coverage area, thereby aggravating the problem of uneven current on the balls of the ball grid array 100A.

[0049] Currently, the impedance of the Power Distribution Network (PDN) system can be optimized by using PDN system network design methods, starting from controlling the system impedance. This method is called the Target Impedance design method. Its core idea is to optimize the PDN system impedance by utilizing the linear constraint relationship between current change, impedance, and voltage change.

[0050] Figure 2 A schematic diagram of a PDN system is shown. Figure 2 As shown, the PDN system 200 may include a power supply 201 and a capacitor 202 connected in series with the power supply 201. Since various factors of the PDN system 200 can be reduced to their influence on impedance, the PDN system 200 can be equivalent to... Figure 3 The equivalent model 300 of the PDN system is shown. Figure 3 As shown, the equivalent model 300 may include a constant voltage source 301 and an impedance 302 connected in series with the constant voltage source 301. The voltage difference ΔV across the impedance 302 satisfies ΔV = Z * ΔI. The impedance 302 can represent the total impedance of the package substrate, and ΔI represents the maximum transient current change of the constant voltage source 301. When the current ΔI is constant, if it is necessary to control the voltage difference ΔV across the impedance within the allowable range, it is necessary to control the impedance of the PDN system. The smaller the impedance, the better the performance of the PDN system.

[0051] To alleviate the problem of uneven current distribution on the spheres of a ball grid array, Figure 4 A side view schematic diagram of a packaged device using a nine-layer packaged substrate as an example is shown. Figure 4 As shown, in the packaged device 400, the package substrate 410 may include a first conductive layer 411A, a second conductive layer 412A, a third conductive layer 413A, a fourth conductive layer 414A, a fifth conductive layer 415A, a sixth conductive layer 416A, a seventh conductive layer 417A, an eighth conductive layer 418A, and a ninth conductive layer 419A distributed along a preset direction. The first conductive layer 411A is connected to the printed circuit board 420 via a ball grid array 400A, and the ninth conductive layer 419A is connected to the die 430 via a bump array 400B. In this case, the preset direction can be the direction from the printed circuit board 420 to the die 230.

[0052] It is understandable that, such as Figure 4 As shown, the insulating layer included in the packaging substrate can be divided into a core layer and a stacked layer. Figure 4 The layers included in the insulating layer are not shown; only the core layer 410B included in the insulating layer is shown, and the core layer 410B is located between the fifth conductive layer 414A and the sixth conductive layer 416A.

[0053] like Figure 4 As shown, the areas of the first conductive layer 411A, second conductive layer 412A, third conductive layer 413A, fourth conductive layer 414A, fifth conductive layer 415A, sixth conductive layer 416A, seventh conductive layer 417A, eighth conductive layer 418A, and ninth conductive layer 419A gradually increase along a predetermined direction. The power supply device 440 is located on the printed circuit board 420 and to the right of the package substrate 410. The current flowing through the solder balls in the ball grid array 400A is transmitted to the die via the corresponding conductive layer above them. Figure 4 As shown in the distribution of the conductive layer areas, along the direction closer to the power supply device 440, the impedance of the solder balls included in the ball grid array becomes higher and higher, and the corresponding current on the solder balls becomes lower and lower, thereby alleviating the problem of excessive current on the solder balls near the power supply device 440 in the ball grid array 400A to a certain extent.

[0054] The inventor discovered that by using Figure 4 In the designed package substrate configuration, the solder ball impedance near the power supply device 440 in the ball grid array 400A is higher than the solder ball impedance farther from the power supply device 440 in the ball grid array. For example, Figure 4The impedance of the solder balls in the die-covered area of ​​the ball grid array 400A is lower than that in the non-die-covered area. As a result, the current flowing through the ball grid array 400A is mainly integrated on the solder balls in the die-covered area. However, the current on the solder balls in the die-covered area is too large, which can easily cause the short circuit problems mentioned above. The current on the solder balls in the non-die-covered area is small, which results in low utilization of the solder balls in the non-die-covered area.

[0055] To address the aforementioned issues, this application provides a packaging device and a packaging substrate that can improve the uniformity of current on the balls of a ball grid array while solving the problem of low utilization of solder balls in non-die-covered areas of the ball grid array.

[0056] The packaging device provided in this application embodiment may include: a bare die, a packaging substrate, a printed circuit board, and a power supply device disposed on the printed circuit board. The packaging substrate can be used for planar design of signal transmission channels for various high-power chip packages. For example, the packaging substrate can be used for planar design of power supply channels for high-power servers.

[0057] In this embodiment of the application, the lowermost conductive layer of the packaging substrate is connected to the printed circuit board, and a portion of the uppermost conductive layer is used to connect to the die.

[0058] When the lowest conductive layer of the packaging substrate is connected to the printed circuit board through the ball grid array, the packaging substrate can improve the utilization rate of the solder balls in the non-die-covered area of ​​the ball grid array while balancing the current on the solder balls in the die-covered and non-die-covered areas.

[0059] The packaging substrate of this application embodiment may include a plurality of conductive layers stacked together and an insulating layer formed between two adjacent conductive layers. The insulating layer has a plurality of conductive vias, which are connected to two adjacent conductive layers.

[0060] The lowest conductive layer among the multiple conductive layers is used to connect with the printed circuit board on which the power supply device is located. A portion of the uppermost conductive layer among the multiple conductive layers is used to connect with the die. Each conductive layer has a conductive side facing the direction of the power supply device. The power supply device has a reference side facing the direction of the multiple conductive layers.

[0061] When the preset direction is the same as the direction of the printed circuit board pointing to the die, the distance between the conductive side and the reference side of each conductive layer changes along the preset direction in the order of small to large and then large to small.

[0062] Figure 5A This illustration shows a packaging schematic diagram using a nine-layer packaging substrate as an example, according to an embodiment of this application. Figure 5A As shown, the packaging substrate of this application embodiment includes nine conductive layers and an insulating layer located between two adjacent conductive layers. The nine conductive layers may include: a first conductive layer 511A, a second conductive layer 512A, a third conductive layer 513A, a fourth conductive layer 514A, a fifth conductive layer 515A, a sixth conductive layer 516A, a seventh conductive layer 517A, an eighth conductive layer 518A, and a ninth conductive layer 519A.

[0063] like Figure 5A As shown, the first insulating layer 511B is located between the first conductive layer 511A and the second conductive layer 512A; the second insulating layer 512B is located between the second conductive layer 512A and the third conductive layer 513A; the third insulating layer 513B is located between the third conductive layer 513A and the fourth conductive layer 514A; the fourth insulating layer 514B is located between the fourth conductive layer 514A and the fifth conductive layer 515A; the fifth insulating layer 515B is located between the fifth conductive layer 515A and the sixth conductive layer 516A; the sixth insulating layer 516B is located between the sixth conductive layer 516A and the seventh conductive layer 517A; the seventh insulating layer 517B is located between the seventh conductive layer 517A and the eighth conductive layer 518A; and the eighth insulating layer 518B is located between the eighth conductive layer 518A and the ninth conductive layer 519A.

[0064] like Figure 5A As shown, the first conductive layer 511A can be connected to the printed circuit board 520 through the ball grid array 500A, and the ninth conductive layer 519A can be connected through the bump array 500B. The printed circuit board 520 is provided with a power supply device 540.

[0065] For example, such as Figure 5A As shown, the first conductive layer 511A in this embodiment may include a plurality of first pads, each of which can be connected to the printed circuit board 520 via the corresponding solder balls included in the ball grid array 500A. The ninth conductive layer 519A may include a plurality of second pads, each of which can be connected to the die 530 via the corresponding bumps included in the bump array 500B.

[0066] In this embodiment, both the first and second pads can be distributed in a dot matrix pattern, and can be flexibly distributed, depending on the actual situation. Both the first and second pads in this embodiment can be power pads; however, in addition to power pads, they may also include ground pads and other signal pads.

[0067] The conductive layer in this application embodiment can be a thin metal layer, such as a copper layer, used for transmitting power signals or other signals. These copper layers can have openings in areas requiring avoidance, providing a passage for the object to be avoided. For example, in... Figure 5AIn the illustrated scheme, the packaging substrate includes not only nine conductive layers for transmitting power signals, but also a conductive layer for transmitting ground signals. Figure 5A (Not shown), while the conductive layer for transmitting power signals and the conductive layer for transmitting user ground signals can be alternately distributed along a preset direction. In this case, the conductive layer for transmitting power signals needs to avoid the ground signal transmission path. The following explanation uses the conductive layer for transmitting power signals as an example.

[0068] The conductive layer used for transmitting power signals in this application embodiment may include one or more metal leads (such as copper leads). Each metal lead may be connected to a conductive via in the same hole network in two adjacent insulating layers, or it may be connected to a conductive via in the same power hole network.

[0069] like Figure 5A As shown, when the power supply device 540 supplies power to the die 530, the current supplied by the power supply device can be transmitted through the printed circuit board to the solder balls included in the ball grid array 500A. Each solder ball can transmit current to the die 530 through a corresponding transmission path. This transmission path may include a first pad, multiple conductive vias, at least one wire, and a first pad. The solder ball may be electrically connected to a first pad, and the first pad may be electrically connected to a second pad through at least one wire. The at least one wire may include conductive vias in each insulating layer belonging to the same power via network as the solder ball, and metal leads in adjacent conductive layers connected through the conductive vias in the same power via network.

[0070] To facilitate the description of the distance variation between the conductive side surface of different conductive layers and the reference side surface of the power supply device, Figure 5B This paper shows a simplified side view of a packaging substrate and a power supply device according to an embodiment of this application. The packaging substrate of this embodiment is omitted. Figure 5A The diagram shows the various insulating layers, while retaining nine conductive layers.

[0071] like Figure 5BAs shown, the distance between the conductive side of the first conductive layer and the reference side of the power supply device can be represented as d1, the distance between the conductive side of the second conductive layer and the reference side of the power supply device can be represented as d2, the distance between the conductive side of the third conductive layer and the reference side of the power supply device can be represented as d3, the distance between the conductive side of the fourth conductive layer and the reference side of the power supply device can be represented as d4, the distance between the conductive side of the fifth conductive layer and the reference side of the power supply device can be represented as d5, the distance between the conductive side of the sixth conductive layer and the reference side of the power supply device can be represented as d6, the distance between the conductive side of the seventh conductive layer and the reference side of the power supply device can be represented as d7, the distance between the conductive side of the eighth conductive layer and the reference side of the power supply device can be represented as d8, and the distance between the conductive side of the ninth conductive layer and the reference side of the power supply device can be represented as d9.

[0072] from Figure 5B It can be seen that d1 > d2 > d3 > d4 > d5 < d6 < d7 < d8 < d9. In this case, along the direction away from the power supply device 540, the number of conductive layers corresponding to the solder balls included in the ball grid array 500A increases. Therefore, compared with the scheme of laying conductive layers on the entire surface, the overall area of ​​the solder balls in the non-die-covered area of ​​the conductive layer (i.e., the sum of the projected areas of the solder balls in the non-die-covered area of ​​each conductive layer) is relatively small. Therefore, the overall impedance of the solder balls in the non-die-covered area of ​​the ball grid array in this embodiment of the application increases, so that the current on the solder balls in the die-covered area and the non-die-covered area of ​​the ball grid array 500A tends to be balanced.

[0073] Moreover, relative to Figure 4 The scheme shown is as follows: Figure 5B As shown, the overall area of ​​the solder balls in the non-die-covered region projected onto the conductive layer (i.e., the sum of the projected areas of the solder balls in the non-die-covered region onto each conductive layer) increases. Therefore, by increasing the overall area of ​​the solder balls in the non-die-covered region projected onto the conductive layer, the impedance of the solder balls in the non-die-covered region is reduced, thereby increasing the current on the solder balls in the non-die-covered region of the ball grid array 500A and improving the utilization rate of the solder balls in the non-die-covered region of the ball grid array 500A.

[0074] As can be seen, the embodiments of this application can reduce the impedance of the solder balls in the non-die-covered area by gradually moving the conductive layer inward and then outward along a preset direction, thereby increasing the current on the solder balls in the non-die-covered area of ​​the ball grid array 500A.

[0075] In one possible implementation, when the distance between the conductive side surface of each conductive layer and the reference side surface varies along a preset direction in an order of increasing and then decreasing, each conductive layer has a first projected coverage area and a first non-projected coverage area, which are distributed along a direction close to the power supply device. When the distance between the conductive side surface of each conductive layer and the reference side surface varies along a preset direction in an order of increasing and then decreasing, the area of ​​the different conductive layers in the first non-projected coverage area also varies along a preset direction in an order of decreasing and then increasing.

[0076] Figure 5C A schematic diagram illustrating the positional relationship between the conductive layer and the power supply device in an embodiment of this application is shown. Figure 5C As shown, the conductive layer in this embodiment of the application has a first projection coverage area 510A and a first non-projection coverage area 510B. With the conductive layer as the projection plane, the projection of the die on the conductive layer coincides with the first projection coverage area 510A, while the projection of the power supply device 540 on the conductive layer is located in the area outside the conductive layer. The first projection coverage area 510A and the first non-projection coverage area 510B are distributed along the direction close to the power supply device 540.

[0077] from Figure 5C It can be seen that when the distance between the conductive side and the reference side of each conductive layer changes along a preset direction in an order of increasing and then decreasing, the length of the first non-projection coverage area 510B of different conductive layers in the horizontal direction X gradually decreases and then gradually increases along the preset direction. Since the width of the first non-projection coverage area 510B of different conductive layers does not change, when the distance between the conductive side and the reference side of each conductive layer changes along a preset direction in an order of increasing and then decreasing, the area of ​​the first non-projection coverage area changes along a preset direction in an order of decreasing and then increasing. The effect of this can be referred to the relevant description above.

[0078] Considering that the insulating layer is located between two adjacent conductive layers, and that the insulating layer has multiple conductive vias that can connect the two adjacent conductive layers, when there are multiple insulating layers, the number of conductive vias in each insulating layer varies along a preset direction in an order from smallest to largest and then from largest to smallest.

[0079] by Figure 5AAs shown, the first insulating layer 511B has 11 conductive vias, the second insulating layer 512B has 9 conductive vias, the third insulating layer 513B has 8 conductive vias, the fourth insulating layer 514B has 7 conductive vias, the fifth insulating layer 515B has 7 conductive vias, the sixth insulating layer 516B has 8 conductive vias, the seventh insulating layer 517B has 9 conductive vias, and the eighth insulating layer 518B has 10 conductive vias.

[0080] It can be seen that the distribution pattern of the number of conductive vias in the first insulating layer 511B to the eighth insulating layer 518B matches the distance variation pattern between the conductive side surface and the reference side surface in the first conductive layer 511A to the ninth conductive layer 519A. Therefore, the number of conductive vias in each insulating layer can match the area of ​​the adjacent conductive layer, providing sufficient current channels for the two adjacent conductive layers and ensuring the connectivity of the two adjacent conductive layers.

[0081] In one possible implementation, the plurality of conductive layers in this embodiment include a reference conductive layer, at least one lower conductive layer, and at least one upper conductive layer. The at least one lower conductive layer, the reference conductive layer, and the at least one upper conductive layer are stacked along a predetermined direction, and the distance between the conductive side surface of the reference conductive layer and the reference side surface is minimized. Figure 5A and Figure 5B For example, the fifth conductive layer 515A has the smallest distance between its conductive side and the reference side, therefore, the fifth conductive layer 515A can be a reference conductive layer.

[0082] like Figure 5A and Figure 5B As shown, the first conductive layer 511A, the second conductive layer 512A, the third conductive layer 513A and the fourth conductive layer 514A are all located between the printed circuit board 520 and the fifth conductive layer 515A. Therefore, the first conductive layer 511A, the second conductive layer 512A, the third conductive layer 513A and the fourth conductive layer 514A can be used as the lower conductive layer.

[0083] like Figure 5A and Figure 5B As shown, the sixth conductive layer 516A, the seventh conductive layer 517A, the eighth conductive layer 518A, and the ninth conductive layer 519A are all located between the fifth conductive layer 515A and the bare die 530. Therefore, the sixth conductive layer 516A, the seventh conductive layer 517A, the eighth conductive layer 518A, and the ninth conductive layer 519A can be used as the upper conductive layer.

[0084] In some embodiments, the number of insulating layers in this application is multiple, and the reference conductive layer is adjacent to the insulating layer with the largest thickness among the multiple insulating layers. When one of the multiple insulating layers has the largest thickness, that insulating layer can be used as the core layer of the packaging substrate, while the other insulating layers can be used as the stacked layers of the packaging substrate.

[0085] by Figure 5A For example, from Figure 5A It can be seen that among the first insulating layer 511B, the second insulating layer 512B, the third insulating layer 513B, the fourth insulating layer 514B, the fifth insulating layer 515B, the sixth insulating layer 516B, the seventh insulating layer 517B, and the eighth insulating layer 518B, the fifth insulating layer 515B has the largest thickness. The fifth insulating layer 515B is adjacent to the fifth conductive layer 515A, and the fifth conductive layer 515A can be used as a reference conductive layer.

[0086] When a reference conductive layer is adjacent to the thickest insulating layer among multiple insulating layers, the upper and lower conductive layers can typically be symmetrically distributed on the two surfaces of the reference conductive layer (i.e., the surface facing the die and the surface facing the printed circuit board). Here, symmetrical distribution can mean that the difference between the number of lower conductive layers and the number of upper conductive layers is less than a preset difference value.

[0087] For example, the number of lower conductive layers is equal to the number of upper conductive layers, and each lower conductive layer and its corresponding upper conductive layer are symmetrical about the reference conductive layer. This structure increases the overall projection area of ​​the solder balls in the non-die-covered area onto the lower conductive layer (i.e., the sum of the projection areas of the solder balls in the non-die-covered area across all conductive layers). Because the lower conductive layer is closer to the solder balls in the non-die-covered area, the solder balls in this area can transfer from the lower conductive layer to the upper conductive layer with lower impedance and greater on-ball current, thereby improving the current-carrying capacity of the solder balls in the non-die-covered area and further enhancing the utilization rate of the ball grid array in the non-die-covered area.

[0088] In some embodiments, the difference between the number of lower conductive layers and the number of upper conductive layers is less than a preset difference. For example, the preset difference can range from 0 to k, where k represents an integer greater than 0, and the value of k is selected according to the actual situation. This structure allows adjustment of the overall area of ​​the solder balls projected onto the lower conductive layer in the non-die-covered area (i.e., the sum of the projected areas of the solder balls in the non-die-covered area across all conductive layers), controlling the degree of impedance reduction and the increase in current on the solder balls in the non-die-covered area, thereby ensuring that the current on the solder balls in the die-covered area and the non-die-covered area of ​​the non-ball grid array is as balanced as possible.

[0089] Figure 6 This diagram illustrates another simplified side view of the packaging substrate and power supply device according to an embodiment of this application. Figure 6As shown, the packaging substrate of this application embodiment and Figure 5B The difference lies in the fact that the fourth conductive layer has the smallest distance d4 between its conductive side and the reference side; therefore, the fourth conductive layer can be the reference conductive layer. In this case, there are two lower conductive layers and six upper conductive layers. Relative to... Figure 5A The structure shown has a relatively small overall area of ​​the solder balls projected onto the lower conductive layer in the non-die-covered area (i.e., the sum of the projected areas of the solder balls in the non-die-covered area across all conductive layers). Therefore, when using... Figure 6 In the structure shown, although the impedance of the solder ball in the non-dead die covered area decreases, it is still relatively... Figure 5A The reduction in current of the structure shown is relatively small, therefore, the current on the solder balls in the non-die-covered area of ​​the ball grid array can be increased by a small amount.

[0090] Figure 7 This illustration shows another simplified side view of the packaging substrate and power supply device according to an embodiment of this application. (See attached diagram.) Figure 7 As shown, the packaging substrate of this application embodiment and Figure 5B The difference lies in the fact that the sixth conductive layer has the smallest distance d6 between its conductive side and the reference side; therefore, the sixth conductive layer can be the reference conductive layer. In this case, there are 5 lower conductive layers and 2 upper conductive layers. Relative to... Figure 5A The structure shown has a relatively high overall projection area of ​​the solder balls in the non-die-covered area onto the lower conductive layer (i.e., the sum of the projection areas of the solder balls in the non-die-covered area onto each conductive layer). Therefore, when using... Figure 7 In the structure shown, although the impedance of the solder ball in the non-dead die covered area decreases, it is still relatively... Figure 5A The structure shown has a higher reduction rate, therefore, the current on the solder balls in the non-die-covered area of ​​the ball grid array can be increased by a higher magnitude.

[0091] As can be seen, by adjusting the difference between the number of the lower conductive layer and the number of the upper conductive layer, the degree of impedance reduction of the solder balls in the non-die-covered area and the magnitude of the increase in the current on the balls can be controlled, thereby ensuring that the current on the solder balls in the non-ball grid array in the die-covered area and the non-die-covered area is as balanced as possible.

[0092] In some embodiments, the distance between the conductive side surface and the reference side surface of each lower conductive layer is equal to a first distance, and the distance between the conductive side surface and the reference side surface of each upper conductive layer is equal to a second distance; there are multiple lower conductive layers and multiple upper conductive layers, and the difference between the first distances of two adjacent lower conductive layers is equal to the difference between the second distances of two adjacent upper conductive layers.

[0093] Figure 8A simplified schematic diagram illustrating the distance difference between two adjacent conductive layers and the power supply device in an embodiment of this application is shown. Figure 8 As shown, d3-d2=Δ32, d7-d6=Δ76. Here, Δ32=Δ76.

[0094] When the difference of the first distance between two adjacent lower conductive layers is equal to the difference of the second distance between two adjacent upper conductive layers, the impedance of each solder ball included in the ball grid array can be easily calculated, making the design of the packaging substrate simpler and faster.

[0095] In some embodiments, the distance between the conductive side surface of each lower conductive layer and the reference side surface is equal to a first distance, and the distance between the conductive side surface of the upper conductive layer corresponding to each lower conductive layer and the reference side surface is equal to a second distance; the first distance is less than the second distance, and the distance difference between each lower conductive layer and the upper conductive layer corresponding to each lower conductive layer to the reference conductive layer is within a preset distance range.

[0096] by Figure 5A For example, the fifth conductive layer 515A can be used as a reference conductive layer, the first conductive layer 511A, the second conductive layer 512A, the third conductive layer 513A, and the fourth conductive layer 514A can be used as lower conductive layers, and the sixth conductive layer 516A, the seventh conductive layer 517A, the eighth conductive layer 518A, and the ninth conductive layer 519A can be used as upper conductive layers. In this case, the fourth conductive layer 514A corresponds to the sixth conductive layer 516A, the third conductive layer 513A corresponds to the seventh conductive layer 517A, the second conductive layer 512A corresponds to the eighth conductive layer 518A, and the first conductive layer 511A and the ninth conductive layer 519A are used.

[0097] like Figure 5B As shown, d1 can be the first distance corresponding to the first conductive layer 511A, d2 can be the first distance corresponding to the second conductive layer 512A, d3 can be the first distance corresponding to the third conductive layer 513A, d4 can be the second distance corresponding to the fourth conductive layer 514A, d6 can be the second distance corresponding to the sixth conductive layer 516A, d7 can be the first distance corresponding to the seventh conductive layer 517A, d8 can be the second distance corresponding to the eighth conductive layer 518A, and d9 can be the second distance corresponding to the ninth conductive layer 519A.

[0098] like Figure 5BAs shown, based on the formula d1>d2>d3>d4>d5<d6<d7<d8<d9, the order is d1>d9, d2>d8, d3>d7, d4>d6. In this case, the length of the lower conductive layer in the non-projection coverage area is greater than the length of the corresponding upper conductive layer in the non-projection coverage area. Therefore, if the number of lower and upper conductive layers is the same, the overall area of ​​the solder balls in the projection area of ​​the lower conductive layer in the non-die coverage area is larger than the overall area of ​​the solder balls in the projection area of ​​the upper conductive layer. This further reduces the solder ball impedance in the non-die coverage area and increases the solder ball current in the non-die coverage area, thereby improving the utilization rate of the solder balls in the non-die coverage area.

[0099] For example, the distance between the conductive side of the lowest conductive layer and the reference side is equal to a third distance, and the distance between the conductive side of the highest conductive layer and the reference side is equal to a fourth distance, wherein the fourth distance is greater than or equal to the third distance.

[0100] When the distance between the conductive side and the reference side of each conductive layer changes in a preset direction from small to large and then from large to small, if the third distance is greater than the fourth distance, then the bottom conductive layer has the largest area among all conductive layers, which can effectively reduce the solder ball impedance in the non-die-covered area and increase the solder ball current in the non-die-covered area.

[0101] by Figure 5B For example, based on the condition d1>d2>d3>d4>d5<d6<d7<d8<d9, d1>d9, d2>d8, d3>d7, d4>d6. In this case, the distance between the conductive side and the reference side of the first conductive layer is the largest, and the corresponding area of ​​the first conductive layer is the largest among all conductive layers. This can effectively reduce the solder ball overcurrent capacity in the non-die-covered area and improve the solder ball utilization rate in the non-die-covered area.

[0102] In one possible implementation, each insulating layer has a second projected coverage area and a second non-projected coverage area. The second projected coverage area is the area projected onto the surface of the insulating layer by the die, and the second non-projected coverage area is the area where the die's projection onto the surface of the insulating layer is not covered.

[0103] With the insulating layer as the projection plane, the projection of the die on the insulating layer coincides with the second projection coverage area, while the projection of the power supply device on the insulating layer is located in the area outside the insulating layer, and the second projection coverage area and the second non-projection coverage area are distributed along the direction close to the power supply device.

[0104] When the conductive via distribution density of the insulating layer in the second projection coverage area is less than the first preset density, the solder ball impedance of the ball grid array in the die coverage area can be increased, and the current on the solder balls in the die coverage area can be reduced. When the conductive via distribution density of the insulating layer in the second non-projection coverage area is greater than the second preset density, the solder ball impedance of the ball grid array in the non-die coverage area can be reduced, and the solder ball current carrying capacity of the ball grid array in the non-die coverage area can be increased. This not only improves the solder ball utilization rate in the non-die coverage area, but also balances the current on the solder balls in the die coverage area and the non-die coverage area.

[0105] In practical applications, there is no magnitude relationship between the conductive via distribution density of the insulating layer in the second projection coverage area and the conductive via distribution density of the insulating layer in the second non-projection coverage area in the embodiments of this application. It is only based on related technologies that the conductive via distribution density of the insulating layer in the second projection coverage area is reduced, while the conductive via distribution density of the insulating layer in the second non-projection coverage area is increased.

[0106] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0107] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A packaging substrate, characterized in that, The packaging substrate includes: a plurality of conductive layers stacked together and an insulating layer formed between two adjacent conductive layers, the insulating layer having a plurality of conductive vias, the plurality of conductive vias being connected to two adjacent conductive layers; The lowest conductive layer among the plurality of conductive layers is used to connect with a printed circuit board equipped with a power supply device, a portion of the uppermost conductive layer among the plurality of conductive layers is used to connect with a bare die, each of the conductive layers has a conductive side facing the direction of the power supply device, and the power supply device has a reference side facing the direction of the plurality of conductive layers. The distance between the conductive side surface of each conductive layer and the reference side surface varies along a preset direction in an order of increasing and then decreasing, and the preset direction is the same as the direction from which the printed circuit board points to the die.

2. The packaging substrate according to claim 1, characterized in that, The plurality of conductive layers include a reference conductive layer, at least one lower conductive layer and at least one upper conductive layer, wherein the at least one lower conductive layer, the reference conductive layer and the at least one upper conductive layer are stacked along the preset direction, and the distance between the conductive side surface of the reference conductive layer and the reference side surface is minimized. The at least one upper conductive layer that is opposite to the reference conductive layer is used to connect with the printed circuit board, and the at least one lower conductive layer that is opposite to the reference conductive layer is used to connect with the die.

3. The packaging substrate according to claim 2, characterized in that, The number of insulating layers is multiple, and the reference conductive layer is adjacent to the insulating layer with the largest thickness among the multiple insulating layers.

4. The packaging substrate according to claim 2, characterized in that, The difference between the number of the lower conductive layer and the number of the upper conductive layer is less than a preset difference value.

5. The packaging substrate according to claim 2, characterized in that, The number of lower conductive layers is equal to the number of upper conductive layers, and each lower conductive layer and the corresponding upper conductive layer are symmetrical about the reference conductive layer.

6. The packaging substrate according to claim 2, characterized in that, The distance between the conductive side surface of each lower conductive layer and the reference side surface is equal to a first distance, and the distance between the conductive side surface of each upper conductive layer and the reference side surface is equal to a second distance. There are multiple lower conductive layers and multiple upper conductive layers. The difference in the first distance between two adjacent lower conductive layers is equal to the difference in the second distance between two adjacent upper conductive layers.

7. The packaging substrate according to claim 2, characterized in that, The distance between the conductive side surface of each lower conductive layer and the reference side surface is equal to a first distance, and the distance between the conductive side surface of the upper conductive layer corresponding to each lower conductive layer and the reference side surface is equal to a second distance. The first distance is less than the second distance, and the distance difference between each lower conductive layer and the corresponding upper conductive layer to the reference conductive layer is within a preset distance range.

8. The packaging substrate according to claim 1, characterized in that, The distance between the conductive side surface of the lowest conductive layer and the reference side surface of the plurality of conductive layers is equal to a third distance, and the distance between the conductive side surface of the uppermost conductive layer and the reference side surface of the plurality of conductive layers is equal to a fourth distance, wherein the fourth distance is greater than or equal to the third distance.

9. The packaging substrate according to claim 1, characterized in that, Each of the conductive layers has a first projected coverage area and a first non-projected coverage area, the first projected coverage area and the first non-projected coverage area being distributed along a direction close to the power supply device; The first projection coverage area is the projection area of ​​the die on the surface of the conductive layer, and the first non-projection coverage area is the area of ​​the die not covered by the projection on the surface of the conductive layer. The area of ​​different conductive layers in the first non-projection coverage area changes from large to small and then from small to large along the preset direction.

10. The packaging substrate according to any one of claims 1 to 9, characterized in that, The number of insulating layers is multiple, and the number of conductive vias in the multiple insulating layers varies along the preset direction in an order from small to large and then from large to small.

11. The packaging substrate according to any one of claims 1 to 9, characterized in that, Each of the insulating layers has a second projected coverage area and a second non-projected coverage area, the second projected coverage area and the second non-projected coverage area being distributed along a direction close to the power supply device; The second projection coverage area is the projection area of ​​the bare die on the surface of the insulating layer, and the second non-projection coverage area is the area where the projection of the bare die on the surface of the insulating layer is not covered. The distribution density of conductive vias in the second projection coverage area of ​​the insulating layer is less than the first preset density, and the distribution density of conductive vias in the second non-projection coverage area of ​​the insulating layer is greater than the second preset density.

12. A packaged device, characterized in that, include: A bare die, a packaging substrate, a printed circuit board, and a power supply device disposed on the printed circuit board, wherein the packaging substrate is the packaging substrate according to any one of claims 1 to 11; The lowest conductive layer among the multiple conductive layers of the packaging substrate is connected to the printed circuit board, and a portion of the uppermost conductive layer among the multiple conductive layers is used to connect to the die.

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