Wafer grinding method
By forming an edge support in the annular peripheral region of the wafer, the problem of wafer edges being easily broken during the grinding process is solved, resulting in a more stable grinding effect and reduced manufacturing costs.
Patent Information
- Application Number
- CN202410839930.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-26
- Publication Date
- 2025-12-26
AI Technical Summary
During the wafer grinding process, the wafer edges are prone to cracks and breakage, especially when the wafer becomes thinner. Existing technologies struggle to provide effective edge support and uniform grinding force, leading to edge weakening and breakage.
An edge support, such as a patterned photoresist layer or a patterned thermosetting material layer, is formed in the annular peripheral region of the wafer to cover the annular peripheral region but expose the solder ball area. Combined with the back-side polishing tape, it provides stable edge support and reduces polishing stress.
The use of edge supports significantly reduces the risk of damage to wafer edges, lowers manufacturing costs, and improves the uniformity and stability of the grinding process.
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Figure CN121199852A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates generally to the fabrication of multiple semiconductor devices, and more specifically to various wafer grinding methods. BACKGROUND
[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic devices to be smaller in size, faster in speed, and higher in performance, and pack more and more functionality into a single device. One of the solutions is to reduce the size of the semiconductor devices via a wafer grinding process to provide semiconductor dies with a thinner profile. However, as the wafer is ground and becomes thinner, the wafer edge can be reduced to a sharp edge that can be relatively weak. From a microscopic perspective, it can be observed that there is little structural support at this portion of the wafer. Thus, an uneven force applied during grinding or stress relief can easily create a crack. This crack can continue to propagate during further handling and cause the wafer edge to chip or even the wafer to break.
[0003] Therefore, there is a need to further improve wafer grinding methods. SUMMARY
[0004] It is an object of the present application to provide an improved wafer grinding method with wafer strength enhancement.
[0005] According to an aspect of the present application, a wafer grinding method is provided. The wafer grinding method includes providing a wafer substrate including a front side and a back side, wherein the front side includes a solder ball region and an annular peripheral region surrounding the solder ball region; forming a patterned photoresist layer on the front side of the wafer substrate, wherein the patterned photoresist layer at least partially covers the annular peripheral region but exposes the solder ball region; forming a plurality of solder balls on the solder ball region; attaching a backside grinding tape on the front side to cover both the solder ball region and the annular peripheral region; and performing a backside grinding process on the back side of the wafer substrate.
[0006] According to another aspect of the present application, a wafer grinding method is provided. The wafer grinding method includes providing a wafer substrate including a front side and a back side, wherein the front side includes a solder ball region and an annular peripheral region surrounding the solder ball region, wherein the solder ball region is formed with a plurality of solder balls; forming a patterned thermoset material layer on the front side of the wafer substrate, wherein the patterned thermoset material layer at least partially covers the annular peripheral region but exposes the solder ball region; attaching a backside grinding tape on the front side to cover both the solder ball region and the annular peripheral region; and performing a backside grinding process on the back side of the wafer substrate.
[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application, as claimed. Furthermore, the accompanying drawings are incorporated in and constitute a part of the specification. The drawings illustrate embodiments of the application and, together with the description, serve to explain the principles of the application. BRIEF DESCRIPTION OF DRAWINGS
[0008] The drawings referred to in this description are incorporated in and constitute a part of this specification. The illustrations in the various drawings are for the purpose of illustrating embodiments of the application and do not limit the present application, unless otherwise explicitly stated in the specification. The reader should not assume that the described embodiments are the only ones in accordance with the application.
[0009] Figure 1A A plan view of a wafer substrate is shown.
[0010] Figure 1B A portion of the wafer substrate shown in Figure 1A is shown.
[0011] Figure 1C A side view of a portion of the wafer substrate shown in Figure 1A is shown during a backside grinding process.
[0012] Figure 2A A plan view of a wafer substrate formed with edge supports according to one embodiment of the application is shown.
[0013] Figure 2B A portion of the wafer substrate shown in Figure 2A is shown.
[0014] Figure 2C A side view of a portion of the wafer substrate shown in Figure 2A is shown during a backside grinding process.
[0015] Figure 2D and 2E A portion of the wafer substrate shown in Figure 2A is shown according to two other embodiments of the application.
[0016] Figures 3A to 3G A portion of the wafer substrate in a plurality of wafer grinding steps according to embodiments of the application is shown.
[0017] Figures 4A to 4C A portion of the wafer substrate in a plurality of wafer grinding steps according to another embodiment of the application is shown.
[0018] Throughout the drawings, the same reference designators will be used to denote same or similar portions in the several views. DETAILED DESCRIPTION
[0019] The following detailed description of the exemplary embodiments of the present application refers to the accompanying drawings that form a part of this description. The drawings show, among other things, specific exemplary embodiments of the present application. These embodiments, presented in sufficient detail to enable one skilled in the art to make and use the application, are illustrative in nature and are not intended to be limiting of the application. Other embodiments of the present application can be readily devised by those skilled in the art and can be constructed using the same or similar design techniques without departing from the spirit or scope of the present application. Accordingly, the reader should not place undue reliance on the detailed description set forth herein. The scope of the present application is defined only by the appended claims, rather than the detailed description and the exemplary embodiments describing the application.
[0020] In this application, the use of the singular includes the plural, unless specifically stated otherwise. In this application, the use of "or" means "and / or" unless stated otherwise. Furthermore, the use of the term "including", as well as other forms such as "include" and "includes", is not limiting. Also, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components that comprise more than one subunit unless specifically stated otherwise. Further, the section headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description.
[0021] As used herein, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "on", "under", "over", "left", "right", "vertical", "horizontal", "side", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that, when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements can be present.
[0022] Figures 1A to 1C The wafer substrate 100 prepared for a conventional wafer grinding process is shown from different angles. Figure 1A A plan view of the wafer substrate 100 is shown, Figure 1B A portion 100a of the wafer substrate 100 is shown, Figure 1C A side view of a portion of the wafer substrate 100 during a back grinding process is shown.
[0023] Reference is made to Figures 1A to 1CThe wafer substrate 100 can generally take the form of a circular plate having various semiconductor units 130 (only 9 are shown for illustration purposes). Specifically, the front side 110 of the wafer substrate 100 includes a solder ball region 111 and an annular peripheral region 112 surrounding the solder ball region 111. In the solder ball region 111, a plurality of semiconductor units 130 can be formed with a plurality of solder balls 140 for electrical connection with other electrical devices.
[0024] During the backgrinding process, the wafer substrate 100 is attached with a backgrinding tape 150. The backgrinding tape 150 provides support and protection for the active front side 110 of the wafer substrate 100. Then, the wafer substrate 100 can be placed on a chuck table 160, and the back side 120 of the wafer substrate 100 opposite to the front side 110 can be exposed for backgrinding.
[0025] As shown in Figure 1C Due to the nature of the plurality of solder balls 140 formed on the front side 110 of the wafer substrate 100, the backgrinding tape 150 on the annular peripheral region 112 can form a stepped profile 170, and thus, the annular peripheral region 112 can not have sufficient support underneath. This stepped profile 170 is important for high bumped (>120um) wafers. In addition, the chuck table 160 usually has a central porous region 161 and a ceramic region 162. When grinding high bumped wafers, manufacturers usually use a chuck table with a smaller porous region (286mm) instead of a regular chuck table (with a porous region of 297mm), this chuck table with a smaller porous region can also cause vacuum leakage underneath the annular peripheral region 112. Therefore, in a conventional wafer grinding process, the edge of the wafer substrate 100 is not fully supported, thus, the annular peripheral region 112 of the wafer substrate 100 is subjected to greater grinding stress, potentially uneven grinding and greater total thickness variation (TTV), which can cause edge weakening, edge chipping and die cracking.
[0026] To solve the above problems, the present application provides an improved wafer grinding method with better edge support at the annular peripheral region of the wafer substrate.
[0027] Figures 2A to 2C A wafer substrate 200 prepared for a wafer grinding process according to an embodiment of the present application is shown from different angles. Figure 2A A plan view of the wafer substrate 200 is shown, Figure 2B A portion 200a of the wafer substrate 200 is shown, Figure 2CA side view of a portion of wafer substrate 200 during a backside grinding process is shown.
[0028] Unlike conventional backside grinding processes, in embodiments, an edge support 270 is formed on the annular peripheral region 212 of the frontside 210 of wafer substrate 200. With this edge support 270, the annular peripheral region 212 has sufficient structural support underneath. Also, a chuck table with a normal porous region 261 (e.g., 297 mm) can be used, similar to the solder ball region 211 of the frontside 210 of wafer substrate 200, the annular peripheral region 212 is vacuumed. Thus, grinding stress and damage to the wafer edge can be greatly reduced, especially for thin wafers with high bumps. Also, manufacturers do not need to purchase chuck tables with smaller porous regions. Thus, manufacturing cost can be reduced.
[0029] The edge support 270 can take any desired form on the annular peripheral region 212. In some embodiments, as shown in FIG. 1A, the edge support 270 can cover all of the annular peripheral region 212. In some embodiments, as shown in FIG. 1B, the edge support 270 can partially cover the annular peripheral region 212. In some embodiments, as shown in FIG. 1C, the edge support 270 can expose the saw streets 231 between the semiconductor units 230 of wafer substrate 200 to minimize saw blade clogging during sawing, especially when thin blades or very fine diamond blades are used. In some embodiments, as shown in FIG. 1D, the edge support 270 can be formed at a distance from either or both of the boundaries of the annular peripheral region 212. Specifically, there can be a distance Dl between the outer boundary of the annular peripheral region 212 and the outer boundary of the edge support 270, preferably in the range of 0.5 mm to 1.5 mm, more preferably 1 mm. Thus, the backside grinding tape 250 can be adhered to the wafer substrate 200 near the wafer edge. Similarly, there can be a distance D2 between the inner boundary of the annular peripheral region 212 and the inner boundary of the edge support 270, preferably in the range of 0.5 mm to 1.5 mm, more preferably 1 mm. Thus, the backside grinding tape 250 can be adhered to the wafer substrate 200 near the wafer edge. Also, the edge support 270 with this configuration leaves enough space for the material of the backside grinding tape 250 to conform and fill the area between the edge support 270 and the outermost solder balls 240. Figure 2B Figure 2D 2E Figure 2D Figure 2E
[0030] The height of the edge support 270 can vary as desired. Preferably, the height of the edge support 270 is in the range of 1 / 2 to 3 / 4 of the average height of the plurality of solder balls 240. This height can minimize the difference in height between the plurality of solder balls 240 and the front side 210 of the wafer substrate 200, and still allow sufficient coverage of the backside grind tape 250. Thus, the backside grind tape 250 can easily and stably cover the plurality of solder balls 240, as well as the area between the plurality of outermost solder balls 240 and the edge support 270.
[0031] According to embodiments of the present application, the edge support 270 can be a patterned photoresist layer or a patterned thermoset material layer. These two materials allow better control of the height of the edge support. Details of wafer grinding with such edge supports are shown below.
[0032] Figures 3A to 3G A portion of a wafer substrate 300 formed with a patterned photoresist layer in a wafer grinding step according to embodiments of the present application is shown.
[0033] Referring to Figure 3A , a wafer substrate 300 is provided. Similar to the wafer substrates 100 and 200 shown previously in Figures 1A to 1C and 2A-2C, the wafer substrate 300 includes a front side 310 and a back side 320 opposite each other. The front side 310 includes a solder ball region 311 and an annular peripheral region 312 surrounding the solder ball region 311. Preferably, the solder ball region 311 has not yet been formed with a plurality of solder balls, and an under ball metal (UBM) layer 313 is exposed.
[0034] In some embodiments, the wafer substrate 300 can include a base substrate material, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material used for structural support. Semiconductor elements (not shown) formed thereon can be separated into individual semiconductor dies by passive die-to-die saw streets after the grinding process.
[0035] Referring to Figures 3B to 3D , a patterned photoresist layer 370 is then formed. The patterned photoresist layer 370 at least partially covers the annular peripheral region 312, but exposes the solder ball region 311. In particular, as shown in Figure 3B , a photoresist layer 371 made of a positive photoresist material is formed to cover the front side 310 of the wafer substrate 300. Then, as shown in Figure 3CAs shown, mask 372 can be positioned above the photoresist layer to at least partially cover the annular peripheral region 312, but expose the solder ball region 311. An exposure process using, for example, an ultraviolet laser source can then be performed on the photoresist layer through mask 372. Furthermore, as... Figure 3D As shown, a development process is performed on the exposed photoresist layer, and a portion of the photoresist layer 371 exposed to the ultraviolet laser source through the mask is removed, while a portion 370 of the photoresist layer 371 covered by or aligned with the mask 372 is retained for use in several subsequent steps.
[0036] It is understood that in some other embodiments, in order to form the patterned photoresist layer 370, a negative photoresist material and a mask having a complementary coverage area to the mask 372 mentioned above may also be used.
[0037] It is also understood that the patterned photoresist layer 370 can take different forms. For example, the patterned photoresist layer 370 can completely cover the annular peripheral region 312, exposing or covering multiple saw marks of the wafer substrate 300 in the annular peripheral region 312. In some other embodiments, the distance between the outer boundary of the annular peripheral region 312 and the outer boundary of the patterned photoresist layer 370 is in the range of 0.5 mm to 1.5 mm, preferably equal to 1 mm. In some embodiments, the distance between the inner boundary of the annular peripheral region 312 and the inner boundary of the patterned photoresist layer 370 is in the range of 0.5 mm to 1.5 mm, preferably equal to 1 mm. As mentioned above, in some embodiments, the height of the patterned photoresist layer 370 can be in the range of 1 / 2 to 3 / 4 of the average height of the plurality of solder balls 340 to be formed. Several advantages of such a configuration have been described above and will not be repeated here.
[0038] It is understood that masking and photolithography processes can be performed to control the pattern of the patterned photoresist layer 370. It is also understood that, in order to control the height of the patterned photoresist layer 370, a predetermined amount of photoresist material to cover the front surface 310 of the wafer substrate 300 can be pre-calculated, and the predetermined height can be achieved.
[0039] refer to Figure 3E Multiple solder balls 340 are formed on the solder ball area 311 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The materials of the multiple solder balls 340 can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and multiple combinations thereof, as well as optional flux solutions.
[0040] refer to Figure 3FA backside grind tape 350 is attached on the front side 310, covering both the solder ball region 311 and the annular peripheral region 312. The backside grind tape 350 can comprise a variety of materials, such as epoxy or acrylic materials with adhesive properties, which can be deposited using spin coating or screen printing methods.
[0041] Referring to Figure 3G A backside grinding process is performed on the backside 320 of the wafer substrate 300. Since the patterned photoresist layer 370 is disposed at the edge of the wafer substrate 300, the edge of the wafer 300 is fully supported during the grinding process. As a result, the grinding impact at the edge can be reduced. In some embodiments, the backside grinding process can comprise repeatedly using a grinding wheel to remove a predetermined amount of material from the backside 320 of the wafer substrate 300. It can be appreciated that the backside grind tape 350 can be removed after the backside grinding process.
[0042] Since the location of the patterned photoresist layer 370 is in the annular peripheral region 312, i.e., the patterned photoresist layer 370 is in a passive region, the patterned photoresist layer 370 will not affect the electrical functionality of the semiconductor units, and the patterned photoresist layer 370 does not need to be removed from the wafer substrate 300.
[0043] As mentioned above, thermoset materials are also suitable materials for the edge support of the wafer substrate. Figures 4A to 4C A portion of a wafer substrate 400 having a patterned thermoset material layer formed as an edge support in a plurality of wafer grinding steps is shown. Similar configurations can be referred to the above embodiments, which are not repeated here.
[0044] Referring to Figure 4A A wafer substrate 400 having a front side 410 and a backside 420 is provided. The front side 410 comprises a solder ball region 411 and an annular peripheral region 412 surrounding the solder ball region 411, and the solder ball region 411 is formed with a plurality of solder balls 440.
[0045] Next, a patterned thermoset material layer 470 can be formed on the front side 410 of the wafer substrate 400. The patterned thermoset material layer 470 at least partially covers the annular peripheral region 412, but exposes the solder ball region 411. In some embodiments, the patterned thermoset material layer 470 can be made of an epoxy material. The patterned thermoset material layer 470 can be formed by dispensing a thermoset material at a plurality of desired locations on the front side 410 and then curing using, for example, heating.
[0046] Similar to the above reference Figures 3A to 3GIn the illustrated embodiments, the patterned thermoset material layer 470 can be formed to completely cover or expose the saw streets of the plurality of semiconductor units of the wafer substrate 400. In some other embodiments, the distance between the outer boundary of the annular peripheral region 412 and the outer boundary of the patterned thermoset material layer 470 is in the range of 0.5 mm to 1.5 mm, preferably equal to 1 mm. In some embodiments, the distance between the inner boundary of the annular peripheral region 412 and the inner boundary of the patterned thermoset material layer 470 is in the range of 0.5 mm to 1.5 mm, preferably equal to 1 mm. As mentioned above, in some embodiments, the height of the patterned thermoset material layer 470 can be in the range of 1 / 2 to 3 / 4 of the average height of the plurality of solder balls 440 to be formed. The advantages of such configurations are as described above and will not be repeated here.
[0047] It can be appreciated that in order to control the pattern of the patterned thermoset material layer 470, a stencil and / or a screen can be used. It can also be appreciated that in order to control the height of the patterned thermoset material layer 470, a predetermined amount of thermoset material to cover the front surface 410 of the wafer substrate 400 can be pre-calculated and a predetermined height can be achieved.
[0048] Referring to Figure 4B , similar to the embodiments shown in Figure 3F , the backside grinding tape 450 is attached on the front side 410 to cover both the solder ball region 411 and the annular peripheral region 412. Referring to Figure 4C , similar to the embodiments shown in Figure 3G , a backside grinding process is performed on the backside 420 of the wafer substrate 400.
[0049] Since the location of the patterned thermoset material layer 470 is in the annular peripheral region 412, i.e., the patterned thermoset material layer 470 is in the passive region, the patterned thermoset material layer 370 will not affect the electrical functionality of the plurality of semiconductor units, and the patterned thermoset material layer 470 does not need to be removed from the wafer substrate 400.
[0050] It can be appreciated that the present application provides various methods for forming the edge support of a wafer, whereby the wafer undergoing the backside grinding process can have a lower risk of edge chipping, and the overall cost of backside grinding can be reduced.
[0051] The discussion herein includes a number of illustrative drawings showing semiconductor wafers and methods of wafer grinding. For the sake of clarity, the drawings do not show all aspects of each example component. Any example component and / or method provided herein can share any or all features with any or all other components and / or methods provided herein.
[0052] Various embodiments have been described herein with reference to the accompanying drawings. However, it is apparent that various modifications and changes can be made thereto, and additional embodiments can be implemented, without departing from the broader scope of the application as set forth in the appended claims. Moreover, other embodiments will be apparent from consideration of the specification and the practices of one or more embodiments of the application as disclosed herein. Thus, it is intended that the application and embodiments herein be considered as exemplary only with the true scope and spirit of the application being indicated by the list of claims.
Claims
1. A wafer polishing method characterized by, The method comprises: providing a wafer substrate comprising a front side and a back side, wherein the front side comprises a solder ball region and an annular peripheral region surrounding the solder ball region; forming a patterned photoresist layer on the front side of the wafer substrate, wherein the patterned photoresist layer at least partially covers the annular peripheral region but exposes the solder ball region; forming a plurality of solder balls on the solder ball region; attaching a backgrind tape on the front side to cover both the solder ball region and the annular peripheral region; and performing a backgrind process on the back side of the wafer substrate.
2. The method of claim 1, wherein, The distance between the outer boundary of the annular peripheral region and the outer boundary of the patterned photoresist layer is in the range of 0.5mm to 1.5mm.
3. The method of claim 1, wherein, The distance between the inner boundary of the annular peripheral region and the inner boundary of the patterned photoresist layer is in the range of 0.5mm to 1.5mm.
4. The method of claim 1, wherein, The distance between the outer boundary of the annular peripheral region and the outer boundary of the patterned photoresist layer is 1mm, and the distance between the inner boundary of the annular peripheral region and the inner boundary of the patterned photoresist layer is 1mm.
5. The method of claim 1, wherein, The patterned photoresist layer exposes or covers a plurality of saw streets of the wafer substrate in the annular peripheral region.
6. The method of claim 1, wherein, The height of the patterned photoresist layer is in the range of 1 / 2 to 3 / 4 of the average height of the plurality of solder balls.
7. A wafer polishing method characterized by, The method comprises: providing a wafer substrate comprising a front side and a back side, wherein the front side comprises a solder ball region and an annular peripheral region surrounding the solder ball region, wherein the solder ball region is formed with a plurality of solder balls; forming a patterned thermoset material layer on the front side of the wafer substrate, wherein the patterned thermoset material layer at least partially covers the annular peripheral region but exposes the solder ball region; attaching a backgrind tape on the front side to cover both the solder ball region and the annular peripheral region; and performing a backgrind process on the back side of the wafer substrate.
8. The method of claim 7, wherein, Forming a patterned thermoset material layer on the front side of the wafer substrate comprises dispensing a thermoset material on the front side of the wafer substrate.
9. The method of claim 7, wherein, The distance between the outer boundary of the annular peripheral region and the outer boundary of the patterned thermoset material layer is in the range of 0.5mm to 1.5mm.
10. The method of claim 7, wherein, The distance between the inner boundary of the annular peripheral region and the inner boundary of the patterned thermoset material layer is in the range of 0.5mm to 1.5mm.
11. The method of claim 7, wherein, The distance between the outer boundary of the annular peripheral region and the outer boundary of the patterned thermoset material layer is 1mm, and the distance between the inner boundary of the annular peripheral region and the inner boundary of the patterned thermoset material layer is 1mm.
12. The method of claim 7, wherein, The patterned thermoset material layer exposes or covers a plurality of saw streets of the wafer substrate.
13. The method of claim 7, wherein, The height of the patterned thermoset material layer is in the range of 1 / 2 to 3 / 4 of the average height of the plurality of solder balls.
14. The method of claim 7, wherein, The patterned thermoset material layer is made of an epoxy material. The patterned thermoset material layer is made of an epoxy material.