Power supply circuit and source carrier system

Abstract

The present application discloses a power supply circuit and a source load system, wherein the power supply circuit includes a power interface unit, a first capacitor and a second capacitor, an NMOS tube and a PMOS tube, the power interface unit includes an external power input terminal, a first ground terminal, a second ground terminal and a power output terminal, the other end of the first capacitor is respectively connected to the drain of the NMOS tube and the drain of the PMOS tube, the source of the NMOS tube is connected to the second ground terminal, and the source of the PMOS tube is respectively connected to the other end of the second capacitor and the first ground terminal; a control unit, the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence. It can be used as a power supply circuit for a non-common-ground source load system, without the problem of voltage drop, and has a small size, low price, and no high-frequency magnetic parts are introduced, and there is no electromagnetic interference.

Description

Technical Field

[0001] The present application relates to the field of source-carrying systems, and in particular to a power supply circuit and a source-carrying system. Background Art

[0002] At present, in some non-shared ground source-load systems, additional power supply circuits need to be configured. For example, in the buck circuit of the source-load system, there are upper MOS (Metal-Oxide-Semiconductor) tubes and lower MOS tubes in series. Since the reference ground of the upper MOS tube is different from the reference ground of the lower MOS tube, the reference Figure 8 As shown, the reference ground of the upper MOS tube is GND1, and the reference ground of the lower MOS tube is GND2, so a separate driving power supply needs to be provided for the upper MOS tube.

[0003] In the related art, one method is to use a bootstrap capacitor to drive the upper MOS tube, and the other method is to use an isolated power supply module to drive the upper MOS tube separately. However, the disadvantage of using the bootstrap capacitor method is that when the PWM wave works at a high duty cycle or extremely light load, the bootstrap capacitor may not be charged for a considerable period of time, and the voltage across the bootstrap capacitor will drop to a point where it is not enough to drive the upper MOS tube to fully turn on, resulting in a voltage drop problem; the disadvantage of the isolated power supply module is that it is expensive, large in size, not suitable for high power density occasions, and introduces high-frequency magnetic parts, which will cause electromagnetic interference to the source load system. Summary of the invention

[0004] The present application proposes a power supply circuit and a source-carrying system, which will not have the problem of voltage drop, and are small in size, low in price, and free from electromagnetic interference.

[0005] According to the first aspect of the present application, a power supply circuit is used to supply power to an upper MOS tube and a lower MOS tube connected in series, wherein the output end of the upper MOS tube is connected to a first ground end, and the output end of the lower MOS tube is connected to a second ground end, and comprises: a power interface unit, wherein the power interface unit comprises an external power input end and a power output end; a first capacitor and a second capacitor, wherein the external power input end is connected to one end of the first capacitor through a first unidirectional conduction module, and one end of the first capacitor is respectively connected to one end of the second capacitor and the power output end through a second unidirectional conduction module; an NMOS tube and a PMOS tube, wherein the other end of the first capacitor is respectively connected to the drain of the NMOS tube and the drain of the PMOS tube, the source of the NMOS tube is connected to the second ground end, and the source of the PMOS tube is respectively connected to the other end of the second capacitor and the first ground end; and a control unit, wherein the control unit is respectively connected to the gate of the NMOS tube and the gate of the PMOS tube, and the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence.

[0006] According to some embodiments of the present application, the control unit includes an MCU and a transistor, and a first PWM signal output terminal and a second PWM signal output terminal are provided on the MCU, the first PWM signal output terminal is connected to the gate of the NMOS tube, the second PWM signal output terminal is connected to the base of the transistor, the emitter of the transistor is connected to the second ground terminal, and the collector of the transistor is connected to the gate of the PMOS tube. The MCU controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset order through the first PWM signal and the second PWM signal.

[0007] According to some embodiments of the present application, the control unit further includes a first resistor and a second resistor, the gate of the NMOS tube is connected to the second ground terminal through the first resistor; the base of the transistor is connected to the second ground terminal through the second resistor.

[0008] According to some embodiments of the present application, a switch S1 and a third resistor are further included, and the gate of the PMOS tube is connected to the source of the PMOS tube through the switch S1 and the third resistor which are connected in sequence.

[0009] According to some embodiments of the present application, the first unidirectional conduction module is a first diode, the power input end is connected to the anode of the first diode, and the cathode of the first diode is connected to one end of the first capacitor.

[0010] According to some embodiments of the present application, the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence;

[0011] The conduction time of each NMOS tube is the same as the conduction time of each PMOS tube.

[0012] According to some embodiments of the present application, the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence;

[0013] Wherein, each conduction time of the NMOS tube is greater than each conduction time of the PMOS tube.

[0014] According to some embodiments of the present application, the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence;

[0015] Wherein, each turn-on time of the NMOS tube is shorter than each turn-on time of the PMOS tube.

[0016] According to some embodiments of the present application, the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence;

[0017] A dead time is set between the control unit controlling the NMOS tube to exit the conduction state and the PMOS tube to enter the conduction state, and a dead time is set between the control unit controlling the PMOS tube to exit the conduction state and the NMOS tube to enter the conduction state.

[0018] According to the second aspect of the present application, the source-carrying system includes the above-mentioned power supply circuit.

[0019] The power supply circuit and source-carrying system according to the embodiments of the present application have at least the following beneficial effects:

[0020] In the embodiment of the present application, a first ground terminal and a second ground terminal are provided in the power interface unit, and a first capacitor and a second capacitor connected in parallel are provided between the external power input terminal and the power output terminal. The control unit controls the NMOS tube and the PMOS tube to enter the on state in turn according to a preset sequence. When the NMOS tube is turned on, the first capacitor is charged through the external power input terminal, and when the PMOS tube is turned on, the second capacitor is charged through the first capacitor. Since the NMOS tube and the PMOS tube are turned on in turn, the first ground terminal and the second ground terminal will not be in the same ground. The second capacitor forms a power supply port that is not in the same ground with the external power supply through the power output terminal and the first ground terminal. Therefore, the present application can be used as a power supply circuit for a source-load system that is not in the same ground, and there will be no voltage drop problem. It is small in size, low in price, and does not introduce high-frequency magnetic parts, so there is no electromagnetic interference.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0023] Figure 1 is a circuit schematic diagram of a power supply circuit in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of a driving waveform of a MOS tube and a voltage waveform of a capacitor in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of current flow during a period in which the NMOS tube is turned on and the PMOS tube is turned off in an embodiment of the present application;

[0026] Figure 4A schematic diagram of current flow during a period in which the PMOS tube is turned on and the NMOS tube is turned off in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of a driving waveform of a MOS tube and a voltage waveform of a capacitor when a dead time is set in an embodiment of the present application;

[0028] Figure 6 for Figure 5 Schematic diagram of current flow in the time period t1~t2;

[0029] Figure 7 for Figure 5 Schematic diagram of current flow during the time period t4~t5;

[0030] Figure 8 This is the circuit schematic diagram of the upper MOS tube and the lower MOS tube in the buck circuit. DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0032] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0033] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0034] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0035] Reference Figure 1As shown, a power supply circuit includes: a power interface unit, a first capacitor C1 and a second capacitor C2, an NMOS tube Q1 and a PMOS tube Q2, and a control unit. Specifically, the power interface unit provides all power interfaces for input and output, specifically including an external power input terminal Vin, a first ground terminal GND1, a second ground terminal GND2, and a power output terminal. In this embodiment, the external power input terminal Vin is connected to an external power source, and the external power source can be a battery, a power adapter, or other DC power source. The first ground terminal GND1 serves as an output ground, and the second ground terminal GND2 serves as an input ground. The first capacitor C1 and the second capacitor C2, the external power input terminal Vin is connected to one end of the first capacitor C1 through a first unidirectional conduction module, and one end of the first capacitor C1 is respectively connected to one end of the second capacitor C2 and the power output terminal through a second unidirectional conduction module;

[0036] The NMOS tube Q1 and the PMOS tube Q2, the other end of the capacitor C1 are respectively connected to the drain of the NMOS tube Q1 and the drain of the PMOS tube Q2, the source of the NMOS tube Q1 is connected to the second ground terminal GND2, and the source of the PMOS tube Q2 is respectively connected to the other end of the capacitor C2 and the first ground terminal GND1; the control unit is respectively connected to the gate of the NMOS tube Q1 and the gate of the PMOS tube Q2, and the control unit controls the NMOS tube Q1 and the PMOS tube Q2 to enter the conduction state in turn according to a preset sequence.

[0037] In the embodiment of the present application, a first ground terminal GND1 and a second ground terminal GND2 are provided in the power interface unit, and a first capacitor C1 and a second capacitor C2 are provided in parallel in sequence between the external power input terminal Vin and the power output terminal. The control unit controls the NMOS tube Q1 and the PMOS tube Q2 to enter the on state in turn according to a preset sequence. When the NMOS tube Q1 is turned on, the first capacitor C1 is charged through the external power input terminal Vin, and when the PMOS tube Q2 is turned on, the second capacitor C2 is charged through the capacitor C1. Since the NMOS tube Q1 and the PMOS tube Q2 are turned on in turn, the first ground terminal GND1 and the second ground terminal GND2 will not be in the same ground. The second capacitor C2 forms a power supply port that is not in the same ground with the external power supply through the power output terminal and the first ground terminal GND1. Therefore, the present application can be used as a power supply circuit for a source-load system that is not in the same ground, and there will be no voltage drop problem. It is small in size, low in price, and does not introduce high-frequency magnetic parts, so there is no electromagnetic interference.

[0038] In the above implementation, the first unidirectional conduction module and the second unidirectional conduction module function to prevent backflow, that is, to prevent the first capacitor C1 from discharging to the external power input terminal Vin and to prevent the second capacitor C1 from discharging to the first capacitor C1 and the external power input terminal Vin.

[0039] In this embodiment, the first unidirectional conducting module adopts the first diode D1, and the second unidirectional conducting module adopts the second diode D2. In addition to the diode, other unidirectional conducting switch devices may also be used.

[0040] In the above embodiment, the control unit controls the NMOS tube Q1 and the PMOS tube Q2 to enter the on state in turn according to a preset sequence, which means that the control unit controls the NMOS tube Q1 and the PMOS tube Q2 to be turned on in turn through two PWM signals. Since they are turned on in turn, the NMOS tube Q1 and the PMOS tube Q2 will not be in the on state at the same time.

[0041] In some embodiments of the present application, the control unit may include an MCU and a transistor Q3, and the MCU is provided with a first PWM signal output terminal and a second PWM signal output terminal, the first PWM signal output terminal is connected to the gate of the NMOS tube Q1 through a resistor R1, the second PWM signal output terminal is connected to the base of the transistor Q3 through a resistor R3, the emitter of the transistor Q3 is connected to the second ground terminal GND2, and the collector of the transistor Q3 is connected to the gate of the PMOS tube Q2 through a resistor R5. The MCU controls the NMOS tube Q1 and the PMOS tube Q2 to enter the conduction state in turn according to a preset sequence through the first PWM signal and the second PWM signal.

[0042] It should be noted that, since the control methods of the PMOS tube and the NMOS tube are different, the PMOS tube Q2 in this embodiment is controlled to be turned on by the transistor Q3, that is, when the second PMW signal controls the transistor Q3 to be turned on, the gate of the PMOS tube Q2 is connected to the second ground terminal GND2. At this time, the PMOS tube Q2 is turned on. Therefore, the first PWM signal and the second PWM signal can use signals with the same reference ground, and a conventional MCU can be used without using complex hardware, thereby saving costs.

[0043] It should be understood that, in addition to the above methods, the control unit can also use two MCUs to control the on and off of the NMOS tube Q1 and the PMOS tube Q2 respectively. The two MCUs communicate with each other to ensure that the NMOS tube Q1 and the PMOS tube Q2 enter the on state in turn according to a preset order.

[0044] In some embodiments of the present application, the control unit may further include a first resistor R2 and a second resistor R4, the gate of the NMOS tube Q1 is connected to the second ground terminal GND2 through the first resistor R2; the base of the transistor Q3 is connected to the second ground terminal GND2 through the second resistor R4.

[0045] In this embodiment, the first resistor R2 and the second resistor R4 both act as pull-down resistors, playing a stable pull-down role, which can ensure that the NMOS transistor Q1 and the transistor Q3 are always in the off state when there is no PWM signal, thereby improving the overall stability of the circuit.

[0046] In some embodiments of the present application, the power supply circuit may further include a switch S1 and a third resistor R6, and the gate of the PMOS transistor Q2 is connected to the source of the PMOS transistor Q2 through the switch S1 and the third resistor R6 connected in sequence.

[0047] It should be noted that in order to avoid the problem of mis-conduction or breakdown due to residual voltage between the gate and source of the PMOS tube Q2, in this embodiment, a discharge circuit is formed between the gate and source of the PMOS tube by using the switch S1 and the third resistor R6, and when the power supply circuit stops working, the switch S1 is closed to discharge the GS pole charge of the PMOS tube Q2, thereby improving the reliability and safety of the overall circuit.

[0048] The working process of the above embodiment is described in detail below. In this embodiment, the capacitor charging time is ignored, t0-t2 is one cycle, and the specific process is as follows:

[0049] refer to Figure 2 and Figure 3 As shown, at time t0-t1, the first PWM signal is high level, and the second PWM signal is low level. At this time, the NMOS tube Q1 is turned on, and the PMOS tube Q2 is turned off. At this time, the current flows as follows Figure 3 As shown, the external power input terminal Vin charges the capacitor C1, and since the capacitor C2 has voltage in the initial state, the capacitor C2 is discharged alone.

[0050] refer to Figure 2 and Figure 4 As shown, at time t1-t2, the first PWM signal becomes low level, and the second PWM signal becomes low level. At this time, the NMOS tube Q1 is turned off, and the PMOS tube Q2 is turned on. At this time, the current flows as follows Figure 4 As shown, the external power input terminal Vin stops charging the capacitor C1. At this time, the capacitor C1 charges the capacitor C2. The capacitor C2 is charged first and then discharged, and then enters the next cycle.

[0051] In some embodiments of the present application, in the present application, the MCU controls the on and off of the NMOS tube Q1 through the first PWM signal, and controls the on and off of the PMOS tube Q2 through the second PWM signal. According to the different durations of the high and low levels of the first PWM signal and the second PWM signal in each cycle, the on time of Q1 and Q2 can be changed. Assuming that the on time of the NMOS tube Q1 in one cycle is ta, and the on time of the PMOS tube Q2 in one cycle is tb, there may be the following three operating modes for the on time of Q1 and Q2:

[0052] Working mode 1: Each on-time of the NMOS tube Q1 is the same as each on-time of the PMOS tube Q2, that is, ta=tb.

[0053] In working mode 2, each conduction time of the NMOS tube Q1 is greater than each conduction time of the PMOS tube Q2, that is, ta>tb.

[0054] Working mode three: each conduction time of the NMOS tube Q1 is shorter than each conduction time of the PMOS tube Q2, that is, ta<tb.

[0055] It should be noted that when ta>tb, the duration of charging capacitor C1 and discharging capacitor C2 alone increases. At this time, the voltage drop of the circuit output is smaller, but the output ripple is larger. When ta<tb, that is, the charging time of capacitor C1 is reduced, and the time for capacitor C1 and capacitor C2 to discharge together is increased. The output ripple can be reduced, but the voltage drop is larger. Therefore, control method 2 is suitable for application scenarios that pursue small output ripple, such as op amp power supply, and control method 3 is suitable for application scenarios that pursue output voltage accuracy but are insensitive to output ripple, such as IGBT drive. Control method 1 is suitable for compromise application scenarios.

[0056] In the present application, three working modes can be divided according to the different conduction times of the NMOS tube Q1 and the PMOS tube Q2, which are suitable for different application scenarios. Different working modes can be set for different application scenarios to improve the scope of application.

[0057] In some embodiments of the present application, the control unit controls the NMOS tube Q1 and the PMOS tube Q2 to enter the conduction state in turn according to a preset sequence;

[0058] There is a dead time between when the control unit controls the NMOS tube Q1 to exit the conduction state and the PMOS tube Q2 to enter the conduction state, and there is a dead time between when the control unit controls the PMOS tube Q2 to exit the conduction state and the NMOS tube Q1 to enter the conduction state.

[0059] In this implementation, by setting the dead time, it is possible to completely avoid the situation where the NMOS transistor Q1 and the PMOS transistor Q2 are turned on at the same time, thereby further improving the reliability of the circuit.

[0060] refer to Figure 5 As shown, in the case of setting a dead time, the workflow of the present application is further described in detail, t0-t6 is a cycle, VC1 waveform is the voltage across capacitor C1, VC2 waveform is the voltage across capacitor C2, and the specific process is as follows:

[0061] At t0: NMOS tube Q1 starts to conduct;

[0062] Time period t0~t1: Capacitor C1 is charged, and the voltage across capacitor C1 rises rapidly from VA1 to VA3. Capacitor C2 provides output current for discharge. The current flows as follows: Figure 3 As shown;

[0063] At t1: capacitor C1 is quickly charged to VA3;

[0064] During the time period t1-t2: the voltage across capacitor C1 remains unchanged at VA3, capacitor C2 discharges and provides output current, and the capacitor flows in the following direction: Figure 6 As shown;

[0065] At t2: NMOS tube Q1 is turned off;

[0066] Time period t2-t3: It is the dead time before the PMOS tube Q2 is turned on, which prevents the NMOS tube Q1 and the PMOS tube Q2 from being turned on at the same time. At this time, the voltage across the capacitor C1 remains unchanged at VA3, and the capacitor C2 discharges to provide output current. The current flow direction is the same as that in the time period t1-t2;

[0067] At t3: PMOS tube Q2 is turned on, and the voltage across capacitor C2 is VB1;

[0068] Time period t3-t4: At this time, capacitor C1 is discharged and capacitor C2 is charged. The current flows as follows: Figure 4 As shown;

[0069] Time t4: At this time, VC1=VC2+VF, and capacitor C2 stops charging, where VF is the conduction voltage drop of diode D1;

[0070] Time period t4~t5: Capacitor C1 discharges, and capacitor C2 also discharges at the same time. The current flows as follows: Figure 7 As shown;

[0071] At t5: PMOS tube Q2 is turned off;

[0072] Time period t5~t6: It is the dead time before NMOS tube Q1 is turned on. At this time, the voltage across capacitor C1 remains unchanged, capacitor C2 discharges, and the current flows to the same direction as Figure 4 same;

[0073] At time t6, NMOS tube Q1 is turned on, entering a new cycle and repeating the above process.

[0074] The present invention also relates to a source-carrying system, comprising the power supply circuit of the above embodiment.

[0075] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A power supply circuit, characterized in that: include: A power interface unit, the power interface unit comprising an external power input terminal, a first ground terminal, a second ground terminal and a power output terminal; A first capacitor and a second capacitor, wherein the external power input terminal is connected to one end of the first capacitor through a first unidirectional conduction module, and one end of the first capacitor is respectively connected to one end of the second capacitor and the power output terminal through a second unidirectional conduction module; NMOS tube and PMOS tube, the other end of the first capacitor is respectively connected to the drain of the NMOS tube and the drain of the PMOS tube, the source of the NMOS tube is connected to the second ground terminal, and the source of the PMOS tube is respectively connected to the other end of the second capacitor and the first ground terminal; A control unit, wherein the control unit is connected to the gate of the NMOS tube and the gate of the PMOS tube respectively, and the control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence.

2. The power supply circuit according to claim 1, characterized in that: The control unit includes an MCU and a transistor. The MCU is provided with a first PWM signal output terminal and a second PWM signal output terminal. The first PWM signal output terminal is connected to the gate of the NMOS tube, the second PWM signal output terminal is connected to the base of the transistor, the emitter of the transistor is connected to the second ground terminal, and the collector of the transistor is connected to the gate of the PMOS tube. The MCU controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence through the first PWM signal and the second PWM signal.

3. The power supply circuit according to claim 2, characterized in that: The control unit further includes a first resistor and a second resistor, the gate of the NMOS tube is connected to the second ground terminal through the first resistor; the base of the transistor is connected to the second ground terminal through the second resistor.

4. The power supply circuit according to claim 2, characterized in that: It also includes a switch S1 and a third resistor, and the gate of the PMOS tube is connected to the source of the PMOS tube through the switch S1 and the third resistor which are connected in sequence.

5. The power supply circuit according to claim 1, characterized in that: The first unidirectional conducting module is a first diode, the power input end is connected to the anode of the first diode, and the cathode of the first diode is connected to one end of the first capacitor.

6. The power supply circuit according to claim 1, characterized in that: The control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence; The conduction time of each NMOS tube is the same as the conduction time of each PMOS tube.

7. The power supply circuit according to claim 1, characterized in that: The control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence; Wherein, each conduction time of the NMOS tube is greater than each conduction time of the PMOS tube.

8. The power supply circuit according to claim 1, characterized in that: The control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence; Wherein, each turn-on time of the NMOS tube is shorter than each turn-on time of the PMOS tube.

9. The power supply circuit according to claim 1, characterized in that: The control unit controls the NMOS tube and the PMOS tube to enter the conduction state in turn according to a preset sequence; A dead time is set between the control unit controlling the NMOS tube to exit the conduction state and the PMOS tube to enter the conduction state, and a dead time is set between the control unit controlling the PMOS tube to exit the conduction state and the NMOS tube to enter the conduction state.

10. A source-carrying system, characterized in that: A power supply circuit comprising any one of claims 1 to 9.

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