Semiconductor device and preparation method thereof

By forming alternately arranged sacrificial layers and protective layers on the substrate and forming a capacitor structure during the etching process, the problem of the substrate being easily damaged during the etching process in the three-dimensional memory is solved, and effective protection of the substrate and improvement of device performance are achieved.

CN119697991AActive Publication Date: 2025-03-25RUILI INTEGRATED CIRCUIT CO LTD
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Patent Information

Application Number
CN202411834410.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-12
Publication Date
2025-03-25
Estimated Expiration
2044-12-12

AI Technical Summary

Technical Problem

When making three-dimensional memory, when etching the stack layer by lateral wet etching, the substrate is susceptible to severe damage, resulting in device failure.

Method used

An alternately arranged stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers is formed on the substrate, the second sacrificial layer being the same as the substrate material. Then, by forming a protective layer on the substrate surface as an etch stop layer, part of the second sacrificial layer in the stacked layer is etched laterally along the vertical opening to form a side cavity, and a lower electrode, a capacitance dielectric layer and an upper electrode are formed on the side cavity surface to form a capacitor structure.

Benefits of technology

Through the use of the protective layer, the substrate is effectively protected, the substrate is avoided damage during the etching process, the performance of the device is improved, and the leakage current is reduced.

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Abstract

The invention discloses a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the steps that a substrate is provided, a stacking layer formed by alternately arranging a plurality of first sacrificial layers and a plurality of second sacrificial layers is formed on the substrate, and the second sacrificial layers and the substrate are made of the same material; forming a vertical opening penetrating through the stack layer, extending into the substrate, and forming a cavity in the substrate; forming a protective layer in the concave cavity of the substrate; taking the protection layer as an etching stop layer, and transversely etching a part of the second sacrificial layer in the stack layer along the vertical opening to form a plurality of side cavities which are arranged at intervals in the vertical direction; forming a plurality of lower electrodes on the surface of the second sacrificial layer exposed by the plurality of side cavities; forming a capacitor dielectric layer on the surfaces of the plurality of lower electrodes, wherein the capacitor dielectric layer is also located in the vertical opening and is in contact with the protection layer; an upper electrode is formed on the surface of the capacitor dielectric layer, and the multiple lower electrodes, the capacitor dielectric layer and the upper electrode form a capacitor structure. The embodiment of the invention can improve the performance of the device.
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