Cycle by cycle delay compensated zero crossing detection circuit

Abstract

The application discloses a zero-crossing detection circuit with period-by-period delay compensation, a first current generating module output end is connected with a sampling capacitor C1 and a compensation resistor Rc simultaneously, the other end of the sampling capacitor C1 is grounded, the other end of the compensation resistor Rc is connected with a first input end of a first sampling module, an output end of a compensation calculation module and an inverting input end of a zero-crossing comparison module simultaneously, and the output end of the first sampling module is connected with the first input end of the compensation calculation module; a second current generating module output end is connected with a sampling capacitor C2, a first input end of a second sampling module and a non-inverting input end of the zero-crossing comparison module simultaneously, the output end of the second sampling module is connected with a third input end of the compensation calculation module, and the other end of the sampling capacitor C2 is grounded; and a second input end of the compensation calculation module is connected with an S1 signal. The application belongs to the technical field of zero-crossing detection of switching power supplies, realizes stable high-precision delay compensation, and has higher conversion efficiency.

Description

Technical Field

[0001] This invention belongs to the field of zero-crossing detection technology of switching power supplies, and relates to a cycle-by-cycle delay compensation zero-crossing detection circuit. Background Technology

[0002] In boost-type DC-DC converters, MOSFETs are often chosen as synchronous freewheeling diodes to improve system efficiency under light loads. However, MOSFETs do not possess the unidirectional conductivity of diodes. This means that when the inductor current is below zero, the MOSFET cannot automatically turn off, causing the inductor current to continue decreasing. When the inductor current is less than zero, it is equivalent to drawing charge from the load capacitance, ultimately leading to a decrease in conversion efficiency. Traditional zero-crossing detection circuits determine the zero-crossing detection point by detecting the magnitude of the source-drain voltage of the Mp transistor. Therefore, current mainstream optimization schemes address these two issues.

[0003] To address the offset voltage problem caused by comparator mismatch, the literature [1] (Q.Kuai, Q.Wan and PKTMok, "A Dual-Frequency Thermal Energy Harvesting Interface With Real-Time-Calculation ZCD," in IEEE Journal of Solid-State Circuits, vol.56, no.9, pp.2736-2747, Sept.2021) proposed a zero-crossing detection time calculation circuit. Utilizing the inductor volt-second balance rule, the system parameters VIN and VOUT are converted into current. When the lower transistor is on, VIN is converted into current to charge the capacitor. When the freewheeling transistor is on, the voltage VOUT minus VIN is converted into current to charge the same capacitor. When the two voltages are equal, the charging and discharging energies are the same, which can be considered as the zero-crossing detection time. This method transforms the comparison of the freewheeling transistor source-drain voltage into a comparison of the capacitor charging voltage, amplifying the voltage variation range and effectively reducing the influence of comparator offset voltage. However, the reference [1] only made a rough compensation for the effect of the comparator's inherent delay. When the system parameters change, the problem of the synchronous freewheeling tube parasitic diode turning on or current flowing back will occur, resulting in a decrease in efficiency.

[0004] To address the inherent delay of comparators, existing solutions involve superimposing a fixed bias signal at the input of the zero-crossing comparator module to compensate for its inherent delay. However, such a bias signal is not suitable for all applications. Changes in temperature, inductor values, or output voltage will prevent the bias signal from effectively eliminating the effects of the zero-crossing comparator module's delay, leading to overcompensation or undercompensation and a decrease in conversion efficiency. Therefore, there is an urgent need to develop a delay compensation circuit to solve the problem of reduced system conversion efficiency caused by internal delay. Summary of the Invention

[0005] The purpose of this invention is to provide a cycle-by-cycle delay compensation zero-crossing detection circuit, which solves the problem in the prior art where overcompensation or undercompensation causes the synchronous freewheeling tube to turn off too early or too late, resulting in a decrease in conversion efficiency when using fixed delay compensation.

[0006] The technical solution adopted in this invention is a cycle-by-cycle delay compensation zero-crossing detection circuit. The output terminal of the first current generating module is simultaneously connected to the sampling capacitor C1 and the compensation resistor Rc. The other end of the sampling capacitor C1 is grounded. The other end of the compensation resistor Rc is simultaneously connected to the first input terminal of the first sampling module, the output terminal of the compensation calculation module, and the inverting input terminal of the zero-crossing comparison module. The second input terminal of the first sampling module is connected to the Sample signal, and the output terminal of the first sampling module is connected to the first input terminal of the compensation calculation module. The output terminal of the second current generating module is simultaneously connected to the sampling capacitor C2, the first input terminal of the second sampling module, and the non-inverting input terminal of the zero-crossing comparison module. The second input terminal of the second sampling module is connected to the Sample signal, and the output terminal of the second sampling module is connected to the third input terminal of the compensation calculation module. The other end of the sampling capacitor C2 is grounded. The second input terminal of the compensation calculation module is connected to the S1 signal.

[0007] The beneficial effects of this invention include the following aspects:

[0008] 1) Compared with the high-precision digital zero-crossing detection scheme, the present invention has a faster compensation speed. Existing high-precision digital zero-crossing detection requires multiple cycles to stabilize, while the present invention can achieve stable high-precision delay compensation after two cycles, which is more efficient.

[0009] 2) Existing digital circuits often require ADC modules, which consume a large amount of layout area to achieve high-precision compensation. Therefore, the present invention has a greater advantage in terms of layout area.

[0010] 3) This invention uses external system parameters as zero-crossing detection information. When the external system parameters change, the compensation voltage can be adaptively adjusted, which is safer and more efficient than traditional fixed delay compensation.

[0011] 4) This invention achieves dynamic adjustment of the compensation voltage by sampling the voltage change caused by the comparator delay in the previous cycle as the compensation amount and compensating in the next cycle. This results in higher conversion efficiency compared to the traditional fixed delay compensation system. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a traditional zero-crossing detection circuit;

[0013] Figure 2 This is a schematic diagram of the zero-crossing detection circuit with cycle-by-cycle delay compensation of the present invention;

[0014] Figure 3 This is a simplified schematic diagram of the principle structure of the compensation calculation module in the circuit of this invention;

[0015] Figure 4 This is a simplified schematic diagram of the logic module in the circuit of this invention.

[0016] Figure 5 This is a waveform diagram of the zero-crossing detection timing of the cycle-by-cycle delay compensation of the present invention;

[0017] Figure 6 The diagram shows the simulation results of existing technology using a fixed delay compensation circuit.

[0018] Figure 7 This is a simulation waveform diagram of the zero-crossing detection circuit with cycle-by-cycle delay compensation of the present invention;

[0019] Figure 8 This is a simulation waveform diagram of the present invention with a VIN voltage of 5V and a VOUT voltage of 6.5V.

[0020] Figure 9 This is a simulation waveform diagram of the present invention with a VIN voltage of 5V and a VOUT voltage of 8.2V.

[0021] In the diagram, C1, C2, C C All are sampling capacitors; Rc is a compensation resistor; Mp1, Mn1, Mn2, and Mn4 are all image transistors; Mn3 is a switching transistor; M1 and M2 are both power switching MOSFETs; L0 is an inductor; C0 is a load capacitor; INV1, INV2, INV3, INV4, INV5, INV6, and INV7 are all inverters; AND1 and AND2 are both AND gates; NAND1, NAND2, and NAND3 are both NAND gates; NOR1 is a NOR gate. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0023] The terms "first" and "second" used in the following text are for descriptive purposes only. Related features and components are described intuitively in relation to the corresponding drawings and should not be construed as indicating or implying relative importance. They do not limit the installation positions of components within the device structure; actual installation positions are determined accordingly. For clarity, the various parts in the drawings are not drawn to scale, and certain details have been omitted.

[0024] Reference Figure 1This diagram illustrates a traditional zero-crossing detection circuit. This circuit determines the zero-crossing detection point by detecting the magnitude of the source-drain voltage of the Mp transistor. When the Mn transistor is off and the Mp transistor is on, the COMP comparator outputs a zero-crossing detection signal when the source-drain voltage of the Mp transistor is equal. This signal, after passing through the SR flip-flop, controls the turn-off of the Mp transistor. Firstly, because the on-resistance of the MOSFET is low, the voltage difference between the source and drain is small. Furthermore, the offset voltage problem caused by comparator mismatch can cause the zero-crossing detection point to be earlier or later than expected. Secondly, the inherent delay of the comparator and the system delay can cause the synchronous freewheeling transistor to fail to turn off in time, resulting in current backflow and a decrease in system conversion efficiency.

[0025] Reference Figure 2 The structure of the cycle-by-cycle delay compensation zero-crossing detection circuit of the present invention includes a first current generation module, a second current generation module, a first sampling module, a second sampling module, sampling capacitors C1 and C2, a compensation resistor Rc, a compensation calculation module, a zero-crossing comparison module, a logic module, a first driving module, a second driving module, and a DC-DC power stage circuit.

[0026] The first input terminal of the first current generation module is connected to the input VIN of the DC-DC power stage circuit, and the second input terminal is connected to T. ON The signal, the third input terminal is connected to the Clear signal, and the output terminal of the first current generation module (called the internal node V) X The sampling capacitor C1 and the compensation resistor Rc are connected simultaneously. The other end of the sampling capacitor C1 is grounded, and the other end of the compensation resistor Rc is connected to the first input terminal of the first sampling module, the output terminal of the compensation calculation module, and the inverting input terminal of the zero-crossing comparison module (referred to as internal node V). X_REAL The first sampling module is connected to the second input terminal of the first sampling module, which is connected to the sample signal. The output terminal of the first sampling module is connected to the first input terminal of the compensation calculation module.

[0027] The first input terminal of the second current generating module is connected to the input VIN of the DCDC power stage circuit, the second input terminal is connected to the output VOUT of the DCDC power stage circuit, and the third input terminal is connected to T. OFF The signal, the fourth input terminal is connected to the Clear signal, and the output terminal of the second current generation module (called internal node V) Y The sampling capacitor C2 is connected to the sampling capacitor C2, the first input terminal of the second sampling module, and the non-inverting input terminal of the zero-crossing comparison module. The second input terminal of the second sampling module is connected to the Sample signal, and the output terminal of the second sampling module is connected to the third input terminal of the compensation calculation module. The other end of the sampling capacitor C2 is grounded. The second input terminal of the compensation calculation module is connected to the S1 signal.

[0028] As can be seen, the first sampling module is used to sample the internal node V of the previous cycle.X Point voltage, the second sampling module is used to sample the internal node V of the previous cycle. Y The zero-crossing detection compensation voltage is adaptively adjusted in the next cycle based on the VIN voltage. The first current generation module, based on the magnitude of the VIN voltage, simulates the rising slope of the inductor current and adaptively adjusts the internal node V... X The voltage at the point; the second current generation module, based on the magnitudes of the VOUT and VIN voltages, simulates the decreasing slope of the inductor current and adaptively adjusts the internal node V. Y The voltage at that point.

[0029] Reference Figure 3 The internal structure of the compensation calculation module includes mirror transistors Mp1, Mn1, Mn2, a switching transistor Mn3, and Mn4. The drain of mirror transistor Mp1 is connected to the drain of mirror transistor Mn1, the drain and gate of mirror transistor Mn2, and the source of switching transistor Mn3. The drain of switching transistor Mn3 is connected to the sampling capacitor Cc and the gate of mirror transistor Mn4. The drain of mirror transistor Mn4 is connected to the other end of the compensation resistor Rc and the inverting input of the zero-crossing comparator module. The sources of mirror transistors Mn1, Mn2, and Mn4 are all grounded. The mirror ratio from Mn2 to Mn4 is 1:N. The compensation calculation is used to convert the sampled voltage into a current, and the difference between the currents flows through Mn4 and the compensation resistor Rc to adaptively adjust the compensation voltage.

[0030] The inverting input of the zero-crossing comparator module is connected to the other end of the compensation resistor Rc, the input of the first sampling module, and the drain of the mirror transistor Mn4. The inverting input of the zero-crossing comparator module is connected to the sampling capacitor C2 and the output of the second current generation module. The output of the zero-crossing comparator module is connected to the input of the logic module. The zero-crossing comparator module generates a zero-crossing detection (ZCD) signal, which, through the logic module and driver module one, controls the turn-off of the power switch MOSFET M2. The output of the logic module is connected to the input of driver module one. The logic module generates the logic signals required by each module, and the output of driver module one is connected to the DC-DC power stage circuit.

[0031] The structure of the DC-DC power stage circuit includes power switching MOSFETs M1 and M2, inductor L0, and load capacitor C0. The gate of power switching MOSFET M2 is connected to the output terminal of the driver module. OFFThe signal is connected to the input terminal of drive module one. The drain of power switch MOSFET M2 is grounded through load capacitor C0. The source of power switch MOSFET M2, the drain of power switch MOSFET M1, and inductor L0 are all connected to the internal port SW. The other end of inductor L0 is connected to VIN voltage. The gate of power switch MOSFET M1 is connected to the output terminal of drive module two. The Ton signal is connected to the input terminal of drive module two. The source of power switch MOSFET M1 is grounded.

[0032] Reference Figure 4 The logic module structure includes eight inverters (namely, the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, and the eighth inverter INV8), three NAND gates (the first NAND gate NAND1, the second NAND gate NAND2, and the third NAND gate NAND3), two AND gates (the first AND gate AND1 and the second AND gate AND2), the first NOR gate NOR1, delay module one, and delay module two.

[0033] The input of the second inverter INV2 is connected to the output of the zero-crossing comparator module to receive the ZCD signal output by the zero-crossing comparator module; the output of the second inverter INV2 is also connected to the input of the third inverter INV3 and the input of the first delay module, and the output of the first delay module is connected to the input of the first inverter INV1; the delayed signal of the zero-crossing detection signal output by the first inverter INV1 is used as the first input of the first NAND gate NAND1; the output of the third inverter INV3 is connected to the second input of the first NAND gate NAND1 and the input of the fourth inverter INV4.

[0034] The input of the fifth inverter INV5 receives the on / off state signal Ton from the power switch MOSFET M1; the output of the fourth inverter INV4 is connected to the first input of the second NAND gate NAND2; the output of the fifth inverter INV5 is simultaneously connected to the second input of the third NAND gate NAND3 and the second input of the first AND gate AND1; the output of the third NAND gate NAND3 is connected to the second input of the second NAND gate NAND2; the output of the second NAND gate NAND2 is simultaneously connected to the first input of the third NAND gate NAND3 and the first input of the first AND gate AND1.

[0035] The input of delay module 2 receives the start and end times (CLK signal) of each cycle; the output of delay module 2 is connected to the input of the sixth inverter INV6; the output of the sixth inverter INV6 is connected to the input of the seventh inverter INV7; the output of the seventh inverter INV7 is simultaneously connected to the input of the eighth inverter INV8 and the first input of the first NOR gate NOR1; the first input of the second AND gate AND2 and the second input of the first NOR gate NOR1 simultaneously receive the start and end times (CLK signal) of each cycle.

[0036] As can be seen, the output signals of the logic module are: the first NAND gate NAND1 outputs a pulse signal after triggering the zero-crossing protection signal ZCD in each cycle, which is used to sample the voltage at the two input terminals of the zero-crossing comparator at the end of each cycle; the first AND gate outputs T... OFF The signal outputs a high-level signal during the period from when the switching MOSFET M1 is turned off to when the ZCD signal is output in each cycle. This signal is used to control the working state of the second current generation module and, through the drive module, to control the working state of the switching MOSFET M2 under light load. The second AND gate AND2 outputs the S1 signal to control the working state of the compensation module switching transistor Mn3, ensuring that the mirror transistor Mn4 receives the correct compensation current in each cycle. The first NOR gate NOR1 outputs the Clear signal, which generates a high-level signal at the end of each cycle as a clear signal for the voltage at the two input terminals of the zero-crossing comparator module.

[0037] Driver module one is used to drive power switch MOSFET M2; driver module two is used to drive power switch MOSFET M1.

[0038] The zero-crossing detection circuit with cycle-by-cycle delay compensation described above in this invention is embedded in a chip and is called a switching power supply chip.

[0039] Using the cycle-by-cycle delay compensation zero-crossing detection circuit described above, the detection process is as follows:

[0040] When the switching power supply chip operates in light-load mode, the first current generation module converts the external system parameter VIN into current, and the second current generation module converts VIN and VOUT into current. When power switch MOSFET M1 is turned on, sampling capacitor C1 is charged; when power switch MOSFET M2 is turned on, sampling capacitor C2 is charged. When power switch MOSFET M1 is turned off, the voltage at the non-inverting and inverting input terminals of the zero-crossing comparator module represents the energy of the inductor current. When the zero-crossing comparator module detects that the voltages at the two input terminals are equal, it indicates that the stored energy and released energy of the inductor are equal, and at this time, a zero-crossing detection ZCD signal is output. Due to the internal delay of the comparator, the zero-crossing detection point will be later than the moment when the two voltages of the zero-crossing comparator module are equal. After detecting the ZCD signal, the logic module outputs a control signal T. OFFThe second current generating module is controlled to stop charging, maintaining the internal node V. Y The voltage is measured, and a sample signal is output to control the operation of the first and second sampling modules. Due to the comparator delay, V... Y When a voltage overshoot occurs, the compensation calculation module compensates for the V voltage caused by the delay. Y The overshoot voltage is converted into a compensation current that flows through the mirror transistor Mn4 and is superimposed on the compensation resistor Rc in the next cycle to adjust the compensation voltage.

[0041] This cycle repeats. If the comparator delay in the previous cycle is large, the compensation current will be larger, and the actual zero-crossing detection trigger threshold in the next cycle will be lowered. This allows the zero-crossing detection to be triggered earlier in the next cycle, achieving cycle-by-cycle delay compensation, improving the accuracy of zero-crossing detection, and increasing the system's conversion efficiency.

[0042] The compensation working principle of this invention is as follows:

[0043] When power switching MOSFETs M1 and M2 are turned on in the first cycle, the first current generation module simulates the rising slope of the inductor current, converts VIN into a charging current, charges the sampling capacitor C1, and generates a current I. ON The second current generation module is used to simulate the downward slope of the inductor current, converting VOUT into a charging current to charge the sampling capacitor C2. The second current generation module generates a current I. OFF , respectively represented as:

[0044] V IN ·K=I ON (1)

[0045] (V OUT -V IN )·K=I OFF (2)

[0046] Wherein, coefficient K is the current proportionality coefficient of the first current generation module and the second current generation module. When the power switch MOSFET M1 is turned on, it controls the current I... ON The load is applied to the sampling capacitor C1. When the power switch MOSFET M1 is turned off, the logic module outputs T. OFF The signal controls the first current generation module to stop charging. Since the compensation calculation module did not work during the first cycle, the internal node V... X With V X_REAL The voltages are equal. When the power switch MOSFET M2 is turned on, the control will control the current I... OFF The load is applied to the sampling capacitor C2.

[0047] Zero-crossing detection pre-trigger threshold V XThe zero-crossing detection voltage Vy is expressed as follows:

[0048]

[0049]

[0050] The zero-crossing comparator module detects the voltages at its two input terminals. When the voltages at the two input terminals are equal, it generates a ZCD signal. Due to the comparator's internal delay, the ZCD signal will be delayed beyond the zero-crossing point, causing the power switch MOSFET M2 to turn off later than the zero-crossing point. Therefore, the internal node V... Y The point voltage will continue to increase due to the delay. When the power switch MOSFET M2 is turned off, the logic module outputs T. OFF The signal controls the second current generation module to stop charging; assuming the comparator's internal delay is T. delay The voltage change at the inverting input of the zero-crossing comparator caused by the delay is V. delay As shown in equation (5):

[0051]

[0052] Reference Figure 3 When the zero-crossing comparator outputs the ZCD signal, the logic signal outputs the Sample sampling signal to control the operation of the first sampling module and the second sampling module. The two sampled voltages are converted into currents flowing through the image transistors Mp1 and Mn1 respectively by the compensation calculation module. The current after the difference between the two currents flows through the image transistor Mn2. At the beginning of each cycle, the switching transistor Mn3 is turned on. The compensation current flows through the image transistor Mn4 and the compensation resistor Rc. Assuming that the current flowing through the image transistor Mn4 is Ic, the expression is as shown in equation (6):

[0053]

[0054] When this current flows through the compensation resistor Rc, the actual voltage V at the inverting terminal of the comparator in the next cycle is... X_REAL The expression is as shown in equation (7):

[0055] V X_REAL =V X -NV delay R c (7)

[0056] It can be seen that by reasonably setting the values ​​of parameters N and Rc so that their product is 1, the voltage change at the inverting terminal of the zero-crossing comparator module caused by the delay can be made equal to the voltage change at the inverting terminal of the zero-crossing comparator module caused by the compensation circuit. By compensating the comparator delay of the previous cycle in the next cycle, the ideal offset voltage can be obtained during the zero-crossing detection and comparison operation, thus eliminating the problem of the zero-crossing point being too late due to the comparator delay.

[0057] The following describes the fixed delay-compensated zero-crossing detection circuit and the cycle-by-cycle delay-compensated zero-crossing detection circuit of the present invention in conjunction with embodiments and simulation results. According to the aforementioned structure, the fixed delay-compensated zero-crossing detection circuit and the cycle-by-cycle delay-compensated zero-crossing detection circuit of the present invention were constructed respectively in a certain BCD process library, and then compared and verified through simulation.

[0058] Example 1

[0059] according to Figure 2 The aforementioned structure forms the zero-crossing detection circuit with cycle-by-cycle delay compensation of the present invention.

[0060] Reference Figure 5 IL is the current in the inductor L0 of the switching power supply chip. During the first switching cycle, when the power switching MOSFET M1 is turned on and the power switching MOSFET M2 is turned off, the first current generation module generates a current I. ON The sampling capacitor C1 is charged. When the OCP or DUTY signal is triggered, power switch MOSFET M1 is turned off, power switch MOSFET M2 is turned on, and the logic module outputs T. OFF Signal control I ON The current stops charging, maintaining the internal node V. X_REAL The voltage at the point; simultaneously, the second current generating module is controlled to generate current I. OFF The sampling capacitor C2 is charged, and the zero-crossing comparator module outputs a ZCD signal by comparing the two voltages. However, due to the comparator delay, the voltage change at the non-inverting input of the zero-crossing comparator module causes the zero-crossing detection point to be too late, resulting in inductor current reversal. At this time, the logic module generates a Sample sampling signal through the ZCD signal to control the operation of the first and second sampling modules. The compensation calculation module converts the voltage difference between the two input terminals of the zero-crossing comparator module into current, which flows through the compensation resistor Rc, adaptively adjusting the internal node V. X_REAL The voltage at the zero-crossing comparator module is adjusted so that the voltage change at the inverting input caused by the compensation circuit is equal to the voltage change at the non-inverting input caused by the delay, thus ensuring accurate zero-crossing. In the next cycle, it can be seen that the compensated inductor current is switched off at the zero-crossing point, without any current backflow.

[0061] Example 2

[0062] according to Figure 2 The structure described above is used to construct the zero-crossing detection circuit with cycle-by-cycle delay compensation of the present invention, and the zero-crossing detection of the present invention is compared and verified with that of the traditional fixed delay compensation zero-crossing circuit.

[0063] Reference Figure 6 , Figure 7 ,in, Figure 6 This is a simulation result diagram of existing technology using a fixed delay compensation circuit. Figure 7This is a simulation result diagram of the cycle-by-cycle delay compensation zero-crossing detection circuit of the present invention. The system simulation conditions are all output voltage 6.5V, input voltage 5V, and inductance 4.7μH. Figure I... L This refers to the inductor current L0 of the switching power supply chip, and SW is the internal port of the power stage DC-DC converter. Simulation results show that with a fixed delay compensation circuit, the synchronous freewheeling MOSFET M2 is turned off 132ns before the inductor current zero-crossing point. At this time, the parasitic body diode of M2 conducts, the voltage at point SW increases, and the inductor current still flows through the parasitic body diode, resulting in a decrease in efficiency. In this invention, the actual zero-crossing point is triggered only 12ns in advance, preventing inductor current backflow and reducing the efficiency decrease in light-load mode caused by the power dissipation of the parasitic body diode. Simulation results show that the conversion efficiency of this invention reaches 94.5% in light-load mode.

[0064] Example 3

[0065] according to Figure 2 The structure described above is used to construct the cycle-by-cycle delay compensation zero-crossing detection circuit of the present invention, and to illustrate the impact of the present invention on zero-crossing detection under different system conditions.

[0066] Reference Figure 8 , Figure 9 ,in, Figure 8 This is a simulation waveform diagram of the present invention with a VIN voltage of 5V and a VOUT voltage of 6.5V. Figure 9 This is a simulation waveform diagram of the present invention under VIN voltage of 5V and VOUT voltage of 8.2V. The simulation shows that no inductor current reverse flow occurred at the zero-crossing point, and the conduction time of the parasitic body diode of transistor M2 was less than 15ns. Therefore, the power consumption caused by the parasitic body diode of transistor M2 is negligible under light load mode. The simulation results demonstrate that under different external system parameters, the present invention can adaptively adjust the compensation amount, thereby preventing inductor current reverse flow and reducing the efficiency degradation under light load mode caused by the conduction power consumption of the parasitic body diode.

[0067] In summary, this invention utilizes the voltage change at the non-inverting terminal of the zero-crossing comparator module caused by comparator delay, and monitors the comparator delay in real time cycle by cycle to adjust the compensation current, thereby ensuring the accuracy of the zero-crossing point. Furthermore, it introduces system parameters VIN and VOUT, which can adaptively adjust the compensation current under changes in system parameters. Regardless of how the DC output voltage changes, it can provide the optimal compensation effect, reduce system power consumption, and improve system conversion efficiency in different application scenarios.

Claims

1. A cycle-by-cycle delay-compensated zero-crossing detection circuit, characterized in that: The output of the first current generation module is connected to both the sampling capacitor C1 and the compensation resistor Rc. The other end of the sampling capacitor C1 is grounded. The other end of the compensation resistor Rc is connected to the first input of the first sampling module, the output of the compensation calculation module, and the inverting input of the zero-crossing comparison module. The output of the first sampling module is connected to the first input of the compensation calculation module. The output of the second current generation module is connected to the sampling capacitor C2, the first input of the second sampling module, and the in-phase input of the zero-crossing comparison module. The output of the second sampling module is connected to the third input of the compensation calculation module. The other end of the sampling capacitor C2 is grounded. The second input terminal of the compensation calculation module is connected to the S1 signal; The first current generating module has three input terminals connected to inputs VIN, T, and T, respectively. ON The signal, the Clear signal, and the four input terminals of the second current generation module are respectively connected to input VIN, output VOUT, and T. OFF The signal and the clear signal are connected to the sample signal at the second input terminal of the first sampling module and the sample signal at the second input terminal of the second sampling module. The compensation calculation module has the following internal structure: it includes mirror transistors Mp1, Mn1, Mn2, a switching transistor Mn3, and Mn4. The drain of mirror transistor Mp1 is connected to the drain of mirror transistor Mn1, the drain and gate of mirror transistor Mn2, and the source of switching transistor Mn3. The drain of switching transistor Mn3 is connected to the sampling capacitor Cc and the gate of mirror transistor Mn4. The drain of mirror transistor Mn4 is connected to the other end of the compensation resistor Rc and the inverting input of the zero-crossing comparator module. The sources of mirror transistors Mn1, Mn2, and Mn4 are all grounded. The mirror ratio of the mirror tube Mn2 to the mirror tube Mn4 is 1:N; The inverting input of the zero-crossing comparator module is connected to the other end of the compensation resistor Rc, the input of the first sampling module, and the drain of the mirror transistor Mn4; the inverting input of the zero-crossing comparator module is connected to the sampling capacitor C2 and the output of the second current generation module; and the output of the zero-crossing comparator module is connected to the input of the logic module.

2. The cycle-by-cycle delay compensation zero-crossing detection circuit according to claim 1, characterized in that: The structure of the logic module includes delay module one, delay module two, and eight inverters, namely, first inverter INV1, second inverter INV2, third inverter INV3, fourth inverter INV4, fifth inverter INV5, sixth inverter INV6, seventh inverter INV7, and eighth inverter INV8. The input of the second inverter INV2 is connected to the output of the zero-crossing comparator module. The output of the second inverter INV2 is also connected to the input of the third inverter INV3 and the input of the first delay module. The output of the first delay module is connected to the input of the first inverter INV1. The delayed signal of the zero-crossing detection signal output by the first inverter INV1 serves as the first input of the first NAND gate NAND1. The output of the third inverter INV3 is connected to the second input of the first NAND gate NAND1 and the input of the fourth inverter INV4. The input of the fifth inverter INV5 receives the on / off state signal Ton from the power switch MOSFET M1; the output of the fourth inverter INV4 is connected to the first input of the second NAND gate NAND2; the output of the fifth inverter INV5 is simultaneously connected to the second input of the third NAND gate NAND3 and the second input of the first AND gate AND1; the output of the third NAND gate NAND3 is connected to the second input of the second NAND gate NAND2; the output of the second NAND gate NAND2 is simultaneously connected to the first input of the third NAND gate NAND3 and the first input of the first AND gate AND1. The input of delay module 2 accepts the start and end times of each cycle; the output of delay module 2 is connected to the input of the sixth inverter INV6; the output of the sixth inverter INV6 is connected to the input of the seventh inverter INV7; the output of the seventh inverter INV7 is simultaneously connected to the input of the eighth inverter INV8 and the first input of the first NOR gate NOR1; the first input of the second AND gate AND2 and the second input of the first NOR gate NOR1 simultaneously accept the start and end times of each cycle.

3. The cycle-by-cycle delay compensation zero-crossing detection circuit according to claim 1, characterized in that: It also includes a DC-DC power stage circuit. The structure of the DC-DC power stage circuit includes a power switching MOSFET M1, a power switching MOSFET M2, an inductor L0, and a load capacitor C0. The gate of the power switching MOSFET M2 is connected to the output terminal of the driver module. OFF The signal is connected to the input terminal of the drive module 1. The drain of the power switch MOSFET M2 is grounded through the load capacitor C0. The source of the power switch MOSFET M2, the drain of the power switch MOSFET M1, and the inductor L0 are all connected to the internal port SW. 0的 The other end is connected to the VIN voltage; the gate of the power switch MOSFET M1 is connected to the output terminal of the second drive module, the Ton signal is connected to the input terminal of the second drive module, and the source of the power switch MOSFET M1 is grounded.

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