A voltage stabilizer and a control method, device and equipment thereof

Abstract

The application discloses a voltage stabilizer and a control method, device and equipment thereof, and relates to the technical field of electronic circuits.The voltage stabilizer comprises an operational amplifier, a voltage stabilizing output circuit and a mode switching control circuit.The mode switching control circuit is used for controlling the voltage stabilizing output circuit to adjust the working mode of the voltage stabilizer.The working mode comprises a first working mode when the power supply voltage is a first voltage and a second working mode when the power supply voltage is a second voltage.The voltage stabilizing output circuit is used for converting the first voltage into the second voltage under the action of the operational amplifier when the working mode is the first working mode, and outputting the second voltage when the working mode is the second working mode.The first voltage is greater than the second voltage.The application can realize the switching of the working mode of the LDO under different power supply voltages, can make the LDO output stable voltage under two power supply voltages, and improves the applicability of the LDO in different application scenarios.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a voltage regulator and its control method, apparatus and equipment. Background Technology

[0002] Voltage regulators are common power management chips. Low dropout regulators (LDOs) are widely used in portable and communication devices due to their low quiescent power consumption, low cost, and no output ripple. The traditional output voltage expression for an LDO can be given as follows:

[0003] ;

[0004] From the above expression for the output voltage of a traditional LDO, it can be seen that the output voltage (V) OUT The feedback resistor ratio (R2 / R3) and the reference voltage (V) are used to determine the feedback resistance ratio (R2 / R3) and the reference voltage (V). ref The decision is based on the leakage voltage (V), a key parameter of the LDO, although it may seem unrelated to the power supply voltage. drop The minimum value of the power supply voltage (VDD) is limited. When an LDO is operating normally, the MOSFET works in the linear region, equivalent to a linear resistor, which inevitably generates a voltage drop across its source and drain. The drain voltage refers to the minimum value of this voltage drop that ensures the LDO operates normally under full load conditions. Therefore, the input voltage range of an LDO is specified, thus limiting its application environment. Figure 1 As shown, a power supply voltage greater than 2.4V is required to ensure that the LDO can output a stable voltage of 1.8V. Therefore, how to enable the LDO to output a stable voltage under different power supply voltages and improve the applicability of the LDO in different application scenarios is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a voltage regulator and its control method, apparatus and equipment, so that the LDO can output a stable voltage under different power supply voltages, thereby improving the applicability of the LDO in different application scenarios.

[0006] To solve the above-mentioned technical problems, the present invention provides a voltage regulator, comprising: an operational amplifier, a regulated output circuit, and a mode switching control circuit; wherein, the non-inverting input terminal and the output terminal of the operational amplifier are connected to the regulated output circuit;

[0007] The mode switching control circuit is used to control the voltage regulator output circuit to adjust and switch the operating mode of the voltage regulator; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage;

[0008] The voltage regulator output circuit is used to convert the first voltage into a second voltage output under the action of the operational amplifier when the operating mode is the first operating mode; and to output the second voltage when the operating mode is the second operating mode; wherein the first voltage is greater than the second voltage.

[0009] On the other hand, the mode switching control circuit includes a level converter, a logic gate, and a control output terminal; wherein the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal.

[0010] On the other hand, the voltage-regulated output circuit includes: a drive output circuit and a pull-down control circuit; wherein, the input terminal of the drive output circuit is connected to the power input terminal, and the ground terminal of the drive output circuit is grounded; the output terminal of the drive output circuit serves as a voltage-regulated output terminal; the voltage-regulated control terminal of the drive output circuit is connected to the output terminal of the operational amplifier and the first terminal of the pull-down control circuit, respectively, and the second terminal of the pull-down control circuit is grounded; the operating mode control terminal of the drive output circuit and the control terminal of the pull-down control circuit are respectively connected to the mode switching control circuit.

[0011] The drive output circuit, under the control of the mode switching control circuit, when the operating mode is the first operating mode, respectively connects the output terminal of the drive output circuit to the input terminal and the ground terminal, converts the first voltage input to the power input terminal into the second voltage under the action of the operational amplifier, and outputs the second voltage through the regulated output terminal; when the operating mode is the second operating mode, under the action of the pull-down control circuit, connects the output terminal of the drive output circuit to the input terminal, and outputs the second voltage input to the power input terminal through the regulated output terminal.

[0012] On the other hand, the operating mode also includes a third operating mode when the power input terminal receives a second voltage; wherein, in the third operating mode, the voltage regulator supports the connection of an external sink voltage to the regulated output terminal, the external sink voltage being less than or equal to the second voltage.

[0013] On the other hand, the drive output circuit includes: a first resistor, a second resistor, a first switching unit, a second switching unit, and a first PMOS transistor;

[0014] Wherein, the first terminal of the first switching unit is connected to the power input terminal, and the second terminal of the first switching unit is connected to the source of the first PMOS transistor; the drain of the first PMOS transistor is connected to the first terminal of the second switching unit, and the common terminal of the connection serves as the regulated output terminal; the second terminal of the second switching unit is connected to the first terminal of the first resistor; the second terminal of the first resistor is connected to the first terminal of the second resistor, and the common terminal of the connection is connected to the non-inverting input terminal of the operational amplifier; the second terminal of the second resistor is grounded; the gate of the first PMOS transistor serves as the regulated control terminal and is connected to the first terminal of the pull-down control circuit, and the common terminal of the connection is connected to the output terminal of the operational amplifier;

[0015] The drive output circuit, under the control of the mode switching control circuit, when the operating mode is the first operating mode, turns on the first switching unit and the second switching unit, and under the action of the operational amplifier, converts the first voltage input to the power input terminal into the second voltage, and outputs the second voltage through the drain of the first PMOS; when the operating mode is the second operating mode, it turns on the first switching unit and turns off the second switching unit, and under the action of the pull-down control circuit, turns on the first PMOS and outputs the second voltage input to the power input terminal through the drain of the first PMOS.

[0016] On the other hand, the pull-down control circuit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor;

[0017] In this circuit, the drain of the first NMOS transistor serves as the first terminal of the pull-down control circuit and is connected to the voltage regulation control terminal of the drive output circuit; the common terminal of this connection is connected to the output terminal of the operational amplifier. The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor, and the common terminal of this connection is connected to the gate of the first NMOS transistor and the drain of the third NMOS transistor, respectively. The common terminal connecting the drain of the second NMOS transistor and the gate of the second NMOS transistor is used to connect to the positive terminal of a current source, and the negative terminal of the current source is used to connect to the power input terminal. The sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected, and the common terminal of this connection serves as the second terminal of the pull-down control circuit and is grounded. The control output terminal of the mode switching control circuit includes a first control output terminal.

[0018] The gate of the third NMOS transistor is connected to the first control output terminal. When the operating mode is the second operating mode, the third NMOS transistor is turned off to turn on the first NMOS transistor and the second NMOS transistor to slowly pull down the voltage input to the voltage regulation control terminal of the drive output circuit to 0; when the operating mode is the first operating mode, the third NMOS transistor is turned on to turn off the first NMOS transistor and the second NMOS transistor.

[0019] On the other hand, the pull-down control circuit also includes:

[0020] An isolation circuit is provided between the voltage regulation control terminal of the drive output circuit and the drain of the first NMOS transistor. When the operating mode is the first operating mode, the voltage output from the output terminal of the operational amplifier is isolated and converted into a preset voltage and output to the drain of the first NMOS transistor; wherein the preset voltage is less than or equal to the second voltage.

[0021] On the other hand, the isolation circuit includes: a third resistor, a fourth resistor, and a fourth NMOS transistor;

[0022] In this circuit, the drain of the fourth NMOS transistor serves as the first terminal of the pull-down control circuit and is connected to the voltage regulation control terminal of the drive output circuit; the common terminal of this connection is connected to the output terminal of the operational amplifier. The source of the fourth NMOS transistor is connected to the drain of the first NMOS transistor. The first terminal of the third resistor is connected to the power input terminal. The second terminal of the third resistor is connected to the first terminal of the fourth resistor, and the common terminal of this connection is connected to the gate of the fourth NMOS transistor. The second terminal of the fourth resistor is grounded.

[0023] On the other hand, the first switching unit includes a second PMOS transistor, the second switching unit includes a third PMOS transistor, and the control output terminal of the mode switching control circuit includes a first control output terminal, a second control output terminal, and a third control output terminal; wherein, the source of the second PMOS transistor is connected to the power input terminal, the drain of the second PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the second PMOS transistor serves as the control terminal of the first switching unit and is connected to the second control output terminal; the source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the third PMOS transistor is connected to the first end of the first resistor, and the gate of the third PMOS transistor serves as the control terminal of the second switching unit and is connected to the third control output terminal;

[0024] The first control output terminal, the second control output terminal, and the third control output terminal are all used to control the conduction or cutoff of their respective connected MOS transistors by outputting a first control level and / or a second control level.

[0025] The present invention also provides a control method for a voltage regulator, applied to the voltage regulator as described above, comprising:

[0026] Obtain the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator's regulated output circuit; the power supply voltage includes a first voltage and a second voltage;

[0027] The operating mode of the voltage regulator is determined based on the power supply voltage configuration information; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage;

[0028] The voltage regulator's mode switching control circuit controls the voltage regulator output circuit to switch the voltage regulator to the operating mode.

[0029] The present invention also provides a control device for a voltage regulator, applied to the voltage regulator as described above, comprising:

[0030] The acquisition module is used to acquire the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage;

[0031] The determining module is used to determine the operating mode of the voltage regulator based on the power supply voltage configuration information; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage;

[0032] The control module is used to control the regulated output circuit through the mode switching control circuit of the voltage regulator to adjust the voltage regulator to switch to the working mode.

[0033] Furthermore, the present invention also provides a control device for a voltage regulator, comprising:

[0034] Memory, used to store computer programs;

[0035] A processor is used to implement the steps of the control method for the voltage regulator as described above when executing the computer program.

[0036] The present invention provides a voltage regulator comprising: an operational amplifier, a regulated output circuit, and a mode switching control circuit; wherein the non-inverting input and output terminals of the operational amplifier are connected to the regulated output circuit; the mode switching control circuit is used to control the regulated output circuit to adjust and switch the operating mode of the voltage regulator; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; the regulated output circuit is used to convert the first voltage to a second voltage output under the action of the operational amplifier when the operating mode is the first operating mode; and to output the second voltage when the operating mode is the second operating mode; wherein the first voltage is greater than the second voltage;

[0037] As can be seen, by configuring the mode switching control circuit and the voltage regulation output circuit, this invention enables the LDO to switch its operating mode under different power supply voltages, allowing the LDO to output a stable voltage under both power supply voltages. This achieves a power supply-switching LDO under advanced processes, improving the LDO's applicability in various application scenarios. Furthermore, this invention also provides a control method, device, and equipment for a voltage regulator, which also possesses the aforementioned beneficial effects. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating the relationship between the input and output voltages of a traditional LDO.

[0040] Figure 2 This is a structural block diagram of a voltage regulator provided in an embodiment of the present invention;

[0041] Figure 3 This is a partial circuit diagram of another voltage regulator provided in an embodiment of the present invention;

[0042] Figure 4 A flowchart illustrating a control method for a voltage regulator provided in an embodiment of the present invention;

[0043] Figure 5 This is a structural block diagram of a control device for a voltage regulator provided in an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the structure of a control device for a voltage regulator provided in an embodiment of the present invention;

[0045] Figure 7This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Please refer to Figure 2 , Figure 2 This is a structural block diagram of a voltage regulator provided in an embodiment of the present invention. The voltage regulator may include: an operational amplifier 10, a regulated output circuit 20, and a mode switching control circuit 30; wherein, the non-inverting input terminal and the output terminal of the operational amplifier 10 are connected to the regulated output circuit 20, and the inverting input terminal of the operational amplifier 10 is connected to a reference voltage (Vref).

[0048] The mode switching control circuit 30 is used to control the voltage regulator output circuit 20 to adjust the operating mode of the voltage regulator; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage.

[0049] The voltage regulator output circuit 20 is used to convert the first voltage into a second voltage output under the action of the operational amplifier 10 when the operating mode is the first operating mode; and to output the second voltage when the operating mode is the second operating mode; wherein the first voltage is greater than the second voltage.

[0050] It is understood that the voltage regulator output circuit 20 in this embodiment can switch the operating mode of the LDO according to the control of the mode switching control circuit 30, so that when the power supply voltage connected to the power input terminal of the voltage regulator output circuit 20 is a first voltage or a second voltage, the voltage regulator output terminal of the voltage regulator output circuit 20 can output a stable second voltage in both the first and second operating modes of the LDO, ensuring that the LDO can output a stable voltage in both the first and second voltage conditions. For example, when the operating mode is the first operating mode, the voltage regulator output circuit 20 is used to convert the first voltage input to the power input terminal into a second voltage under the feedback control of the operational amplifier 10, and output the second voltage through the voltage regulator output terminal; when the operating mode is the second operating mode, the voltage regulator output terminal outputs the second voltage input to the power input terminal; wherein, in this embodiment, the first voltage can be greater than the second voltage and less than or equal to twice the second voltage, such as the first voltage can be 3.3V and the second voltage can be 1.8V.

[0051] Correspondingly, the specific structure of the mode switching control circuit 30 in this embodiment can be set by the designer according to the practical scenario and user requirements. The mode switching control circuit 30 includes a level converter, a logic gate, and a control output terminal; wherein, the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal. The specific logic gate circuit can be set according to the practical scenario and user requirements, as long as it can cooperate with the level converter to output a control output signal at the control output terminal that can control the voltage regulator output circuit 20 to switch working modes.

[0052] Correspondingly, the specific circuit structure of the voltage regulator output circuit 20 in this embodiment can also be set by the designer according to the practical scenario. For example, the voltage regulator output circuit 20 may include different drive output circuits for outputting different voltages, or a single drive output circuit may be selected to output different voltages. For example, the voltage regulator output circuit 20 may include: a drive output circuit and a pull-down control circuit; wherein, the input terminal of the drive output circuit is connected to the power input terminal, and the ground terminal of the drive output circuit is grounded; the output terminal of the drive output circuit serves as the voltage regulator output terminal; the voltage regulation control terminal of the drive output circuit is connected to the output terminal of the operational amplifier 10 and the first terminal of the pull-down control circuit, respectively, and the second terminal of the pull-down control circuit... The drive output circuit is grounded; the operating mode control terminal and the control terminal of the pull-down control circuit are respectively connected to the mode switching control circuit 30. The drive output circuit, according to the control of the mode switching control circuit 30, in the first operating mode, respectively connects the output terminal to the input terminal and the ground terminal, converting the first voltage input to the power input terminal into a second voltage under the action of the operational amplifier 10, and outputting the second voltage through the regulated output terminal. In the second operating mode, under the action of the pull-down control circuit, the output terminal of the drive output circuit is connected to the input terminal, and the second voltage input to the power input terminal is output through the regulated output terminal. Correspondingly, in the first or third operating mode, the pull-down control circuit can disconnect the connection between the first and second terminals according to the control of the mode switching control circuit 30; in the third operating mode, the drive output circuit can disconnect the output terminal from the input terminal and the ground terminal according to the control of the mode switching control circuit 30.

[0053] It should be noted that the operating mode of the LDO in this embodiment can include not only the first operating mode when the power input terminal is connected to the first voltage and the second operating mode when the power input terminal is connected to the second voltage, but also a third operating mode when the power input terminal is connected to the second voltage, so that the LDO can support the connection of an external sink voltage to the regulated output terminal in the third operating mode. The external sink voltage is less than or equal to the second voltage, such as the external sink voltage being the second voltage.

[0054] In other words, in this embodiment, by setting the drive output circuit and the pull-down control circuit, when the working mode is the first working mode, the connection between the output terminal of the drive output circuit and the input terminal and the ground terminal is turned on, so that the drive output circuit can convert the first voltage input at the power input terminal into a second voltage and output it through the regulated output terminal under the feedback control of the operational amplifier 10; when the working mode is the second working mode, the connection between the output terminal of the drive output circuit and the ground terminal is turned off, and the output of the operational amplifier 10 is pulled down to 0 under the action of the pull-down control circuit to avoid the feedback control of the operational amplifier 10, and the second voltage input at the power input terminal is output through the regulated output terminal by turning on the connection between the input terminal and the output terminal of the drive output circuit; that is, when the working mode is the second working mode, part of the drive output circuit is used to output the second voltage input at the power input terminal through the regulated output terminal.

[0055] Correspondingly, in some other embodiments, when the operating mode is the second operating mode, the second voltage can be output through an additional circuit (i.e., a direct output circuit) instead of using a partial drive output circuit. For example, the regulated output circuit 20 may include: a drive output circuit and a direct output circuit; wherein, the input terminal of the drive output circuit is connected to the input terminal of the direct output circuit, and the common terminal of the connection is connected to the power input terminal; the output terminal of the drive output circuit is connected to the output terminal of the direct output circuit, and the common terminal of the connection serves as the regulated output terminal; the control terminals of the drive output circuit and the direct output circuit are respectively connected to the mode switching control circuit 30; the drive output circuit is used to conduct when the operating mode is the first operating mode according to the control of the mode switching control circuit 30, and converts the first voltage input to the power input terminal into a second voltage using the feedback control of the operational amplifier 10, and outputs the second voltage through the regulated output terminal; the direct output circuit is used to conduct when the operating mode is the second operating mode according to the control of the mode switching control circuit 30, so as to connect the connection between the input terminal and the output terminal of the direct output circuit, and output the second voltage input to the power input terminal through the regulated output terminal.

[0056] In other words, in some embodiments, by configuring the drive output circuit and the direct output circuit, the drive output circuit is turned on and the direct output circuit is turned off when the operating mode is the first operating mode, so that the drive output circuit can use the feedback control of the operational amplifier 10 to convert the first voltage input at the power input terminal into a second voltage and output it through the regulated output terminal; when the operating mode is the second operating mode, the drive output circuit is turned off and the direct output circuit is turned on, so that the direct output circuit can directly output the second voltage input at the power input terminal through the regulated output terminal; when the operating mode is the third operating mode, the drive output circuit and the direct output circuit are turned off to avoid the influence of the external sink voltage connected to the regulated output terminal on the circuit components in the LDO.

[0057] This embodiment does not limit the specific circuit structure of the drive output circuit. It may include a first PMOS transistor, a first resistor, and a second resistor for converting the first voltage to the second voltage through feedback control of the operational amplifier 10. It may also include a switching unit (i.e., a first switching unit and a second switching unit) connected to the source and drain of the first PMOS transistor, respectively, to switch the on / off state of the drive output circuit according to the control of the mode switching control circuit 30. It should be noted that this embodiment does not limit the number of the first switching unit and the second switching unit, as long as they can effectively turn the drive output circuit and the direct output circuit on or off.

[0058] For example, such as Figure 3As shown, the drive output circuit may include: a first resistor (R1), a second resistor (R2), a first switching unit (M1), a second switching unit (M4), and a first PMOS transistor (PM1); wherein, the first terminal of the first switching unit is connected to the power input terminal (VDD3318), and the second terminal of the first switching unit is connected to the source of the first PMOS transistor; the drain of the first PMOS transistor is connected to the first terminal of the second switching unit, and the common terminal of the connection serves as the regulated output terminal (LDOOUT18); the second terminal of the second switching unit is connected to the first terminal of the first resistor; the second terminal of the first resistor is connected to the first terminal of the second resistor, and the common terminal of the connection is connected to the non-inverting input terminal (VF terminal) of the operational amplifier 10; the second terminal of the second resistor is grounded; and the gate of the first PMOS transistor serves as the regulated control terminal. The first terminal of the pull-down control circuit is connected to the common terminal of the operational amplifier 10 (OP_OUT terminal); the drive output circuit, according to the control of the mode switching control circuit 30, when the working mode is the first working mode, turns on the first switch unit and the second switch unit, and under the action of the operational amplifier, converts the first voltage input to the power input terminal into the second voltage, and outputs the second voltage through the drain of the first PMOS; when the working mode is the second working mode, the first switch unit is turned on and the second switch unit is turned off, and under the action of the pull-down control circuit, the first PMOS is turned on and outputs the second voltage input to the power input terminal through the drain of the first PMOS.

[0059] In other words, the control terminals of the first and second switching units are respectively connected to the mode switching control circuit as working mode control terminals. They are used to turn on the first switching unit when the working mode is either the first or second working mode; and to turn on the second switching unit when the working mode is the first working mode. It should be noted that when the working mode is the second working mode, the pull-down control circuit turns on the first PMOS transistor according to the control of the mode switching control circuit, thereby allowing the 1.8V voltage at the power input terminal to be output through the drain of the first PMOS transistor after passing through the first switching unit. Therefore, this embodiment does not limit the specific structure of the pull-down control circuit, as long as it can be implemented... The first PMOS transistor is turned on when the operating mode is the first operating mode, and it has no effect on the gate voltage of the first PMOS transistor in other operating modes. For the pull-down control circuit, for example, it can be selected to connect the connection between the first and second terminals of the pull-down control circuit when the operating mode is the second operating mode, thereby pulling down the gate voltage of the first PMOS transistor to 0, according to the corresponding control of the mode switching control circuit. Alternatively, it can be selected to pull down the gate voltage of the first PMOS transistor to a voltage threshold suitable for the first PMOS transistor to turn on, and there are no restrictions on the specific design structure between the first and second terminals of the pull-down control circuit.

[0060] In other words, in the first operating mode, the operational amplifier 10 (such as error amplifier EA) can amplify and output the difference between the feedback voltage (i.e. the voltage between the first resistor and the second resistor) connected to the non-inverting input terminal and the reference voltage connected to the inverting input terminal to the gate of the first PMOS transistor, thereby realizing feedback control of the operational amplifier 10 and enabling the first voltage input to the power supply input terminal to be converted into the second voltage output from the regulated output terminal.

[0061] Similarly, this embodiment does not limit the specific circuit structure of the pull-down control circuit described above. For example, the pull-down control circuit may only include a third switching unit (such as a MOSFET) directly controlled by the mode switching control circuit 30 to correspondingly turn on or off the connection between the gate of the first PMOS transistor and ground. Since in the second operating mode, if the gate voltage of the first PMOS transistor suddenly becomes 0, the first PMOS transistor will be fully turned on instantly, generating a large current and posing a risk of large current overshoot, the pull-down control circuit may also include a current mirror for limiting the current flowing into ground from the output of the operational amplifier 10 in the second operating mode, so that the voltage input to the gate of the first PMOS transistor is slowly pulled down to 0, and the current mirror is used to alleviate the large current overshoot; and other switching units for correspondingly controlling the turn-on and turn-off of the current mirror according to the control of the mode switching control circuit 30.

[0062] like Figure 3As shown, the pull-down control circuit mentioned above may include a first NMOS transistor (NM1), a second NMOS transistor (NM2), and a third NMOS transistor (NM3). That is, the mode switching control circuit 30 can control the conduction or cutoff of the current mirror composed of the first NMOS transistor and the second NMOS transistor by controlling the conduction or cutoff of the third NMOS transistor, so as to realize the on / off control of the connection between the power input terminal and the regulated output terminal. In this circuit, the drain of the first NMOS transistor serves as the first terminal of the pull-down control circuit and is connected to the voltage regulation control terminal of the drive output circuit. The common terminal of this connection is connected to the output terminal of the operational amplifier 10. The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor, and the common terminal of this connection is connected to the gate of the first NMOS transistor and the drain of the third NMOS transistor, respectively. The common terminal connecting the drain and gate of the second NMOS transistor is used to connect to the positive terminal of the current source, and the negative terminal of the current source is used to connect to the power input terminal. The sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected, and the common terminal of this connection serves as the second terminal of the pull-down control circuit and is grounded. The control output terminal of the mode switching control circuit includes a first control output terminal (bypass_enb terminal).

[0063] The gate of the third NMOS transistor is connected to the first control output terminal of the mode switching control circuit 30; it is used to turn off the third NMOS transistor when the working mode is the second working mode, so as to turn on the first NMOS transistor and the second NMOS transistor to slowly pull down the voltage input to the voltage regulation control terminal of the drive output circuit to 0; and to turn on the third NMOS transistor when the working mode is the first working mode, so as to turn off the first NMOS transistor and the second NMOS transistor.

[0064] In other words, when the operating mode is the second operating mode, the mode switching control circuit 30 turns off the third NMOS transistor and turns on the first and second NMOS transistors, so that the current flowing through the first NMOS transistor can correspond to the current flowing through the second NMOS transistor (i.e., the output current of the current source). This allows the voltage input to the voltage regulation control terminal (such as the gate of the first PMOS transistor) of the drive output circuit to be slowly (e.g., at a constant speed) pulled down to 0, avoiding the risk of a large current overshoot caused by its sudden change to 0. When the operating mode is the first operating mode, the first, second, and third NMOS transistors are turned off to prevent the external voltage from leaking to ground through the conducting MOS transistors.

[0065] Furthermore, to avoid voltage withstand issues with the first NMOS transistor when operating in the first mode, the pull-down control circuit may further include an isolation circuit between the voltage regulation control terminal of the drive output circuit and the drain of the first NMOS transistor. This isolation circuit isolates the voltage output from the operational amplifier 10 and converts it into a preset voltage for output to the drain of the first NMOS transistor when operating in the first mode. The preset voltage is less than or equal to a second voltage, such as the second voltage. In other words, by using the isolation circuit in this embodiment, the drain of the first NMOS transistor can be prevented from being directly connected to the output of the operational amplifier 10 when operating in the first mode, allowing the first NMOS transistor to use a lower voltage withstand value (such as the second voltage) without overvoltage risk.

[0066] like Figure 3 As shown, the isolation circuit may include a third resistor (R3), a fourth resistor (R4), and a fourth NMOS transistor (NM4). The drain of the fourth NMOS transistor serves as the first terminal of the pull-down control circuit, connected to the voltage regulation control terminal of the drive output circuit. The common terminal of this connection is connected to the output terminal of the operational amplifier 10. The source of the fourth NMOS transistor is connected to the drain of the first NMOS transistor. The first terminal of the third resistor is connected to the power input terminal. The second terminal of the third resistor is connected to the first terminal of the fourth resistor, and the common terminal of this connection is connected to the gate of the fourth NMOS transistor. The second terminal of the fourth resistor is grounded. In other words, by dividing the voltage between the third and fourth resistors, a suitable bias voltage can be obtained and applied to the gate of the fourth NMOS transistor, thereby reducing the voltage connected to the drain of the first NMOS transistor (i.e., the preset voltage) to a lower level.

[0067] It should be noted that the MOSFETs in the circuit provided in this embodiment can all be low-voltage devices. Low-voltage devices have lower withstand voltage values, and the withstand voltage values ​​of the MOSFETs in the circuit can all be less than or equal to the second voltage, and the first voltage can be less than or equal to twice the second voltage; for example Figure 3As shown, when the first voltage is 3.3V and the second voltage is 1.8V, the withstand voltage of the MOS transistors in the circuit can all be 1.8V (i.e., the second voltage). In the second operating mode, if there is no fourth NMOS transistor (NM4), the source-drain voltage of the first NMOS transistor (NM1) will exceed 1.8V (because the output of operational amplifier 10 will exceed 1.8V), causing NM1 to overvoltage. However, after setting NM4, the drain voltage of NM1 is equal to the gate voltage of NM4 minus one of NM4's VGS (the voltage between the gate and the source). The gate voltage of NM4 can be adjusted by adjusting the resistance values ​​of the third resistor (R3) and the fourth resistor (R4) to achieve different degrees of voltage division, thereby enabling appropriate biasing to reduce the drain voltage of NM1 to a lower level, so that the source-drain voltage of NM1 is not greater than 1.8V, avoiding the overvoltage of NM1.

[0068] Correspondingly, the mode switching control circuit 30 can control the conduction or cutoff of the connected MOS transistor by outputting the first control level and / or the second control level from each of its control output terminals; for example, if the first control level is greater than the second control level, then the first control level can be equal to the second voltage (e.g., 1.8V) or fluctuate slightly around the second voltage, the second control level can be equal to the third voltage (e.g., 0) or fluctuate slightly around the third voltage, and the third voltage is less than the second voltage.

[0069] For example, such as Figure 3As shown, the first switching unit includes a second PMOS transistor (PM2), the second switching unit includes a third PMOS transistor (PM3), and the control output terminals of the mode switching control circuit 30 include a first control output terminal, a second control output terminal, and a third control output terminal; wherein, the source of the second PMOS transistor is connected to the power input terminal, the drain of the second PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the second PMOS transistor serves as the control terminal of the first switching unit and is connected to the second control output terminal (hiz_enb terminal) of the mode switching control circuit 30; the source of the third PMOS transistor is connected to the drain of the first PMOS transistor. The drain of the third PMOS transistor is connected to the first end of the first resistor, and the gate of the third PMOS transistor is connected to the third control output terminal (bypass_en18 terminal) of the mode switching control circuit 30 as the control terminal of the second switching unit. The first control output terminal (bypass_enb terminal), the second control output terminal (hiz_enb terminal), and the third control output terminal (bypass_en18 terminal) of the mode switching control circuit 30 can all be used to control the conduction or cutoff of their respective connected MOS transistors (such as NM3, PM2, and PM3) by outputting a first control level or a second control level. As the manufacturing process becomes more and more advanced, the feature size of MOS transistors is reduced, the threshold voltage of the transistors is lowered, the circuit area and power consumption are reduced, the speed is faster, and the chip cost is reduced. This leads to a decrease in the withstand voltage of MOS transistors. In order to ensure that the MOS transistors are not at risk of overvoltage when the LDO voltage conversion circuit is powered by a higher first voltage, in this embodiment, the relatively higher level (i.e., the first control level) output by the mode switching control circuit 30 can be greater than or equal to half of the first voltage and less than the first voltage. For example, the first control level can be the second voltage.

[0070] Correspondingly, the specific structure of the mode switching control circuit 30 in this embodiment can be set by the designer according to the practical scenario and user needs. For example, when the first control level is the second voltage, such as... Figure 3As shown, the regulated output terminal (LDOOUT18 terminal) of the regulated output circuit 20 can be connected to the mode switching control circuit 30. The mode switching control circuit 30 is used to control the first control output terminal (bypass_enb terminal) and the second control output terminal (hiz_enb terminal) to output a first control level and control the third control output terminal (bypass_en18 terminal) to output a second control level when the operating mode is the first operating mode; when the operating mode is the second operating mode, it controls the first and second control output terminals to output the second control level and controls the third control output terminal to output the first control level; when the operating mode is the third operating mode, it controls the second and third control output terminals to output the first control level and controls the first control output terminal to output the second control level. This embodiment does not impose any limitations on the mode switching control circuit 30 as long as it can adjust the operating mode of the voltage regulator by outputting the first and second control levels.

[0071] For example, when the second voltage is 1.8V, such as Figure 3 As shown, the regulated output circuit 20 may include a first level shifter (Level shifter 1), a second level shifter (Level shifter 2), a NOR gate (G1), a first NOT gate (G3), a second NOT gate (G4), and a third NOT gate (G2).

[0072] The system comprises a first level converter and a second level converter, each receiving a 1.8V voltage input at their first input terminals and a fourth voltage at their second input terminals (DVDD09 terminals). The first level converter receives a first enable signal (hiz_en) at its control input terminal, used to control the output of either a first or second control level based on this signal. The second level converter receives a second enable signal (bypass_en) at its control input terminal, also used to control the output of either a first or second control level based on this signal. The output terminal of the first level converter is connected to the first input terminal of a NOR gate, the output terminal of the second level converter is connected to the input terminal of a first NOT gate, the output terminal of the first NOT gate is connected to both the input terminal of the second NOT gate and the second input terminal of the NOR gate, and the output terminal of the NOR gate is connected to the input terminal of a third NOT gate. The output terminal of the third NOT gate serves as the second control output terminal (hiz_enb terminal), the output terminal of the second NOT gate serves as the third control output terminal (bypass_en18 terminal), and the output terminal of the first NOT gate serves as the first control output terminal (bypass_enb terminal). The fourth voltage is less than the second voltage and greater than the third voltage.

[0073] Correspondingly, the voltage-regulated output circuit 20 provided in this embodiment may also include the aforementioned current source.

[0074] Correspondingly, the processor can control the output of the first enable signal and the second enable signal, and through the mode switching control circuit 30, control the MOSFET in the voltage regulator output circuit 20 to adjust the regulator to the desired operating mode. For example, when the operating mode is the first operating mode, both the first enable signal and the second enable signal are 0, and both the first level converter and the second level converter output the second control level. When the operating mode is the second operating mode, the first enable signal is 0 and the second enable signal is 1, the first level converter outputs the second control level and the second level converter outputs the first control level. When the operating mode is the third operating mode, both the first enable signal and the second enable signal are 1, and both the first level converter and the second level converter output the first control level.

[0075] It should be noted that the first input terminals of the first and second level converters receive a 1.8V voltage input, which can be derived from a 1.8V voltage source. If it is desired to reduce the number of power supply interfaces of the voltage regulator while obtaining a stable and continuous 1.8V voltage input, the first input terminals of the first and second level converters can be connected to the voltage regulator output terminal (LDOOUT18 terminal) of the voltage regulator output circuit 20 to obtain a stable 1.8V voltage input. Additionally, if... Figure 3 As shown, the first voltage can be 3.3V, the second voltage can be 1.8V, the third voltage can be 0V, and the fourth voltage can be 0.9V. The LOD can operate in three modes: 3.3V LOD mode (i.e., the first operating mode), 1.8V bypass mode (i.e., the second operating mode), and high-impedance mode (i.e., the third operating mode). The withstand voltage problem occurs in the 3.3V LDO mode. The high-voltage power supply of the first level shifter (Level shifter1) and the second level shifter (Level shifter2) both use the output voltage of the LDO (LDOOUT18). In this structure, the 3.3V LDO mode and the 1.8V bypass mode share PM1. Figure 3 The circuitry for operational amplifier 10 is omitted. In 3.3 V LDO mode, the load is driven by the PM1 branch; while the PM3 branch drives the load in 1.8 V bypass mode.

[0076] Correspondingly, when the LDO operates in 3.3V LDO mode, the input voltage of VDD3318 (i.e., the power input terminal) is 3.3V (i.e., the first voltage). Both hiz_en and bypass_en are set to 0 by the register, making hiz_enb high (1.8V), M1 conducts, bypass_en18 low (0V), PM3 conducts, and PM1 performs normal voltage regulation through the LDO loop. At the same time, bypass_enb is high, NM3 conducts, turning off the current mirrors NM1 and NM2. Since the gate voltage of PM2 is 1.8V, there is no risk of overvoltage. NM4 is used to solve the voltage withstand problem of NM1. Without NM4, the source-drain voltage of NM1 in this mode would be greater than 1.8V. The drain voltage of NM1 is equal to the gate voltage of NM4 minus VGS (the voltage of the gate relative to the source). The gate of NM4 is appropriately biased through the voltage division of the resistor to achieve different degrees of conduction, thereby reducing the drain voltage of NM1 to a lower level and avoiding damage to NM1.

[0077] When the LDO operates in 1.8V bypass mode, VDD3318 is 1.8V, hiz_en is set to 0, and bypass_en is set to 1. At this time, the hiz_enb signal is 0, PM2 is turned on; when bypass_enb is 0, NM3 is turned off, the current mirror composed of NM1 and NM2 is working, pulling the gate of PM1 down to 0, bypass_en18 is high, the LDO loop is turned off, and the load is powered directly by the drain of PM1 to the 1.8V power supply.

[0078] When the LDO operates in high-impedance mode, configuration is only allowed when the input voltage at the power supply terminal is 1.8V, supporting external 1.8V output. With `hiz_en` and `bypass_en` both set to 1, the `hiz_enb` signal is 1.8V, PM2 is off, and `bypass_en18` is high. The path from the feedback resistor to ground is also shut off, ensuring no leakage when the output voltage is externally supplied with 1.8V. Figure 3The circuit setup shown implements a switchable power supply LDO using advanced technology (i.e., low-voltage devices), compatible with both 1.8V and 3.3V power supplies, providing a stable 1.8V output. Even without a 3.3V power supply, it can still output a stable 1.8V using a 1.8V power supply and supports external voltage injection. When the LDO load has a large capacitor, a current mirror pull-down significantly mitigates high-current overshoot. To prevent overvoltage of the bypass MOSFET under 3.3V conditions, a current source is added to follow the high voltage. Furthermore, the slower pull-down speed of the bypass MOSFET NM1 reduces the large current generated during mode switching (e.g., switching from 3.3V LDO mode to 1.8V bypass mode). In both 3.3V LDO mode and high-impedance mode, the gate voltage of PM2 is 1.8V. With a constant gate voltage, PM2 can achieve two different operating states, enabling switching between the first and third operating modes, thus switching the circuit function.

[0079] In this embodiment, the present invention enables the LDO to switch its operating mode under different input voltage conditions by setting up the mode switching control circuit 30 and the voltage regulation output circuit 20. This allows the LDO to output a stable voltage under both input voltage conditions, realizing a power-switchable LDO under advanced technology and improving the applicability of the LDO in different application scenarios.

[0080] Corresponding to the voltage regulator embodiment above, this invention also provides a voltage regulator control method. The voltage regulator control method described below can be referred to in correspondence with the voltage regulator described above.

[0081] Please refer to Figure 4 , Figure 4 This is a flowchart illustrating a control method for a voltage regulator provided in an embodiment of the present invention. The method, applied to the voltage regulator provided in the above embodiment, may include:

[0082] Step 101: Obtain the power supply voltage configuration (i.e. power supply configuration information) of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage.

[0083] It is understood that the power supply voltage configuration information of the regulator in this embodiment may include the configuration information of the LDO power supply voltage in the above embodiment, such as the power supply voltage at the power input terminal in the LDO's regulated output circuit. That is, the processor can detect whether the power supply voltage at the power input terminal in the LDO's regulated output circuit is a first voltage (e.g., 3.3V) or a second voltage (e.g., 1.8V), and thus determine the LDO's operating mode accordingly.

[0084] Step 102: Determine the operating mode of the voltage regulator based on the power supply voltage configuration information; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage.

[0085] It should be noted that in this step, the processor can determine the LDO's operating mode based on the acquired LDO power supply voltage configuration information. For example, the processor can determine the LDO's operating mode as the first operating mode when the power supply voltage at the power input terminal in the LDO's regulated output circuit is a first voltage; and as the second operating mode when the power supply voltage at the power input terminal in the LDO's regulated output circuit is a second voltage. The operating mode can also be a third operating mode with the power supply voltage being the second voltage, to support the LDO's access to an external voltage source. For example, when the power supply voltage at the power input terminal in the LDO's regulated output circuit is the second voltage, the processor can determine the LDO's operating mode as either the second or third operating mode based on user settings.

[0086] Step 103: Control the voltage regulator output circuit through the voltage regulator mode switching control circuit to switch the voltage regulator to working mode.

[0087] It is understood that in this embodiment, the processor can control the MOSFET in the voltage regulator output circuit through the LDO mode switching control circuit to adjust the LDO to a specific operating mode; such as Figure 3 As shown, the processor can configure the first enable signal (hiz_en) and the second enable signal (bypass_en) connected to the control input terminals of the first level shifter (Level shifter1) and the second level shifter (Level shifter2) in the mode switching control circuit through register configuration. This controls the level signals output by the first level shifter and the second level shifter, thereby adjusting the level signals output by the first control output terminal (bypass_enb terminal), the second control output terminal (hiz_enb terminal), and the third control output terminal (bypass_en18 terminal) of the mode switching control circuit. This, in turn, controls the on / off state of the corresponding MOSFET in the voltage regulator output circuit, switching the LDO to the corresponding operating mode.

[0088] In this embodiment, the present invention, through the setting of the LDO mode switching control circuit and the voltage regulation output circuit, can switch the LDO's operating mode according to the LDO's power supply voltage, so that the LDO can output a stable voltage under two power supply voltage conditions. This realizes a power supply switchable LDO under advanced technology and improves the applicability of the LDO in different application scenarios.

[0089] Corresponding to the above method embodiments, this invention also provides a control device for a voltage regulator. The control device for a voltage regulator described below and the control method for a voltage regulator described above can be referred to in correspondence.

[0090] Please refer to Figure 5 , Figure 5 This is a structural block diagram of a control device for a voltage regulator provided in an embodiment of the present invention. The device, applied to the voltage regulator provided in the above embodiment, may include:

[0091] The acquisition module 100 is used to acquire the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage;

[0092] The determining module 200 is used to determine the operating mode of the voltage regulator based on the power supply voltage configuration information; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage.

[0093] The control module 300 is used to control the regulated output circuit through the regulator's mode switching control circuit to switch the regulator to the working mode.

[0094] In this embodiment, the present invention, through the setting of the LDO mode switching control circuit and the voltage regulation output circuit, can switch the LDO's operating mode according to the LDO's power supply voltage, so that the LDO can output a stable voltage under two power supply voltage conditions. This realizes a power supply switchable LDO under advanced technology and improves the applicability of the LDO in different application scenarios.

[0095] Corresponding to the above method embodiments, this invention also provides a control device for a voltage regulator. The control device for a voltage regulator described below and the control method for a voltage regulator described above can be referred to in correspondence.

[0096] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a control device for a voltage regulator provided in an embodiment of the present invention. This device, applied to the voltage regulator provided in the above embodiment, may include:

[0097] Memory D1 is used to store computer programs;

[0098] The processor D2 is used to execute computer programs to implement the steps of the control method for the voltage regulator provided in the above method embodiments.

[0099] Corresponding to the above method embodiments, this invention also provides a computer-readable storage medium. The computer-readable storage medium described below and the control method for a voltage regulator described above can be referred to in correspondence.

[0100] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a computer-readable storage medium provided in an embodiment of the present invention. The computer-readable storage medium 40 stores a computer program 41, which, when executed by a processor, implements the steps of the voltage regulator control method provided in the above-described method embodiment.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods, apparatuses, and computer-readable storage media disclosed in the embodiments are described simply because they correspond to the voltage regulators disclosed in the embodiments; relevant details can be found in the voltage regulator section.

[0102] The voltage regulator and its control method and apparatus provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A voltage regulator, characterized in that, include: An operational amplifier, a regulated output circuit, and a mode switching control circuit are included; wherein the non-inverting input and output terminals of the operational amplifier are connected to the regulated output circuit. The mode switching control circuit is used to control the voltage regulator output circuit to adjust and switch the operating mode of the voltage regulator; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The voltage regulator output circuit is used to convert the first voltage into a second voltage output under the action of the operational amplifier when the operating mode is the first operating mode; and to output the second voltage when the operating mode is the second operating mode; wherein the first voltage is greater than the second voltage; The voltage-regulated output circuit includes a drive output circuit and a pull-down control circuit; wherein, the input terminal of the drive output circuit is connected to the power input terminal, and the ground terminal of the drive output circuit is grounded; the output terminal of the drive output circuit serves as the voltage-regulated output terminal; the voltage-regulated control terminal of the drive output circuit is connected to the output terminal of the operational amplifier and the first terminal of the pull-down control circuit, respectively, and the second terminal of the pull-down control circuit is grounded; the operating mode control terminal of the drive output circuit and the control terminal of the pull-down control circuit are respectively connected to the mode switching control circuit. The drive output circuit, under the control of the mode switching control circuit, when the operating mode is the first operating mode, respectively connects the output terminal of the drive output circuit to the input terminal and the ground terminal, converts the first voltage input to the power input terminal into the second voltage under the action of the operational amplifier, and outputs the second voltage through the regulated output terminal; when the operating mode is the second operating mode, under the action of the pull-down control circuit, connects the output terminal of the drive output circuit to the input terminal, and outputs the second voltage input to the power input terminal through the regulated output terminal.

2. The voltage regulator according to claim 1, characterized in that, The mode switching control circuit includes a level converter, a logic gate, and a control output terminal; wherein the level converter is connected to the logic gate, and the logic gate is connected to the control output terminal.

3. The voltage regulator according to claim 1, characterized in that, The operating mode also includes a third operating mode when the power input terminal receives a second voltage; wherein, in the third operating mode, the voltage regulator supports the connection of an external voltage to the regulated output terminal, and the external voltage is less than or equal to the second voltage.

4. The voltage regulator according to claim 1, characterized in that, The drive output circuit includes: a first resistor, a second resistor, a first switching unit, a second switching unit, and a first PMOS transistor; In this configuration, the first terminal of the first switching unit is connected to the power input terminal, and the second terminal of the first switching unit is connected to the source of the first PMOS transistor. The drain of the first PMOS transistor is connected to the first terminal of the second switching unit, and the common terminal of the connection serves as the regulated output terminal. The second terminal of the second switching unit is connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the first terminal of the second resistor, and the common terminal of the connection is connected to the non-inverting input terminal of the operational amplifier. The second terminal of the second resistor is grounded. The gate of the first PMOS transistor serves as the voltage regulation control terminal and is connected to the first terminal of the pull-down control circuit, and the common terminal of the connection is connected to the output terminal of the operational amplifier. The control terminals of the first and second switching units serve as the operating mode control terminals and are connected to the mode switching control circuit. The drive output circuit, under the control of the mode switching control circuit, when the operating mode is the first operating mode, turns on the first switching unit and the second switching unit, and under the action of the operational amplifier, converts the first voltage input to the power input terminal into the second voltage, and outputs the second voltage through the drain of the first PMOS; when the operating mode is the second operating mode, it turns on the first switching unit and turns off the second switching unit, and under the action of the pull-down control circuit, turns on the first PMOS and outputs the second voltage input to the power input terminal through the drain of the first PMOS.

5. The voltage regulator according to claim 1 or 2, characterized in that, The pull-down control circuit includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; In this circuit, the drain of the first NMOS transistor serves as the first terminal of the pull-down control circuit and is connected to the voltage regulation control terminal of the drive output circuit; the common terminal of this connection is connected to the output terminal of the operational amplifier. The drain of the second NMOS transistor is connected to the gate of the second NMOS transistor, and the common terminal of this connection is connected to the gate of the first NMOS transistor and the drain of the third NMOS transistor, respectively. The common terminal connecting the drain of the second NMOS transistor and the gate of the second NMOS transistor is used to connect to the positive terminal of a current source, and the negative terminal of the current source is used to connect to the power input terminal. The sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected, and the common terminal of this connection serves as the second terminal of the pull-down control circuit and is grounded. The control output terminal of the mode switching control circuit includes a first control output terminal. The gate of the third NMOS transistor is connected to the first control output terminal. When the operating mode is the second operating mode, the third NMOS transistor is turned off to turn on the first NMOS transistor and the second NMOS transistor to slowly pull down the voltage input to the voltage regulation control terminal of the drive output circuit to 0; when the operating mode is the first operating mode, the third NMOS transistor is turned on to turn off the first NMOS transistor and the second NMOS transistor.

6. The voltage regulator according to claim 5, characterized in that, The pull-down control circuit also includes: An isolation circuit is provided between the voltage regulation control terminal of the drive output circuit and the drain of the first NMOS transistor. When the operating mode is the first operating mode, the voltage output from the output terminal of the operational amplifier is isolated and converted into a preset voltage and output to the drain of the first NMOS transistor; wherein the preset voltage is less than or equal to the second voltage.

7. The voltage regulator according to claim 6, characterized in that, The isolation circuit includes: a third resistor, a fourth resistor, and a fourth NMOS transistor; In this circuit, the drain of the fourth NMOS transistor serves as the first terminal of the pull-down control circuit and is connected to the voltage regulation control terminal of the drive output circuit; the common terminal of this connection is connected to the output terminal of the operational amplifier. The source of the fourth NMOS transistor is connected to the drain of the first NMOS transistor. The first terminal of the third resistor is connected to the power input terminal. The second terminal of the third resistor is connected to the first terminal of the fourth resistor, and the common terminal of this connection is connected to the gate of the fourth NMOS transistor. The second terminal of the fourth resistor is grounded.

8. The voltage regulator according to claim 4, characterized in that, The first switching unit includes a second PMOS transistor, and the second switching unit includes a third PMOS transistor. The control output terminal of the mode switching control circuit includes a first control output terminal, a second control output terminal, and a third control output terminal. The source of the second PMOS transistor is connected to the power input terminal, the drain of the second PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the second PMOS transistor serves as the control terminal of the first switching unit and is connected to the second control output terminal. The source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the third PMOS transistor is connected to the first terminal of the first resistor, and the gate of the third PMOS transistor serves as the control terminal of the second switching unit and is connected to the third control output terminal. The first control output terminal, the second control output terminal, and the third control output terminal are all used to control the conduction or cutoff of their respective connected MOS transistors by outputting a first control level and / or a second control level.

9. A control method for a voltage regulator, characterized in that, Applied to the voltage regulator as described in any one of claims 1 to 8, comprising: Obtain the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator's regulated output circuit; the power supply voltage includes a first voltage and a second voltage; The operating mode of the voltage regulator is determined based on the power supply voltage configuration information; wherein, the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The voltage regulator's mode switching control circuit controls the voltage regulator output circuit to switch the voltage regulator to the operating mode.

10. A control device for a voltage regulator, characterized in that, Applied to the voltage regulator as described in any one of claims 1 to 8, comprising: The acquisition module is used to acquire the power supply voltage configuration information of the voltage regulator; wherein, the power supply voltage configuration information includes the power supply voltage at the power input terminal in the voltage regulator output circuit of the voltage regulator; the power supply voltage includes a first voltage and a second voltage; The determining module is used to determine the operating mode of the voltage regulator based on the power supply voltage configuration information; wherein the operating mode includes a first operating mode when the power supply voltage is a first voltage and a second operating mode when the power supply voltage is a second voltage; The control module is used to control the regulated output circuit through the mode switching control circuit of the voltage regulator to adjust the voltage regulator to switch to the working mode.

11. A control device for a voltage regulator, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the control method for the voltage regulator as described in claim 9 when executing the computer program.

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