Data output method, device, storage medium and electronic device

Abstract

The embodiment of the present invention provides a data output method, device, storage medium and electronic device, wherein the method includes: determining a first number of first output ports included in an output chip connected to an output port of a target chip; determining an output resolution of each first output port; determining a target memory layout parameter for writing target data in a memory of the target chip based on the first number and the output resolution; sending the target memory layout parameter to the output chip to instruct the output chip to split the target data received from the target chip according to the target memory layout parameter to obtain a first number of split data, and controlling each first output port to output a split data, wherein the data output by each first output port is different. Through the present invention, the problem of cache data consuming a large amount of resources of the output chip existing in the related art is solved, and the effect of reducing the resource cache consumption of the output chip is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular, to a data output method, device, storage medium and electronic device. Background Art

[0002] In the related art, when a device outputs data, an output chip needs to cache a whole frame of data, which results in high resource consumption of the output chip.

[0003] It can be seen from this that there is a problem in the related art that cache data consumes a large amount of resources of the output chip.

[0004] Currently, no effective solution has been proposed for the above-mentioned problems existing in the related technologies. Summary of the invention

[0005] The embodiments of the present invention provide a data output method, device, storage medium and electronic device to at least solve the problem in the related art that cached data consumes a large amount of resources of an output chip.

[0006] According to one embodiment of the present invention, a data output method is provided, comprising: performing the following operations for each target chip output port included in a target chip to determine target memory layout parameters of target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port; determining an output resolution of each of the first output ports; determining target memory layout parameters for writing target data in a memory of the target chip based on the first number and the output resolution; sending the target memory layout parameters to the output chip to instruct the output chip to split the target data received from the target chip according to the target memory layout parameters to obtain the first number of split data, and controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0007] According to an embodiment of the present invention, there is also provided a data output method, comprising: receiving target memory layout parameters and target data sent by a target chip, wherein the target memory layout parameters are obtained by the target chip in the following manner: performing the following operations for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port, determining an output resolution of each of the first output ports, and determining target memory layout parameters for writing target data in the memory of the target chip based on the first number and the output resolution; splitting the target data according to the target memory layout parameters to obtain the first number of split data; controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0008] According to another embodiment of the present invention, a data output device is provided, comprising: a first output module, configured to perform the following operations for each target chip output port included in a target chip to determine target memory layout parameters of target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port; determining an output resolution of each of the first output ports; determining target memory layout parameters for writing target data in a memory of the target chip based on the first number and the output resolution; sending the target memory layout parameters to the output chip to instruct the output chip to split the target data received from the target chip according to the target memory layout parameters to obtain the first number of split data, and controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0009] According to another embodiment of the present invention, there is also provided a data output device, comprising: a receiving module, used to receive target memory layout parameters and target data sent by a target chip, wherein the target memory layout parameters are obtained by the target chip in the following manner: the following operations are performed for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port, determining an output resolution of each of the first output ports, and determining target memory layout parameters for writing target data in the memory of the target chip based on the first number and the output resolution; a splitting module, used to split the target data according to the target memory layout parameters to obtain the first number of split data; a second output module, used to control each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0010] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0011] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0012] According to yet another embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0013] Through the present invention, the following operations are performed for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determine the first number of the first output ports included in the output chip connected to the target chip; determine the output resolution of each first output port; determine the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution; send the target memory layout parameters to the output chip to instruct the output chip to split the received target data sent by the target chip according to the target memory layout parameters to obtain the first number of split data, and control each first output port to output a split data, wherein the data output by each first output port is different. Since each target chip output port of the target chip can be connected to an external output chip, the target data is output by the first output port of the output chip, and the target data written in the memory of the target chip is written according to the target memory layout parameters determined by the output resolution of the first output port, the output chip splits the target data according to the target memory layout parameters when outputting the data, so that the layout of the memory filled matches the output rate of the output chip, therefore, the problem of consuming a large amount of resources of the output chip by cache data existing in the related art can be solved, and the effect of reducing the resource cache consumption of the output chip can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a hardware structure block diagram of a mobile terminal of a data output method according to an embodiment of the present invention;

[0015] Figure 2 The process of the data output method according to the embodiment of the present invention is as follows Figure 1 ;

[0016] Figure 3 is a schematic diagram of the connection relationship between the target chip and the output chip according to an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of a flow chart of setting a memory sub-layout according to an output resolution according to an embodiment of the present invention;

[0018] Figure 5 is a schematic diagram of dividing target data according to an embodiment of the present invention;

[0019] Figure 6 is a schematic diagram of the first output port supporting different resolution divisions according to an embodiment of the present invention;

[0020] Figure 7 The process of the data output method according to the embodiment of the present invention is as follows Figure 2 ;

[0021] Figure 8is a flow chart of a method for outputting data according to a specific embodiment of the present invention;

[0022] Fig. 9 is a structural frame of a data output device according to an embodiment of the present invention Figure 1 ;

[0023] Fig.10 is a structural frame of a data output device according to an embodiment of the present invention Figure 2 . DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0026] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal of a data output method according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0027] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the data output method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0028] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0029] In this embodiment, a data output method is provided. The following steps S202-S208 are performed for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port.

[0030] Figure 2 The process of the data output method according to the embodiment of the present invention is as follows Figure 1 ,like Figure 2 As shown, the process includes the following steps:

[0031] Step S202, determining a first number of first output ports included in an output chip connected to a target chip;

[0032] In this embodiment, the target chip may be a system-on-chip SOC, and the output chip may be an FPGA output chip. The target chip may include multiple target chip output ports, for example, multiple HDMI2.0 interfaces that support 4K output, and the target chip may be connected to the output chip through the HDMI2.0 interface that supports 4K output. The output chip may include a first number of first output ports, the first number may be an integer greater than 1, and the first output port may be an HDMI1.4 interface. When the target chip is a SOC chip and the output chip is an FPGA chip, the schematic diagram of the connection relationship between the target chip and the output chip can be found in the attached Figure 3 ,like Figure 3 As shown, the SOC chip includes two HDMI2.0 interfaces. The SOC can be connected to two FPGA output chips through two HDMI2.0 interfaces that support 4K output. Each FPGA output chip includes four HDMI1.4 interfaces. The SOC chip can use I2C to configure the detailed timing information of each output port HDMI1.4 of the output FPGA chip. The SOC chip and the output FPGA chip are connected via HDMI.

[0033] In this embodiment, since the target chip supports a limited number of HDMI output ports, an external output chip can be connected through the target chip's HDMI2.0 output port that supports 4K. The output chip includes multiple first output ports, thereby expanding the target chip's native HDMI output ports and solving the problem of insufficient native HDMI output ports of the target chip.

[0034] In the above embodiment, the pixel clock supported by the target chip outputting HDMI may be n times the pixel clock of the second output port, where n is an integer greater than or equal to 2. The first number may be expressed as , where pixel_clock soc Indicates that the target chip outputs the pixel clock supported by HDMI, pixel_clock output The pixel clock of the second output port. Step S204, determining the output resolution of each of the first output ports;

[0035] In this embodiment, the output resolution of each first output port of the output chip can be customized, and the output resolution set for each first output port in the resolution setting instruction can be determined by receiving a resolution setting instruction. Different first output ports can be set with the same resolution or with different resolutions. The hardware restriction of the target chip on the HDMI output width / height is lifted, and the ultra-high / ultra-wide customized resolution output function is realized.

[0036] In the above embodiment, when implementing 4k output, the output resolution of each first output port can be customized to comply with the following principles:

[0037] Principle 1. The total pixel clock of the output custom resolution should be as close to 148.5MHz as possible;

[0038] Principle 2. The product of Htotal (total horizontal pixels) and Vtotal (total vertical lines) of the output custom resolution should be as close as possible to 2475k (i.e. 148500k / 60) pixels;

[0039] Principle 3. The product of the output custom total active pixels Hactive (horizontal total active pixels) and Vactive (vertical total active lines) cannot be greater than 2073.6k (i.e.: 1920x1080) pixels.

[0040] Step S206, determining a target memory layout parameter for writing target data into the memory of the target chip based on the first number and the output resolution;

[0041] In this embodiment, the target memory layout parameter can be calculated as a specific resolution memory layout. By calculating the target memory layout parameter, the target chip output effective data rate can be equal to the output chip output effective data rate, and the amount of data required to be cached by the output chip is minimized, while effectively reducing the delay between the target chip output and the output chip output. Taking 1080P as an example, the output chip only needs to cache 4 lines x 1920 to directly output, without caching the entire frame of the image before outputting.

[0042] Step S208, sending the target memory layout parameters to the output chip to instruct the output chip to split the target data sent by the target chip according to the target memory layout parameters to obtain the first number of split data, and control each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0043] In this embodiment, the target data may be data such as images and video frames. Through the HDMI method, the target chip can output the display output target data to the output chip. Then, the output chip splits the data according to the target memory layout parameters, splits it into the corresponding channel cache queue, and selects valid pixel data from the channel cache queue to the channel display queue. Finally, the output chip outputs the data of the channel display queue according to the set HDMI detailed timing. By sending the target memory layout parameters to the output chip, the output chip splits the target data, so that the layout of the target chip filling in the memory matches the output rate of the output chip, and reduces the resource cache consumption of the output chip.

[0044] See the attached Figure 3, when the first number is 4, an HDMI 2.0 output port of the target chip that supports 4K outputs 3840x2160@60 according to the standard CEA-861 timing, and the output chip splits the received target data into 4 parts, and then outputs each according to the new HDMI timing set by the output port. This splitting method determines that the maximum total effective data volume of each output port of the output chip must be less than or equal to 1920x1080 pixels. The target data output by a SOC chip is split into 4 parts by the output FPGA chip, and then output using HDMI respectively. The total number of HDMI1.4 output ports that a SOC chip can split is determined by the number of native HDMI2.0 output ports of the SOC chip, that is, the maximum number of expandable HDMI1.4 output ports is 4xN (N: the maximum number of native HDMI2.0 output ports that the SOC chip supports to support 4K).

[0045] In this embodiment, the split data outputted from each first output port of the output chip can be outputted separately on the display, or the split data outputted from a plurality of first output ports can be spliced ​​to achieve data splicing output.

[0046] Optionally, the execution subject of the above steps may be a target chip, such as a system-on-system SOC, but is not limited thereto.

[0047] Through the present invention, the following operations are performed for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determine the first number of the first output ports included in the output chip connected to the target chip; determine the output resolution of each first output port; determine the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution; send the target memory layout parameters to the output chip to instruct the output chip to split the received target data sent by the target chip according to the target memory layout parameters to obtain the first number of split data, and control each first output port to output a split data, wherein the data output by each first output port is different. Since each target chip output port of the target chip can be connected to an external output chip, the target data is output by the first output port of the output chip, and the target data written in the memory of the target chip is written according to the target memory layout parameters determined by the output resolution of the first output port, the output chip splits the target data according to the target memory layout parameters when outputting the data, so that the layout of the memory filled matches the output rate of the output chip, therefore, the problem of consuming a large amount of resources of the output chip by cache data existing in the related art can be solved, and the effect of reducing the resource cache consumption of the output chip can be achieved.

[0048] In an exemplary embodiment, determining the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution includes: dividing the target data according to the first number to obtain the first number of sub-data; performing the following operations for each target sub-data included in the sub-data to determine the sub-memory layout parameters for writing the target sub-data in the target chip: determining a second output port included in the first output port for outputting the target sub-data, determining a target output resolution of the second output port included in the output resolution, determining the row effective pixels of the target chip output data as the first row effective pixels, and setting the row effective pixels of the second output port output data to the first row effective pixels. The pixel is determined as a valid pixel of the second row, based on the first row of valid pixels and the second row of valid pixels, the rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port is determined, based on the rate ratio, the number of rows of valid pixels output by the second output port accounts for the total number of pixels of the target sub-data, based on the total number of pixels, the third number of minimum storage units for storing the target sub-data is determined, based on the third number, the sub-memory layout parameters are determined, wherein the size of the minimum storage unit is the same as the size of the cache line of the memory of the target chip; the sub-memory layout parameters of all the target sub-data are determined as the target memory layout parameters. In this embodiment, the memory sub-layout process flow diagram that can be set according to the output resolution can be found in the attached Figure 4 ,like Figure 4 As shown, the process includes:

[0049] Step S402, setting the resolution information of the output port, that is, the target output resolution.

[0050] Step S404, determining whether the resolution belongs to CEA-861 timing, if the determination result is yes, executing step S406, if the determination result is no, executing step S408.

[0051] Step S406: Output detailed timing according to CEA-861 timing.

[0052] Step S408, calculating the custom timing.

[0053] Step S410, calculating the memory arrangement of a specific resolution, that is, the memory sub-layout.

[0054] In the above embodiment, since the output resolution of each first output port can be different and the split data output by each first output port is different, the memory sub-layout for the target sub-data output by each first output port can be calculated separately, so that when the target sub-data is output by the first output port, the storage method of the target sub-data is adapted to the output resolution of the first output port.

[0055] In the above embodiment, the schematic diagram of dividing the target data can be found in the attached Figure 5 ,like Figure 5 As shown, the target data output by the target chip may be region A, and the total resolution of region A may be 3840x2160 pixels (this value is only an exemplary description, and the present invention is not limited to this). Region A may be divided according to a first number. When the resolution of region A is 3840x2160 pixels, it may be divided into 4 groups, resulting in an average of 960x2160 pixels. Each group of regions is called region B. When region A is divided, the output resolution of each first output port is the same. Region A may also be divided according to a custom resolution, and the output resolutions of the first output ports may be set to be different or partially the same. A schematic diagram of the first output port supporting different resolution divisions can be found in the attached figure. Figure 6 . Area B is divided into 540 groups according to 960x4 pixels, and each group of areas is called area C; area C is divided into 240 groups according to 4x4 pixels, and each group of areas is called area D. Area D is called the minimum unit for storing data, that is, the minimum storage unit. The minimum storage unit meets the cache line alignment with the target chip, which improves the DDR storage efficiency. Among them, when the display layer is XRGB8888, one pixel is 4Byte. The amount of data stored in area D is 4x4x4=64Byte.

[0056] It should be noted that the above numerical values ​​are all exemplary descriptions, and different numerical values ​​can be set according to output requirements and the format of target data, and the present invention is not limited to this.

[0057] In the above embodiment, the row effective pixels of the target chip area B can be calculated, which is referred to as the first row effective pixels, and the row effective pixels of the output chip can be calculated, which is referred to as the second row effective pixels. The rate ratio of the target chip outputting 1 effective pixel to the output chip outputting 1 effective pixel is determined based on the first row effective pixels and the second row effective pixels. The total number of pixels occupied by the effective pixels of the output chip output area D row in the target chip area B is calculated based on the rate ratio, and the total number of pixels is converted into the number of pixels used in area D, that is, the third number. Then, the memory sub-layout parameters are determined based on the third number. After determining the memory sub-layout parameters of each target sub-data, each target sub-data can be written into the memory of the target chip according to its corresponding memory sub-layout parameters. Among them, the layout parameters composed of all memory sub-layout parameters can be determined as the target memory layout parameters.

[0058] In an exemplary embodiment, determining the rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port based on the first row of valid pixels and the second row of valid pixels includes: determining a first pixel clock of the target chip output port to output the target sub-data, and determining a second pixel clock of the target sub-data output by the second output port; determining a first ratio of the first pixel clock to the second pixel clock; determining a second ratio of the first row of valid pixels to the total number of pixels in a row of data output by the target chip output port; determining a third ratio of the second row of valid pixels to the total number of pixels in a row of data output by the second output port; determining the ratio of the second ratio to the third ratio to obtain a fourth ratio; determining a first product of the fourth ratio and the first ratio; and determining the first product as the rate ratio. In this embodiment, the ratio A of the first pixel clock of the target sub-data to the second pixel clock of the output chip can be calculated for each area B of the target chip. That is, the first ratio can be expressed as , where Pixel_Clock output Indicates the pixel clock of the output chip output resolution, that is, the second pixel clock, Pixel_Clock regionB The pixel clock representing the target sub-data is the first pixel clock. The first pixel clock may be the ratio of the data size to the first number when the target chip HDMI2.0 output resolution is the first resolution. The first pixel clock may be represented as .in, Indicates the target pixel clock output by the target chip; n: indicates the number of regions divided by the video memory, that is, the first quantity. For example, when the target chip HDMI2.0 outputs 4K resolution, the pixel clock output by the target chip is 594MHz and the first quantity is 4, the first pixel clock is 594MHz / 4, and the first ratio ratioA can be expressed as 594MHz / 4 / Pixel_Clock output .

[0059] In the above embodiment, the ratio ratio B of the row effective pixels Hactive and the row total pixels Htotal at the output port of the target chip can be calculated. The ratio B can be expressed as .in, Indicates the total effective pixels of the target chip output level. The third ratio RatioC of the row effective pixels Hactive and the row total pixels Htotal of the output chip can be calculated, where the third ratio can be expressed as ,in, Indicates the horizontal effective pixels output by the output chip. It indicates the total number of pixels output horizontally by the output chip. It is also possible to calculate the rate ratio of the target chip outputting one effective pixel to the output chip outputting one row of effective pixels. The rate ratio can be expressed as .

[0060] In the above embodiment, it is assumed that the resolution of one HDMI output port of the target chip in case 1 is 3840x2160@60, the total horizontal pixels are 4400 pixels, the effective horizontal pixels are 3840 pixels, the total vertical lines are 2250 lines, the total vertical effective lines are 2160 lines, and the pixel clock is 594MHz. The resolution output by the second output port of the output chip is 1920x1080@60, the total horizontal pixels are 2200 pixels, the effective horizontal pixels are 1920 pixels, the total vertical lines are 1125 lines, the total vertical effective lines are 1080 lines, and the pixel clock is 148.5MHz. One HDMI output port of the target chip is divided into 4 sub-areas, that is, 4 sub-data are obtained and output in 4 sub-areas: RatioA: 594Mhz / 4 parts / 148.5Mhz = 1.0; RatioB: 3840 / 4400=0.873; RatioC: 1920 / 2200=0.873; RatioD: (0.873 / 0.873)x1.0 = 1.0.

[0061] In an exemplary embodiment, determining the number of effective pixels in the row of the second output port occupying the total number of pixels in the target sub-data based on the rate ratio includes: determining the output level effective pixels of the second output port; determining the number of rows of the minimum storage unit included in the target sub-data; determining the second product of the rate ratio, the output level effective pixels and the number of rows; and determining the second product as the total number of pixels. In this embodiment, the total number of pixels Hoccupy occupied by the effective pixels in the output area D of the output chip in the target chip area B can be calculated, and Hoccupy can be expressed as ,in, Indicates the horizontal effective pixels output by the output chip; Indicates the number of rows in area D. In case 1, Hoccupy is 1.0x1920x4 rows = 7680 pixels.

[0062] In an exemplary embodiment, determining the third number of minimum storage units for storing the target sub-data based on the total number of pixels includes: determining a fifth ratio of the total number of pixels to the number of rows of the minimum storage unit included in the target sub-data; and determining a value obtained by rounding up the fifth ratio as the third number. In this embodiment, the total number of pixels Hocupy can be converted into the number of used pixels N of the region D. D , which is the third quantity. The third quantity can be expressed as . Among them, align_up: indicates upward integer alignment; R regionD Indicates the number of rows in region D. In case 1, N D = (7680+3) / 4 = 1920. In an exemplary embodiment, determining the sub-memory layout parameters based on the third number includes: determining the third product of the output horizontal effective pixels of the second output port and the number of rows of the minimum storage unit included in the target sub-data; determining the sixth ratio of the output horizontal effective pixels of the target chip output port to the number of rows; determining the seventh ratio of the third product to the sixth ratio; dividing the target sub-data according to the fourth number of rows to obtain target divided data; determining the fifth number of minimum storage units included in the target divided data; determining the fourth product of the seventh ratio and the fifth number; determining the target difference between the third number and the fourth product; determining the sub-memory layout parameters includes selecting the third number of the minimum storage units in the memory of the target chip to write the target sub-data, and selecting the minimum storage unit of the target difference in the memory of the target chip not to write data. The output chip output area D row effective pixels can be converted into the effective number Na of area D, that is, the fourth product. Among them, the fourth product can be expressed as ,in, Indicates the output horizontal effective pixels of the output chip; represents the number of rows in region D, Indicates the output level effective pixels of the target chip, represents the total number of regions D contained in region C (target partition data), i.e., the fifth number. The target difference can be expressed as the number of unused regions D, Nn, which can be expressed as In case 1, Na: 1920x4 rows / (3840 / 4 copies)x240 pieces=1920 pieces, Nn: 1920-1920=0 pieces.

[0063] In the above embodiment, after determining the number of write areas and the number of non-write areas, the target chip can write the target sub-data into the memory according to the memory sub-layout parameters. In the above embodiment, the target chip calculates the detailed timing of the specific resolution and the target memory layout parameters of the specific resolution according to the resolution of the Nth HDMI output port of the output chip; the target chip configures the detailed timing of the Nth HDMI output port of the output chip through I2C; the target chip fills in the valid pixel data of area B according to the target memory layout parameters of the specific resolution; the target chip can output valid data to the output chip through HDMI2.0, and the output chip obtains and parses the valid data through the HDMI2.0 protocol; the output chip splits the data into each output channel cache queue according to the target memory layout parameters; the output chip takes data from the cache queue and separates the valid data according to the target memory layout parameters of the specific resolution. If it is confirmed to be valid data, the data is put into the display queue of the output channel; if it is confirmed that it is not valid data, the data is directly discarded; the output chip sends data according to the set detailed timing, and dynamically adjusts the pixel clock according to the FIFO situation of the display channel queue to prevent FIFO overflow or starvation.

[0064] In an exemplary embodiment, determining the first pixel clock of the target chip output port outputting the target sub-data includes: determining the target pixel clock of the target chip; determining an eighth ratio of the target pixel clock to the first number; and determining the eighth ratio as the first pixel clock. In this embodiment, the target pixel clock of the target chip may be a clock corresponding to the output resolution of the target chip. The first pixel clock of the target sub-data may be expressed as ,in, Indicates the pixel clock output by the target chip; n: indicates the number of areas divided into the display layer, that is, the first quantity.

[0065] In an exemplary embodiment, determining the output resolution of each first output port includes: receiving a resolution setting instruction; and determining the output resolution of each first output port based on the resolution setting instruction. In this embodiment, the output resolution of each first output port can be set according to the resolution setting instruction to achieve customized settings for each second output port.

[0066] In this embodiment, a method for outputting data is provided. Figure 7 The process of the data output method according to the embodiment of the present invention is as follows Figure 2 ,like Figure 7 As shown, the process includes the following steps:

[0067] Step S702, receiving target memory layout parameters and target data sent by a target chip, wherein the target memory layout parameters are obtained by the target chip in the following manner: performing the following operations for each target chip output port included in the target chip to determine target memory layout parameters of target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port, determining an output resolution of each of the first output ports, and determining target memory layout parameters for writing target data in a memory of the target chip based on the first number and the output resolution;

[0068] Step S704, splitting the target data according to the target memory layout parameter to obtain the first number of split data;

[0069] Step S706, controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0070] In this embodiment, the target chip may be a system-on-chip SOC, and the output chip may be an FPGA output chip. The target chip may include multiple target chip output ports, for example, multiple HDMI2.0 interfaces that support 4K output, and the target chip may be connected to the output chip through the HDMI2.0 interface that supports 4K output. The output chip may include a first number of first output ports, the first number may be an integer greater than 1, and the first output port may be an HDMI1.4 interface. When the target chip is a SOC chip and the output chip is an FPGA chip, the schematic diagram of the connection relationship between the target chip and the output chip can be found in the attached Figure 3 ,like Figure 3As shown, the SOC chip includes two HDMI2.0 interfaces. The SOC can be connected to two FPGA output chips through two HDMI2.0 interfaces that support 4K output. Each FPGA output chip includes four HDMI1.4 interfaces. The SOC chip can use I2C to configure the detailed timing information of each output port HDMI1.4 of the output FPGA chip. The SOC chip and the output FPGA chip are connected via HDMI.

[0071] In the above embodiment, since the number of HDMI output ports supported by the target chip is limited, an external output chip can be connected through the HDMI2.0 output port that supports 4K of the target chip. The output chip includes multiple first output ports, which realizes the expansion of the native HDMI output port of the target chip and solves the problem of insufficient native HDMI output ports of the target chip. The output resolution of each first output port of the output chip can be customized, and the output resolution set for each first output port in the resolution setting instruction can be determined by receiving a resolution setting instruction. Different first output ports can be set with the same resolution or with different resolutions. The hardware restrictions on the HDMI output width / height of the target chip are lifted, and the ultra-high / ultra-wide custom resolution output function is realized.

[0072] In the above embodiment, when implementing 4k output, the output resolution of each first output port can be customized to comply with the following principles:

[0073] Principle 1. The total pixel clock of the output custom resolution should be as close to 148.5MHz as possible;

[0074] Principle 2. The product of Htotal (total horizontal pixels) and Vtotal (total vertical lines) of the output custom resolution should be as close as possible to 2475k (i.e. 148500k / 60) pixels;

[0075] Principle 3. The product of the output custom total active pixels Hactive (horizontal total active pixels) and Vactive (vertical total active lines) cannot be greater than 2073.6k (i.e.: 1920x1080) pixels.

[0076] In the above embodiment, the target chip calculates the target memory layout parameter which can be a specific resolution memory layout. By calculating the target memory layout parameter, the target chip output effective data rate can be equal to the output chip output effective data rate, and the amount of data required to be cached by the output chip is minimized, while effectively reducing the delay between the target chip output and the output chip output. Taking 1080P as an example, the output chip only needs to cache 4 lines x 1920, and can directly output without caching the entire frame of the image before outputting.

[0077] In the above embodiment, the target data may be data such as images and video frames. Through the HDMI method, the target chip can output the display output target data to the output chip. Then, the output chip splits the data according to the target memory layout parameters, splits it into the corresponding channel cache queue, and selects valid pixel data from the channel cache queue to the channel display queue. Finally, the output chip outputs the data of the channel display queue according to the set HDMI detailed timing. By sending the target memory layout parameters to the output chip, the output chip splits the target data, so that the layout of the target chip filling in the memory matches the output rate of the output chip, and reduces the resource cache consumption of the output chip.

[0078] See the attached Figure 3 , when the first number is 4, an HDMI 2.0 output port of the target chip that supports 4K outputs 3840x2160@60 according to the standard CEA-861 timing, and the output chip splits the received target data into 4 parts, and then outputs each according to the new HDMI timing set by the output port. This splitting method determines that the maximum total effective data volume of each output port of the output chip must be less than or equal to 1920x1080 pixels. The target data output by a SOC chip is split into 4 parts by the output FPGA chip, and then output using HDMI respectively. The total number of HDMI1.4 output ports that a SOC chip can split is determined by the number of native HDMI2.0 output ports of the SOC chip, that is, the maximum number of expandable HDMI1.4 output ports is 4xN (N: the maximum number of native HDMI2.0 output ports that the SOC chip supports to support 4K).

[0079] In the above embodiment, the split data outputted by each first output port of the output chip can be outputted separately on the display, or the split data outputted by a plurality of first output ports can be spliced ​​to realize data splicing output.

[0080] Optionally, the execution subject of the above steps may be output information, such as an FPGA chip.

[0081] Through the present invention, the following operations are performed for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determine the first number of the first output ports included in the output chip connected to the target chip; determine the output resolution of each first output port; determine the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution; send the target memory layout parameters to the output chip to instruct the output chip to split the received target data sent by the target chip according to the target memory layout parameters to obtain the first number of split data, and control each first output port to output a split data, wherein the data output by each first output port is different. Since each target chip output port of the target chip can be connected to an external output chip, the target data is output by the first output port of the output chip, and the target data written in the memory of the target chip is written according to the target memory layout parameters determined by the output resolution of the first output port, the output chip splits the target data according to the target memory layout parameters when outputting the data, so that the layout of the memory filled matches the output rate of the output chip, therefore, the problem of consuming a large amount of resources of the output chip by cache data existing in the related art can be solved, and the effect of reducing the resource cache consumption of the output chip can be achieved.

[0082] In an exemplary embodiment, controlling each of the first output ports to output one of the split data includes: determining split valid data from the split data based on the output resolution; and outputting the split valid data according to the detailed timing of the pre-received data output. In this embodiment, the output chip splits the data according to the target memory layout parameters, splits it into corresponding channel buffer queues, and selects valid pixel data from the channel buffer queue to the channel display queue. Finally, the output chip outputs the data of the channel display queue according to the set HDMI detailed timing.

[0083] In an exemplary embodiment, after controlling each of the first output ports to output one of the split data, the method further includes: determining the storage state of the first-in-first-out queue of the display queue for storing the split data; and adjusting the pixel clock of the first output port based on the storage state. In this embodiment, the output FPGA chip sends data according to the set detailed timing, and adjusts the pixel clock according to the FIFO situation of the display channel queue to prevent FIFO overflow or starvation. For example, the output chip can determine whether the storage state of the first-in-first-out queue in the display channel queue is lower than the threshold value at which the first-in-first-out queue will be empty, or determine whether the storage state of the first-in-first-out queue in the display channel queue is higher than the threshold value at which the first-in-first-out queue will be full. If it is higher than the threshold value at which the first-in-first-out queue will be full, the pixel clock is increased to accelerate data transmission until the FIFO is lower than the set threshold value, and if it is lower than the FIFO empty threshold value, the pixel clock is reduced to slow down data transmission until the FIFO is higher than the set threshold value.

[0084] The data output method is described below in conjunction with a specific implementation method, taking the target chip as a SOC chip and the output chip as an output FPGA chip as an example:

[0085] Figure 8 is a flow chart of a method for outputting data according to a specific embodiment of the present invention. Figure 8 As shown, the process includes:

[0086] Step S802, the SOC chip calculates the detailed timing of the specific resolution and the specific memory layout of the specific resolution (corresponding to the above-mentioned memory sub-layout) according to the resolution of the Nth HDMI output port;

[0087] Step S804, the SOC chip configures the detailed timing of the Nth HDMI output port of the FPGA through the I2C method;

[0088] Step S806, the SOC chip fills in the valid pixel data of area B according to the memory layout of the specific resolution;

[0089] Step S808, the SOC chip outputs valid data to the output FPGA chip through HDMI2.0, and the output FPGA chip obtains and parses the valid data through the HDMI2.0 protocol;

[0090] Step S810, the output FPGA chip splits the data into each output channel cache queue according to the overall memory layout;

[0091] Step S812, the output FPGA chip takes data from the cache queue and separates valid data according to the memory layout of the specific resolution. If it is confirmed to be valid data, the data is put into the display queue of the output channel; if it is confirmed not to be valid data, the data is directly discarded;

[0092] In step S814, the FPGA chip determines whether the storage state of the FIFO queue in the display channel queue is lower than the threshold at which the FIFO queue will be empty, or determines whether the storage state of the FIFO queue in the display channel queue is higher than the threshold at which the FIFO queue will be full. If the judgment result is yes, step S816 is executed, and if the judgment result is no, step S818 is executed.

[0093] Step S816, if it is higher than the threshold that the FIFO will be full, the pixel clock is increased to speed up data transmission until the FIFO is lower than the set threshold; if it is lower than the FIFO empty threshold, the pixel clock is reduced to slow down data transmission until the FIFO is higher than the set threshold.

[0094] Step S818, FPGA outputs the channel display queue data according to the set HDMI detailed timing.

[0095] Step S820, determine whether the frame data has been generated. If the judgment result is yes, execute step S808, if the judgment result is no, execute step S814.

[0096] In the above embodiment, the format of the video memory of the SOC chip can be XRGB8888, and the HDMI output format can be RGB444. The format of the video memory of the SOC chip can also be YUY2 or AYUV, and the HDMI output format can also be YUV444, which is not limited by the present invention.

[0097] In the aforementioned embodiment, the SOC chip display module is directly connected to the DDR interface, which is more efficient than the output FPGA chip accessing the DDR through the PCIe method. The memory layout enables different HDMI output ports to output different content. Under the same output resolution, the HDMI output port can be used in video splicing scenarios. The native HDMI2.0 of the SOC chip supports 4k output ports, which can expand the output of HDMI signals of 4 different pictures according to the overall memory layout, where the minimum storage area D is cache line (64Byte) aligned, which improves the DDR storage efficiency; the SOC chip output effective pixel rate matches the FPGA output effective pixel rate, effectively reducing the internal cache of the output FPGA chip, while reducing the transmission delay between the SOC output and the output FPGA chip.

[0098] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0099] In the present embodiment, a data output device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions thereof will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and contemplated.

[0100] Fig. 9 is a structural frame of a data output device according to an embodiment of the present invention Figure 1 ,like Fig. 9 As shown, the device comprises:

[0101] The first output module 92 is used to perform the following operations for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determine the first number of first output ports included in the output chip connected to the target chip output port; determine the output resolution of each of the first output ports; determine the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution; send the target memory layout parameters to the output chip to instruct the output chip to split the target data received from the target chip according to the target memory layout parameters to obtain the first number of split data, and control each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0102] In an exemplary embodiment, the first output module 92 can determine the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution in the following manner: divide the target data according to the first number to obtain the first number of sub-data; perform the following operations for each target sub-data included in the sub-data to determine the sub-memory layout parameters for writing the target sub-data in the target chip: determine a second output port included in the first output port for outputting the target sub-data, determine a target output resolution for the second output port included in the output resolution, determine the row effective pixels of the target chip output data as the first row effective pixels, and set the second output port The row effective pixels of the output data are determined to be the second row effective pixels, and the rate ratio of an effective pixel of the target sub-data output by the target chip to an effective pixel of the split data output by the second output port is determined based on the first row effective pixels and the second row effective pixels, and the number of row effective pixels output by the second output port accounts for the total number of pixels of the target sub-data is determined based on the rate ratio, and the third number of minimum storage units for storing the target sub-data is determined based on the total number of pixels, and the sub-memory layout parameters are determined based on the third number, wherein the size of the minimum storage unit is the same as the size of a cache line of the memory of the target chip; the sub-memory layout parameters of all the target sub-data are determined as the target memory layout parameters.

[0103] In an exemplary embodiment, the first output module 92 can determine the rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port based on the first row of valid pixels and the second row of valid pixels in the following manner: determine a first pixel clock for the target chip output port to output the target sub-data, and determine a second pixel clock for the second output port to output the target sub-data; determine a first ratio of the first pixel clock to the second pixel clock; determine a second ratio of the first row of valid pixels to the total number of pixels in a row of data output by the target chip output port; determine a third ratio of the second row of valid pixels to the total number of pixels in a row of data output by the second output port; determine the ratio of the second ratio to the third ratio to obtain a fourth ratio; determine a first product of the fourth ratio and the first ratio; and determine the first product as the rate ratio.

[0104] In an exemplary embodiment, the first output module 92 can determine the number of rows of valid pixels output by the second output port to the total number of pixels of the target sub-data based on the rate ratio in the following manner: determine the output horizontal valid pixels of the second output port; determine the number of rows of the minimum storage unit included in the target sub-data; determine the second product of the rate ratio, the output horizontal valid pixels and the number of rows; and determine the second product as the total number of pixels. In an exemplary embodiment, the first output module 92 can determine the third number of minimum storage units for storing the target sub-data based on the total number of pixels in the following manner: determine the fifth ratio of the total number of pixels to the number of rows of the minimum storage unit included in the target sub-data; and determine the value obtained by rounding up the fifth ratio as the third number.

[0105] In an exemplary embodiment, the first output module 92 can determine the sub-memory layout parameters based on the third number in the following manner: determine the third product of the output horizontal effective pixels of the second output port and the number of rows of the minimum storage unit included in the target sub-data; determine the sixth ratio of the output horizontal effective pixels of the target chip output port to the number of rows; determine the seventh ratio of the third product to the sixth ratio; divide the target sub-data according to a fourth number of rows to obtain target divided data; determine the fifth number of minimum storage units included in the target divided data; determine the fourth product of the seventh ratio and the fifth number; determine the target difference between the third number and the fourth product; determine the target difference between the third number and the fifth ratio; determine that the sub-memory layout parameters include selecting the third number of the minimum storage units in the memory of the target chip to write the target sub-data, and selecting the minimum storage unit of the target difference in the memory of the target chip not to write data.

[0106] In an exemplary embodiment, the first output module 92 can determine the first pixel clock of the target chip output port to output the target sub-data in the following manner: determine the target pixel clock of the target chip; determine the eighth ratio of the target pixel clock to the first number; and determine the eighth ratio as the first pixel clock.

[0107] In an exemplary embodiment, the first output module 92 may determine the output resolution of each of the first output ports in the following manner: receiving a resolution setting instruction; and determining the output resolution of each of the first output ports based on the resolution setting instruction.

[0108] Fig.10 is a structural frame of a data output device according to an embodiment of the present invention Figure 2 ,like Fig.10 As shown, the device comprises:

[0109] The receiving module 1002 is used to receive target memory layout parameters and target data sent by a target chip, wherein the target memory layout parameters are obtained by the target chip in the following manner: performing the following operations for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port, determining an output resolution of each of the first output ports, and determining the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution;

[0110] A splitting module 1004 is used to split the target data according to the target memory layout parameter to obtain the first number of split data;

[0111] The second output module 1006 is used to control each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different.

[0112] In an exemplary embodiment, the second output module 1006 can control each of the first output ports to output one of the split data in the following manner: determine split valid data from the split data based on the output resolution; and output the split valid data according to the detailed timing of the pre-received data output.

[0113] In an exemplary embodiment, the device can be used to determine the storage status of a first-in-first-out queue of a display queue for storing the split data after controlling each of the first output ports to output the split data; and adjust the pixel clock of the first output port based on the storage status.

[0114] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0115] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0116] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0117] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0118] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0119] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of the method in each embodiment of the present application when the computer program is executed by a processor.

[0120] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0121] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data output method, applied to a target chip, characterized in that: include: The following operations are performed for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port; determining an output resolution of each of the first output ports; Determining target memory layout parameters for writing target data in a memory of the target chip based on the first number and the output resolution; Sending the target memory layout parameter to the output chip to instruct the output chip to split the target data sent by the target chip according to the target memory layout parameter to obtain the first number of split data, and controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different; Determining the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution includes: dividing the target data according to the first number to obtain the sub-data of the first number; performing the following operations for each target sub-data included in the sub-data to determine the sub-memory layout parameters for writing the target sub-data in the target chip: determining a second output port included in the first output port for outputting the target sub-data, determining a target output resolution of the second output port included in the output resolution, determining the row effective pixels of the output data of the target chip output port as the first row effective pixels, and determining the row effective pixels of the output data of the second output port as The second row is determined to be valid, based on the first row of valid pixels and the second row of valid pixels, a rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port is determined, based on the rate ratio, the number of rows of valid pixels output by the second output port accounts for the total number of pixels of the target sub-data, based on the total number of pixels, a third number of minimum storage units for storing the target sub-data is determined, based on the third number, the sub-memory layout parameters are determined, wherein the size of the minimum storage unit is the same as the size of the cache line of the memory of the target chip; the sub-memory layout parameters of all the target sub-data are determined as the target memory layout parameters.

2. The method according to claim 1, characterized in that Determining the rate ratio of one valid pixel of the target sub-data output by the target chip to one valid pixel of the split data output by the second output port based on the first row of valid pixels and the second row of valid pixels includes: Determine a first pixel clock at which the target chip output port outputs the target sub-data, and determine a second pixel clock at which the second output port outputs the target sub-data; determining a first ratio of the first pixel clock to the second pixel clock; Determine a second ratio of the first row of valid pixels to the total number of pixels in a row of output data of the target chip output port; Determine a third ratio of the second row of valid pixels to the total number of pixels in the row of output data of the second output port; determining a ratio of the second ratio to the third ratio to obtain a fourth ratio; determining a first product of the fourth ratio and the first ratio; The first product is determined as the rate ratio.

3. The method according to claim 1, characterized in that: Determining the number of valid pixels in a row output by the second output port as a percentage of the total number of pixels in the target sub-data based on the rate ratio includes: Determine an output horizontal effective pixel of the second output port; Determining the number of rows of the minimum storage unit included in the target sub-data; determining a second product of the rate ratio, the output horizontal effective pixels and the number of rows; The second product is determined as the total number of pixels.

4. The method according to claim 1, characterized in that: Determining a third number of minimum storage units for storing the target sub-data based on the total number of pixels includes: determining a fifth ratio of the total number of pixels to the number of rows of the minimum storage unit included in the target sub-data; A value obtained by rounding up the fifth ratio is determined as the third number.

5. The method according to claim 1, characterized in that Determining the sub-memory layout parameter based on the third quantity includes: determining a third product of the output horizontal effective pixels of the second output port and the number of rows of the minimum storage unit included in the target sub-data; Determine a sixth ratio of the output horizontal effective pixels of the target chip output port to the number of rows; determining a seventh ratio of the third product to the sixth ratio; Dividing the target sub-data according to a fourth number of rows to obtain target divided data; determining a fifth number of minimum storage units included in the target partitioned data; determining a fourth product of the seventh ratio and the fifth amount; determining a target difference between the third quantity and the fourth product; Determining the sub-memory layout parameters includes selecting the third number of the minimum storage units in the memory of the target chip to write the target sub-data, and selecting the minimum storage unit of the target difference value in the memory of the target chip not to write data.

6. The method according to claim 2, characterized in that Determining a first pixel clock at which the target chip output port outputs the target sub-data includes: Determining a target pixel clock of the target chip; determining an eighth ratio of the target pixel clock to the first number; The eighth ratio is determined as the first pixel clock.

7. The method according to claim 1, characterized in that Determining the output resolution of each of the first output ports includes: Receive resolution setting instructions; The output resolution of each of the first output ports is determined based on the resolution setting instruction.

8. A data output method, applied to an output chip, characterized in that: include: Receive target memory layout parameters and target data sent by a target chip, wherein the target memory layout parameters are obtained by the target chip in the following manner: perform the following operations for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determine a first number of first output ports included in an output chip connected to the target chip output port, determine an output resolution of each of the first output ports, and determine the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution; Splitting the target data according to the target memory layout parameter to obtain the first number of split data; Controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different; The target chip determines the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution in the following manner: dividing the target data according to the first number to obtain the sub-data of the first number; performing the following operations for each target sub-data included in the sub-data to determine the sub-memory layout parameters for writing the target sub-data in the target chip: determining a second output port included in the first output port for outputting the target sub-data, determining a target output resolution of the second output port included in the output resolution, determining the row effective pixels of the output data of the target chip output port as the first row effective pixels, and setting the row effective pixels of the output data of the second output port to the first row effective pixels. The row effective pixels are determined to be valid for the second row, and the rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port is determined based on the first row effective pixels and the second row effective pixels, and the number of row effective pixels output by the second output port accounts for the total number of pixels of the target sub-data is determined based on the rate ratio, and the third number of minimum storage units for storing the target sub-data is determined based on the total number of pixels, and the sub-memory layout parameters are determined based on the third number, wherein the size of the minimum storage unit is the same as the size of the cache line of the memory of the target chip; the sub-memory layout parameters of all the target sub-data are determined as the target memory layout parameters.

9. The method according to claim 8, characterized in that Controlling each of the first output ports to output one of the split data includes: Determining split valid data from the split data based on the output resolution; The split valid data is output according to the detailed timing of the data output received in advance.

10. The method according to claim 8, characterized in that After controlling each of the first output ports to output one of the split data, the method further includes: Determining a storage state of a first-in-first-out queue of a display queue for storing the split data; A pixel clock of the first output port is adjusted based on the storage state.

11. A data output device, applied to a target chip, characterized in that: include: The first output module is configured to perform the following operations for each target chip output port included in the target chip to determine the target memory layout parameters of the target data outputted through the target chip output port: determining a first number of first output ports included in the output chip connected to the target chip output port; determining an output resolution of each of the first output ports; Determining target memory layout parameters for writing target data in a memory of the target chip based on the first number and the output resolution; Sending the target memory layout parameter to the output chip to instruct the output chip to split the target data sent by the target chip according to the target memory layout parameter to obtain the first number of split data, and controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different; The first output module determines the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution in the following manner: dividing the target data according to the first number to obtain the sub-data of the first number; performing the following operations for each target sub-data included in the sub-data to determine the sub-memory layout parameters for writing the target sub-data in the target chip: determining a second output port included in the first output port for outputting the target sub-data, determining a target output resolution of the second output port included in the output resolution, determining the row effective pixels of the output data of the target chip output port as the first row effective pixels, and setting the second output port to output the data The valid pixels of the first row are determined as the second row valid, based on the first row valid pixels and the second row valid pixels, the rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port is determined, based on the rate ratio, the number of total pixels of the target sub-data accounted for by the valid pixels of the row output by the second output port is determined, based on the total number of pixels, a third number of minimum storage units for storing the target sub-data is determined, based on the third number, the sub-memory layout parameters are determined, wherein the size of the minimum storage unit is the same as the size of the cache line of the memory of the target chip; the sub-memory layout parameters of all the target sub-data are determined as the target memory layout parameters.

12. A data output device, applied to an output chip, characterized in that: include: A receiving module, configured to receive target memory layout parameters and target data sent by a target chip, wherein the target memory layout parameters are obtained by the target chip in the following manner: performing the following operations for each target chip output port included in the target chip to determine the target memory layout parameters of the target data output through the target chip output port: determining a first number of first output ports included in an output chip connected to the target chip output port, determining an output resolution of each of the first output ports, and determining the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution; a splitting module, configured to split the target data according to the target memory layout parameter to obtain the first number of split data; A second output module, used for controlling each of the first output ports to output one of the split data, wherein the data output by each of the first output ports is different; The target chip determines the target memory layout parameters for writing the target data in the memory of the target chip based on the first number and the output resolution in the following manner: dividing the target data according to the first number to obtain the sub-data of the first number; performing the following operations for each target sub-data included in the sub-data to determine the sub-memory layout parameters for writing the target sub-data in the target chip: determining a second output port included in the first output port for outputting the target sub-data, determining a target output resolution of the second output port included in the output resolution, determining the row effective pixels of the output data of the target chip output port as the first row effective pixels, and setting the row effective pixels of the output data of the second output port to the first row effective pixels. The row effective pixels are determined to be valid for the second row, and the rate ratio of a valid pixel of the target sub-data output by the target chip to a valid pixel of the split data output by the second output port is determined based on the first row effective pixels and the second row effective pixels, and the number of row effective pixels output by the second output port accounts for the total number of pixels of the target sub-data is determined based on the rate ratio, and the third number of minimum storage units for storing the target sub-data is determined based on the total number of pixels, and the sub-memory layout parameters are determined based on the third number, wherein the size of the minimum storage unit is the same as the size of the cache line of the memory of the target chip; the sub-memory layout parameters of all the target sub-data are determined as the target memory layout parameters.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 7, or execute the method described in any one of claims 8 to 10 when running.

14. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of claims 1 to 7, or to execute the method described in any one of claims 8 to 10.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the method described in any one of claims 1 to 7, or executes the steps of the method described in any one of claims 8 to 10.

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