Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a drift layer, a P-type modulation layer, a current blocking layer, a channel layer, a barrier layer, a first trench, a PGaN active layer, a gate, a source, and a drain. The P-type modulation layer is provided on the central region of one surface of the drift layer; the current blocking layer is located on the periphery of the P-type modulation layer; the channel layer is located on the side of the P-type modulation layer and the current blocking layer facing away from the drift layer, and the channel layer covers the P-type modulation layer and part of the current blocking layer; the first trench penetrates the channel layer and the P-type modulation layer; the barrier layer is located on the side of the channel layer facing away from the drift layer and in the first trench, and the barrier layer located on the side of the channel layer facing away from the drift layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the first trench; the gate is located on the side of the PGaN active layer facing away from the drift layer; the source is located at least on the side of the current blocking layer facing away from the drift layer and is in contact with the heterojunction structure.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof. Background Art

[0002] GaN material has a wider bandgap, allowing for smaller devices while maintaining the same breakdown voltage, leading to its increasing application in semiconductor devices. However, mainstream GaN device production still uses planar structures, where the gate and drain are located at roughly the same height across the thickness of the semiconductor device, significantly wasting device area. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present invention, there is provided a semiconductor device, including:

[0004] drift layer;

[0005] A P-type modulation layer is provided on a central region of one side surface of the drift layer in the thickness direction of the semiconductor device;

[0006] a current blocking layer, disposed on the same side surface of the drift layer as the P-type modulation layer and located at the periphery of the P-type modulation layer;

[0007] a channel layer located on a side of the P-type modulation layer and the current blocking layer facing away from the drift layer, and the channel layer covers the P-type modulation layer and a portion of the current blocking layer adjacent to the P-type modulation layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer;

[0008] a first trench penetrating the channel layer and the P-type modulation layer in a thickness direction of the semiconductor device;

[0009] a barrier layer, located on a side of the channel layer facing away from the drift layer and in the first trench and in contact with the barrier layer, wherein the barrier layer located on a side of the channel layer facing away from the drift layer forms a heterojunction structure with the channel layer;

[0010] A PGaN active layer is located in the first trench;

[0011] a gate, located on a side of the PGaN active layer facing away from the drift layer;

[0012] a source electrode, at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure;

[0013] The drain is located on a side of the drift layer away from the heterojunction structure.

[0014] In some embodiments, in a thickness direction of the semiconductor device, a bottom wall of the first trench is higher than a bottom surface of the current blocking layer on a side facing the drift layer.

[0015] In some embodiments, the top surface of the current blocking layer facing away from the drift layer is flush with the top surface of the P-type modulation layer facing away from the drift layer, or the top surface of the current blocking layer facing away from the drift layer is higher than the top surface of the P-type modulation layer facing away from the drift layer.

[0016] In some embodiments, the semiconductor device is a PGaN structure GaN power device, and the gate is a Schottky metal; and / or,

[0017] The material of the current blocking layer is P-type gallium nitride.

[0018] In some embodiments, the semiconductor device further comprises:

[0019] a passivation layer, the passivation layer being located on a side of the gate and the barrier layer facing away from the drift layer;

[0020] The source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

[0021] According to a second aspect of an embodiment of the present invention, there is provided a semiconductor device, comprising:

[0022] drift layer;

[0023] a current blocking layer provided in a peripheral region of a surface of the drift layer on one side in a thickness direction of the semiconductor device, wherein a middle region of the surface of the drift layer where the current blocking layer is provided is exposed from the middle of the current blocking layer;

[0024] a channel layer located on the same side of the drift layer and the current blocking layer, and the channel layer covers the drift layer exposed from the middle of the current blocking layer and a partial width of the current blocking layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer;

[0025] a second trench penetrating the channel layer in a thickness direction of the semiconductor device;

[0026] a barrier layer, located on a side of the channel layer facing away from the drift layer and in the second trench, wherein the barrier layer located on the side of the channel layer facing away from the drift layer forms a heterojunction structure with the channel layer;

[0027] a PGaN active layer located in the second trench and in contact with the barrier layer;

[0028] The gate is located on the side of the PGaN active layer away from the drift layer

[0029] a gate, located on a side of the PGaN active layer facing away from the drift layer;

[0030] a source electrode, at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure;

[0031] The drain is located on a side of the drift layer away from the heterojunction structure.

[0032] In some embodiments, in the thickness direction of the semiconductor device, the bottom wall of the second trench is higher than the bottom surface of the current blocking layer on the side facing the drift layer; and / or,

[0033] The semiconductor device is a PGaN structure GaN power device, and the gate is a Schottky metal; and / or,

[0034] The material of the current blocking layer is P-type gallium nitride; and / or,

[0035] The semiconductor device further includes a passivation layer, wherein the passivation layer is located on a side of the gate and the barrier layer away from the drift layer;

[0036] The source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

[0037] According to a third aspect of an embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0038] providing a substrate, and forming a drift layer on one side of the substrate;

[0039] forming a P-type modulation layer in a middle region of a surface of the drift layer facing away from the substrate;

[0040] forming a current blocking layer on a surface of the drift layer facing away from the substrate and located outside the P-type modulation layer;

[0041] A channel layer, a first trench, a barrier layer, a PGaN active layer and a gate are formed on the side of the P-type modulation layer and the current blocking layer away from the drift layer; the channel layer covers the P-type modulation layer and a portion of the current blocking layer close to the P-type modulation layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; the first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device; the barrier layer is located on the side of the channel layer away from the drift layer and in the first trench, and the barrier layer located on the side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the first trench and in contact with the barrier layer; the gate is located on the side of the PGaN active layer away from the drift layer;

[0042] forming a source electrode, wherein the source electrode is at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure;

[0043] The substrate is removed and a drain is formed. The drain is located on a side of the drift layer away from the heterojunction structure.

[0044] In some embodiments, after providing a substrate and before forming a drift layer on one side of the substrate, the method includes:

[0045] forming a nucleation layer and a buffer layer on one side of the substrate, wherein the nucleation layer is an AlN layer, and the buffer layer comprises an AlGaN layer, a staggered multi-layer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer;

[0046] The forming of a drift layer on one side of the substrate comprises:

[0047] A drift layer is formed on a side of the buffer layer facing away from the substrate.

[0048] In some embodiments, when or after removing the substrate and before forming the drain, the method further includes:

[0049] removing the nucleation layer; or,

[0050] The nucleation layer and at least a portion of the buffer layer are removed.

[0051] In some embodiments, before forming the source, the method further includes:

[0052] forming a passivation layer, wherein the passivation layer is located on a side of the gate and the barrier layer facing away from the drift layer;

[0053] After the source electrode is formed, the source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

[0054] According to a fourth aspect of an embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0055] providing a substrate, and forming a drift layer on one side of the substrate;

[0056] forming a current blocking layer in a peripheral region of a surface of the drift layer on one side in a thickness direction of the semiconductor device; a middle region of the surface of the drift layer where the current blocking layer is provided is exposed from the middle of the current blocking layer;

[0057] A channel layer, a second trench, a barrier layer, a PGaN active layer and a gate are formed on the same side of the drift layer and the current blocking layer, wherein the channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; the second trench penetrates the channel layer in the thickness direction of the semiconductor device; the barrier layer is located on a side of the channel layer away from the drift layer and in the second trench, and the barrier layer located on the side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the second trench; and the gate is located on a side of the PGaN active layer away from the drift layer;

[0058] forming a source electrode, wherein the source electrode is at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure;

[0059] The substrate is removed and a drain is formed. The drain is located on a side of the drift layer away from the heterojunction structure.

[0060] In some embodiments, after providing a substrate and before forming a drift layer on one side of the substrate, the method includes:

[0061] forming a nucleation layer and a buffer layer on one side of the substrate, wherein the nucleation layer is an AlN layer, and the buffer layer comprises an AlGaN layer, a staggered multi-layer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer;

[0062] The forming of a drift layer on one side of the substrate comprises:

[0063] forming a drift layer on a side of the buffer layer facing away from the substrate;

[0064] When or after removing the substrate and before forming the drain, the method further includes:

[0065] removing the nucleation layer; or,

[0066] The nucleation layer and at least a portion of the buffer layer are removed.

[0067] In some embodiments, before forming the source, the method further includes:

[0068] forming a passivation layer, wherein the passivation layer is located on a side of the gate and the barrier layer facing away from the drift layer;

[0069] After the source electrode is formed, the source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

[0070] The main technical effects achieved by the embodiments of the present application are:

[0071] The semiconductor device and its preparation method provided in the embodiments of the present application configure the semiconductor device as a vertical structure, which is beneficial for controlling the volume of the device in which the semiconductor device is located. The blocking effect of the current blocking layer below the source electrode can reduce the turn-off leakage, thereby achieving better reliability and lower power consumption. The provision of a PGaN active layer below the gate can increase the height of the barrier layer, raising the potential energy in the trench below the gate to above the Fermi level. A high electron potential barrier will be formed at the interface between the drift layer and the barrier layer, better confining electrons in the 2DEG channel and improving electron mobility. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 A top view of a semiconductor device provided by one embodiment of the present invention;

[0073] Figure 2 For the Figure 1 A sectional view taken along the section line AA';

[0074] Figure 3 A cross-sectional view of another semiconductor device provided by an embodiment of the present invention;

[0075] Figure 4 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present invention;

[0076] Figures 5 to 27 A structural diagram corresponding to some process steps in a process of preparing a semiconductor device according to a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0077] Figure 28A flow chart of another method for manufacturing a semiconductor device provided by one embodiment of the present invention;

[0078] Figure 29 and Figure 30 This is a structural diagram corresponding to some process steps in a process of preparing a semiconductor device according to a method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0079] The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device and the method for manufacturing the same in the present invention are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.

[0080] Please refer to Figure 1 and Figure 2 , and in combination with other drawings when necessary, an embodiment of the present application provides a semiconductor device, wherein the semiconductor device 100 includes a drift layer 10, a current blocking layer 20, a P-type modulation layer 30, a channel layer 41, a barrier layer 42, a first trench 101, a PGaN active layer 50, a gate 60, a source 80 and a drain 90.

[0081] The P-type modulation layer 30 is disposed on a central region of one side surface of the drift layer 10 in the thickness direction T of the semiconductor device.

[0082] The current blocking layer 20 and the P-type modulation layer 30 are disposed on the same side surface of the drift layer 10 and are located outside the P-type modulation layer 30 .

[0083] The channel layer 41 is located on the side of the P-type modulation layer 30 and the current blocking layer 20 away from the drift layer 10, and the channel layer 41 covers the P-type modulation layer 30 and the current blocking layer 20 of a portion of the width close to the P-type modulation layer 30; the current blocking layer 20 includes a first blocking portion 21 overlapping with the channel layer 41, and a second blocking portion 22 located outside the first blocking portion 21 and not overlapping with the channel layer 41. The so-called overlap refers to the overlap of the projection along the thickness direction. For example, Figure 2 As shown, the projection of the first barrier portion 21 along the thickness direction falls within the projection of the channel layer 41 along the thickness direction, while the projection of the second barrier portion 22 along the thickness direction falls outside the projection of the channel layer 41 along the thickness direction.

[0084] The first trench 101 penetrates the channel layer 41 and the P-type modulation layer 30 in the thickness direction T of the semiconductor device.

[0085] The barrier layer 42 is located on a side of the channel layer 41 away from the drift layer 10 and in the first trench 101 . A barrier layer portion 421 located on a side of the channel layer 41 away from the drift layer 10 forms a heterojunction structure 40 with the channel layer 41 .

[0086] The PGaN active layer 50 is located in the first trench 101 and contacts the barrier layer 42 ;

[0087] The gate 60 is located on a side of the PGaN active layer away from the drift layer.

[0088] The source electrode 80 is at least located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and in contact with the heterojunction structure 40 .

[0089] The drain electrode 90 is located on a side of the drift layer 10 facing away from the heterojunction structure 40 .

[0090] The semiconductor device 100 is configured as a vertical structure, which is beneficial for controlling the volume of the device in which the semiconductor device is located. The blocking effect of the current blocking layer 20 below the source 80 and the P-type modulation layer below the channel layer 41 can increase the device's saturated output current and reduce the off-state leakage, thereby achieving better reliability and lower power consumption. The provision of the PGaN active layer 50 below the gate 60 can increase the height of the barrier layer 42, raising the potential energy in the trench below the gate 60 to above the Fermi level. A high electron barrier is formed at the interface between the drift layer 10 and the barrier layer 42, better confining electrons within the 2DEG channel and improving electron mobility.

[0091] The drift layer 10 provides a path for conducting most of the current in the semiconductor device and mainly withstands the voltage when the device is in operation.

[0092] Because doping concentration directly affects the breakdown voltage and on-resistance of the semiconductor device, the inventors have discovered that, in some embodiments, the drift layer 10 can be formed using undoped or lightly doped (1e15-1e16 / cm⁻³) gallium nitride. When the drift layer 10 is lightly doped gallium nitride, the gallium nitride can be doped with N-type silicon.

[0093] Generally, as the thickness of the drift layer 10 increases, the breakdown voltage of the device in which the semiconductor device is located is higher, but the on-resistance will also increase. After research, the inventors found that the thickness range of the drift layer 10 can be set at 1μm-20μm. So that the drift layer 10 will not be easily broken down due to too small a thickness, nor will it cause excessive on-resistance due to too large a thickness. For example, the thickness of the drift layer 10 can be set to 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm...19μm, 20μm and other sizes within the range of 1μm-20μm. The specific thickness of the drift layer 10 can be determined according to the structure of the device in which the semiconductor device is located, the target breakdown voltage, and other conditions.

[0094] The current blocking layer 20 can prevent charge from passing through the source 80 and the drain 90, so that when the device in which the semiconductor device 100 is located is in operation, under the control of the gate 60, the current can better flow from the drain 90, the drift layer 10, and the heterojunction structure 40 to the source 80 in sequence.

[0095] In some embodiments, the current blocking layer 20 is made of p-type gallium nitride. The thickness of the current blocking layer 20 can be 200 nm to 600 nm. This ensures that the current blocking layer 20 blocks charge from passing between the source electrode 80 and the drain electrode 90 while being sufficiently thick that it affects device size and wastes material. For example, the thickness of the current blocking layer 20 can be 200 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, or any other thickness within the range of 200 nm to 600 nm.

[0096] It should be noted that, in some other embodiments, the material of the current blocking layer 20 may also be N-type gallium nitride.

[0097] The P-type modulation layer 30 can be used to adjust the electric field distribution in the drift layer 10 to optimize the device's breakdown voltage and current handling capability. The P-type modulation layer 30 creates a space charge region in the drift layer 10, smoothing the electric field distribution and reducing the local electric field strength, thereby increasing the device's breakdown voltage.

[0098] In some embodiments, the material of the P-type modulation layer 30 may be P-type gallium nitride. The P-type modulation layer 30 may be a doped modulation layer doped with a trivalent element, such as one or both of aluminum (Al) and boron (B), with a doping concentration of 1e16 / cm⁻³ to 1e17 / cm⁻³.

[0099] In some embodiments, the thickness of the P-type modulation layer 30 is in the range of 50 nm to 500 nm. For example, the thickness of the P-type modulation layer 30 can be 50 nm, 100 nm, 110 nm, 150 nm, 200 nm, 300 nm, ..., 500 nm, etc., within the range of 50 nm to 500 nm.

[0100] The channel layer 41 can transmit current from the drain to the source.

[0101] In some embodiments, the material of the channel layer 41 may be GaN without intentional doping.

[0102] In some embodiments, the channel layer 41 may have a thickness of 0.3 μm-1 μm. For example, the channel layer 41 may have a thickness within the range of 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1 μm.

[0103] In some embodiments, to facilitate the preparation of the first trench 101, the first trench 101 may penetrate a portion of the drift layer 10. Of course, in some other embodiments, the first trench may just penetrate to the top surface of the drift layer facing the channel layer.

[0104] The barrier layer portion 421 of the barrier layer 42, located on the side of the channel layer 41 facing away from the drift layer 10, forms a heterojunction structure with the channel layer 41. The spontaneous polarization effect and piezoelectric polarization effect of this heterojunction structure induce a built-in polarization electric field, thereby generating a high-density, high-mobility 2DEG. Another barrier layer portion 422 of the barrier layer 42, located in the first trench 101, can cover the sidewalls and bottom wall of the first trench 101.

[0105] In some embodiments, the barrier layer 42 is made of AlGaN.

[0106] In some embodiments, the barrier layer 42 may have a thickness ranging from 20 nm to 30 nm. For example, the barrier layer 42 may have a thickness of 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, or the like.

[0107] In some embodiments, the PGaN active layer 50 is made of p-type gallium nitride. The thickness of the PGaN active layer 50 can be 200 nm to 600 nm. For example, the thickness of the current blocking layer 20 can be 200 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, or any other thickness within the range of 200 nm to 600 nm.

[0108] In some embodiments, the gate 60 is a Schottky metal, such as platinum or nickel. The semiconductor device is a PGaN structured GaN power device. The PGaN active layer below the gate 60 increases the height of the barrier layer, raising the potential energy in the trench below the gate to above the Fermi level. A high electron barrier is formed at the interface between the drift layer and the barrier layer, better confining electrons within the 2DEG channel and improving electron mobility.

[0109] The source electrode 80 is an ohmic metal, and can be a stacked structure layer consisting of Ti, Al, Ni, and Ag layers stacked in sequence.

[0110] The drain electrode 90 is made of a metal material, such as one or more of Ti, Ni, and Ag. If the drain electrode 90 is made of multiple metal materials, the drain electrode 90 may be a stacked structure layer composed of multiple different metal material layers.

[0111] In some embodiments, in the thickness direction T of the semiconductor device, the bottom wall 1011 of the first trench 101 is higher than the bottom surface 2001 of the current blocking layer 20 facing the drift layer 10, so that the current blocking layer 20 can balance the charge at the lower corner of the gate 60, so that the electric field distribution at the lower corner of the gate 60 is more uniform, thereby improving device performance.

[0112] In some embodiments, a top surface 2002 of the current blocking layer 20 facing away from the drift layer 10 is flush with a top surface 3001 of the P-type modulation layer 30 facing away from the drift layer 10 .

[0113] In some other embodiments, a top surface 2002 of the current blocking layer 20 facing away from the drift layer 10 is higher than a top surface 3001 of the P-type modulation layer 30 facing away from the drift layer 10 .

[0114] In some embodiments, the semiconductor device 100 further includes a passivation layer 70. The passivation layer 70 is located on a side of the gate 60 and the barrier layer 42 facing away from the drift layer 10. Specifically, the passivation layer 70 is located on a side of the gate 60 and the barrier layer portion 421 facing away from the drift layer 10.

[0115] The passivation layer 70 may be made of silicon nitride. The thickness of the passivation layer 70 may be 0.1 μm to 1.5 μm. For example, the thickness of the passivation layer 70 may be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, etc.

[0116] Accordingly, if Figure 2 As shown, the source electrode 80 may be located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on a side of the passivation layer 70 away from the drift layer 10 .

[0117] In some other embodiments, the source electrode 80 may also be located only on the side of the second blocking portion 22 of the current blocking layer 20 facing away from the drift layer 10 .

[0118] In some embodiments, a buffer layer may be included between the drift layer 10 and the drain 90. For example, the buffer layer may include a low-temperature GaN layer 110 and a high-temperature GaN layer 120. Of course, in other embodiments, the buffer layer may include only one gallium nitride layer, such as only the high-temperature GaN layer 120. Alternatively, in other embodiments, the drift layer 10 is in direct contact with the drain 90 without a buffer layer interposed therebetween.

[0119] like Figure 3 As shown, the present application further provides a semiconductor device 100 ′, which includes a drift layer 10 , a current blocking layer 20 , a channel layer 41 , a barrier layer 42 , a first trench 101 , a PGaN active layer 50 , a gate 60 , a source 80 , and a drain 90 .

[0120] The current blocking layer 20 is provided in the peripheral area of ​​the surface of the drift layer 10 on one side in the thickness direction T of the semiconductor device. The middle area of ​​the surface of the drift layer 10 where the current blocking layer 20 is provided is exposed from the middle of the current blocking layer 20 .

[0121] The channel layer 41 is located on the same side of the drift layer 10 and the current blocking layer 20, and the channel layer 41 covers the drift layer 10 exposed from the middle of the current blocking layer 20 and a partial width of the current blocking layer 20; the current blocking layer 20 includes a first blocking portion 21 overlapping with the channel layer 41, and a second blocking portion 22 located outside the first blocking portion 21 and not overlapping with the channel layer 41.

[0122] The second trench 201 penetrates the channel layer 41 in the thickness direction T of the semiconductor device.

[0123] The barrier layer 42 is located on a side of the channel layer 41 away from the drift layer 10 and in the second trench 201 . The barrier layer portion 421 located on a side of the channel layer 41 away from the drift layer 10 forms a heterojunction structure 40 with the channel layer 41 .

[0124] The PGaN active layer 50 is located in the second trench 201 and contacts the barrier layer 42 .

[0125] The gate 60 is located on a side of the PGaN active layer away from the drift layer.

[0126] The source electrode 80 is at least located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and in contact with the heterojunction structure 40 .

[0127] The drain electrode 90 is located on a side of the drift layer 10 facing away from the heterojunction structure 40 .

[0128] The semiconductor device 100' utilizes a vertical structure, which helps control the device volume. Furthermore, the blocking effect of the current blocking layer below the source reduces off-state leakage, thereby achieving improved reliability and lower power consumption. The PGaN active layer below the gate increases the barrier layer height, raising the potential energy in the trench below the gate above the Fermi level. A high electron barrier forms at the interface between the drift layer and the barrier layer, better confining electrons within the 2DEG channel and improving electron mobility.

[0129] In some embodiments, in the thickness direction T of the semiconductor device, a bottom surface of the gate 60 facing the drift layer 10 is higher than a bottom surface of the current blocking layer 20 facing the drift layer 10 .

[0130] In some embodiments, the gate 60 is a Schottky metal. The semiconductor device is a PGaN structure GaN power device.

[0131] The setting of the PGaN active layer below the gate 60 can increase the height of the barrier layer and raise the potential energy in the groove below the gate to above the Fermi level. A high electron potential barrier will be formed at the interface between the drift layer and the barrier layer, which will better confine the electrons in the 2DEG channel and improve the electron mobility.

[0132] The source electrode 80 is an ohmic metal, and can be a stacked structure layer consisting of Ti, Al, Ni, and Ag layers stacked in sequence.

[0133] The drain electrode 90 is made of metal.

[0134] In some embodiments, the current blocking layer 20 is made of P-type gallium nitride.

[0135] In some embodiments, the semiconductor device further includes a passivation layer 70, which is located on a side of the gate 60 and the barrier layer 42 facing away from the drift layer 10. Specifically, the passivation layer 70 is located on a side of the gate 60 and the barrier layer portion 421 facing away from the drift layer 10.

[0136] Accordingly, if Figure 3As shown, the source electrode 80 is located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on a side of the passivation layer 70 away from the drift layer 10 .

[0137] In some other embodiments, the source electrode 80 may also be located only on the side of the second blocking portion 22 of the current blocking layer 20 facing away from the drift layer 10 .

[0138] In some embodiments, a buffer layer may be included between the drift layer 10 and the drain 90. For example, the buffer layer may include a low-temperature GaN layer 110 and a high-temperature GaN layer 120. Of course, in other embodiments, the buffer layer may include only one gallium nitride layer, such as only the high-temperature GaN layer 120. Alternatively, in other embodiments, the drift layer 10 is in direct contact with the drain 90 without a buffer layer interposed therebetween.

[0139] It should be noted that, in some embodiments, to facilitate the preparation of the second trench 201, the second trench 201 may penetrate a portion of the drift layer 10. Of course, in other embodiments, the second trench may just penetrate to the top surface of the drift layer facing the channel layer.

[0140] The semiconductor device 100' is different from the above-mentioned semiconductor device 100 in that the semiconductor device 100' does not include the P-type modulation layer 30. For other identical and similar structures, the identical and similar points can be referred to the above-mentioned related descriptions and will not be repeated here.

[0141] It should be noted that the semiconductor devices 100 and 100' described herein do not include a separate substrate layer. The drift layer 10 not only serves as the device's drift layer but also provides support for the semiconductor devices 100 and 100'. Compared to semiconductor devices using a separate substrate, this facilitates controlling the thickness of the semiconductor devices 100 and 100', reduces device resistance, and facilitates heat dissipation.

[0142] It should also be noted that in the semiconductor devices 100 and 100', the source electrode 80 may be in direct contact with the current blocking layer 20, or may be separated by a portion of the channel layer. Direct contact between the source electrode 80 and the current blocking layer 20 is more conducive to improving the current blocking effect of the current blocking layer 20.

[0143] like Figure 4 As shown, the present application further provides a method for preparing a semiconductor device, which includes the following steps S110 to S160:

[0144] In step S110, a substrate is provided, and a drift layer is formed on one side of the substrate;

[0145] In step S120, a P-type modulation layer is formed in a central region of a surface of the drift layer facing away from the substrate;

[0146] In step S130, a current blocking layer is formed on a surface of the drift layer facing away from the substrate and is located outside the P-type modulation layer.

[0147] In step S140, a channel layer, a second trench, a barrier layer, a PGaN active layer, and a gate are formed on the side of the P-type modulation layer and the current blocking layer facing away from the drift layer; the channel layer covers the P-type modulation layer and a portion of the current blocking layer close to the P-type modulation layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; the first trench penetrates the channel layer and the P-type modulation layer in the direction of the semiconductor thickness; the barrier layer is located on the side of the channel layer facing away from the drift layer and in the first trench, and the barrier layer located on the side of the channel layer facing away from the drift layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the first trench and in contact with the barrier layer; and the gate is located on the side of the PGaN active layer facing away from the drift layer;

[0148] In step S150, a source electrode is formed, wherein the source electrode is at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure;

[0149] In step S160 , the substrate is removed and a drain is formed. The drain is located on a side of the drift layer away from the heterojunction structure.

[0150] The method for manufacturing the semiconductor device can be used to manufacture the semiconductor device 100 or similar semiconductor devices as described above. Figures 5 to 27 The preparation method of the semiconductor device is described in detail.

[0151] like Figures 5 to 12 In step S110 , a substrate 200 is provided, and a drift layer 10 is formed on one side of the substrate 200 .

[0152] like Figure 5 and Figure 6 As shown, a substrate 200 is provided. The substrate 200 may be diamond.

[0153] Of course, in some other embodiments, the substrate may also be a silicon substrate, a sapphire substrate, etc.

[0154] If the substrate 200 is made of diamond, before forming the drift layer 10 on one side of the substrate 200, the method may further include forming a nucleation layer 210 and a buffer layer on one side of the substrate 200. The nucleation layer 210 is an AlN layer. The buffer layer includes a first buffer layer 220, a second buffer layer 230, a third buffer layer 110, and a fourth buffer layer 120 sequentially stacked on the nucleation layer 210. The first buffer layer 220 may be an AlGaN layer. The second buffer layer 230 may be a staggered stack of multiple AlN / GaN layers. The third buffer layer 110 may be a low-temperature GaN layer. The fourth buffer layer 120 may be a high-temperature GaN layer.

[0155] like Figure 7 As shown, a nucleation layer 210 is formed on one side of substrate 200 to reduce the lattice mismatch between the substrate and the subsequent GaN layer. This nucleation layer 210 can be formed using an epitaxial growth process. The thickness of nucleation layer 210 can be 10 nm to 30 nm, for example, 10 nm, 13 nm, 15 nm, 18 nm, or 20 nm.

[0156] like Figure 8 As shown, a first buffer layer 220 is formed on the side of the nucleation layer 210 facing away from the substrate 200 to further reduce the lattice mismatch between the substrate and the subsequent GaN layer. The thickness of the first buffer layer 220 is 0.1μm-0.2μm. For example, 0.1μm, 0.12μm, 0.15μm, 0.16μm, 0.18μm, 0.2μm, etc.

[0157] like Figure 9 As shown, a second buffer layer 230 is formed on the side of the first buffer layer 220 facing away from the substrate 200. The second buffer layer 230 is a staggered stack of multiple AlN / GaN layers. The multi-layer alternating stress field reduces dislocation density, making the semiconductor layer structure, such as the subsequently provided drift layer 10, more flat and uniform. The specific number of layers of the second buffer layer 230 can be determined according to the specific situation, such as 10 pairs of AlN / GaN layers, 20 pairs of AlN / GaN layers, or other multiple AlN / GaN layers. The thickness of each AlN layer or GaN layer can be several nanometers, such as 2 nm.

[0158] like Figure 10 As shown, a third buffer layer 110 is formed on the side of the second buffer layer 230 facing away from the substrate 200 to improve the adhesion quality and growth rate of subsequent layer structures. The third buffer layer 110 can be formed using an epitaxial growth process. Its thickness can be 100nm-300nm, for example, 100nm, 150nm, 180nm, 200nm, 250nm, or 300nm.

[0159] like Figure 11As shown, a fourth buffer layer 120 is formed on the side of the third buffer layer 110 facing away from the substrate 200, serving as the foundation for the drift layer in subsequent device fabrication. The fourth buffer layer 120 can be formed using an epitaxial growth process. The thickness of the fourth buffer layer 120 can be 1 μm to 2 μm, such as 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, or 2 μm.

[0160] like Figure 12 As shown, forming the drift layer 10 on one side of the substrate 200 includes: forming the drift layer 10 on a side of the buffer layer away from the substrate 200. The drift layer 10 can be formed by an epitaxial growth process.

[0161] The thickness of the drift layer 10 can be set in the range of 1μm-20μm. This ensures that the drift layer 10 is not easily broken down due to a too small thickness, nor does it cause excessive on-resistance due to a too large thickness. For example, the thickness of the drift layer 10 can be set to 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm...19μm, 20μm, etc., within the range of 1μm-20μm. The specific thickness of the drift layer 10 can be determined according to the structure of the semiconductor device, the target breakdown voltage, and other conditions.

[0162] like Figures 13 to 15 In step S120 , a P-type modulation layer 30 is formed in the middle region of the surface of the drift layer 10 facing away from the substrate 200 .

[0163] like Figure 13 As shown, when forming the P-type modulation layer 30 , a P-type modulation material layer 301 may be firstly laid on the entire surface of the drift layer 10 facing away from the substrate 200 .

[0164] like Figure 14 and Figure 15 Then, using the patterned photoresist 240 as a mask, a plasma etching process is used to etch away the P-type modulation material layer 301 at the edge, forming a P-type modulation layer 30 at the center. After the P-type modulation material layer 301 at the edge is etched away, a trench 102 at the edge can be formed. The depth of the trench 102 can be 200 nm to 600 nm, for example, 500 nm.

[0165] like Figure 16 In step S130 , a current blocking layer 20 is formed on a surface of the drift layer 10 facing away from the substrate 200 and located outside the P-type modulation layer 30 .

[0166] The current blocking layer 20 may be formed in the trench 102 by metal organic chemical vapor deposition (MOCVD).

[0167] like Figures 17 to 25 In step S140, a channel layer 41, a first trench 101, a barrier layer 42, a PGaN active layer 50, and a gate 60 are formed on the side of the P-type modulation layer 30 and the current blocking layer 20 facing away from the drift layer. The channel layer 41 covers the P-type modulation layer and a portion of the current blocking layer adjacent to the P-type modulation layer. The current blocking layer includes a first blocking portion overlapping the channel layer and a second blocking portion located outside the first blocking portion and not overlapping the channel layer. The first trench penetrates the channel layer and the P-type modulation layer in the thickness direction of the semiconductor device. A barrier layer 42 is located on the side of the channel layer 41 facing away from the drift layer 10 and in the first trench 101. The barrier layer 42 on the side of the channel layer 41 facing away from the drift layer 10 forms a heterojunction structure 40 with the channel layer 41. A PGaN active layer 50 is located in the first trench 101 and contacts the barrier layer 42. A gate 60 is located on the side of the PGaN active layer 50 facing away from the drift layer 10.

[0168] like Figure 17 As shown, a channel material layer 410 is formed on a side of the P-type modulation layer 30 and the current blocking layer 20 away from the drift layer.

[0169] like Figure 18 and Figure 19 As shown, next, a first trench 101 is formed, and the first trench 101 penetrates the channel material layer 410 and the P-type modulation layer 30 in the thickness direction of the semiconductor device.

[0170] The patterned photoresist 250 may be used as a mask layer, and a plasma etching process may be adopted to etch away the middle portion of the P-type modulation layer 30 and the channel material layer 410 to form the first trench 101 .

[0171] In some embodiments, to facilitate the preparation of the first trench 101, a portion of the drift layer 10 may be etched away when forming the first trench 101. Accordingly, the first trench 101 penetrates a portion of the drift layer 10. Of course, in other embodiments, when forming the first trench, the etching may be performed just to the top surface of the drift layer facing the channel layer. Accordingly, the first trench may be just penetrated to the top surface of the drift layer facing the channel layer.

[0172] like Figure 20 As shown, subsequently, a barrier material layer 420 is formed on the entire side of the channel material layer 410 away from the drift layer and in the first trench 101 .

[0173] like Figure 21As shown, subsequently, the first trench 101 is filled with a PGaN active layer material to form a PGaN active layer 50 . The PGaN active layer 50 is in contact with the barrier layer 42 .

[0174] like Figure 22 As shown, next, a gate 60 is formed on a side of the PGaN active layer 50 facing away from the drift layer 10 .

[0175] like Figure 23 As shown, a passivation material layer 701 is subsequently formed on the side of the gate 60 and the barrier layer 42 (specifically, the barrier layer portion 421 ) facing away from the drift layer 10 .

[0176] The passivation material layer 701 may be made of silicon nitride and may have a thickness of 0.5 μm to 1.5 μm.

[0177] like Figure 24 and Figure 25 As shown, the patterned photoresist 260 is then used as a mask layer, and a plasma etching process is adopted to etch away the edge areas of the channel material layer 410, the barrier material layer 420 and the passivation material layer 701 to form a channel layer 41, a barrier layer 42 and a passivation layer 70, as well as a groove 103 located outside the channel layer 41, the barrier layer 42 and the passivation layer 70.

[0178] like Figure 26 As shown, in step S150 , a source electrode 80 is formed. The source electrode 80 is at least located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and in contact with the heterojunction structure 40 .

[0179] The source electrode 80 is an ohmic metal and can be a stacked structure formed by sequentially depositing Ti, Al, Ni, and Ag layers using a deposition process.

[0180] like Figure 26 As shown, after the source electrode 80 is formed, the source electrode 80 is located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and on a side of the passivation layer 70 away from the drift layer 10 .

[0181] In some other embodiments, the source may also be located only on a side of the second barrier portion away from the drift layer.

[0182] like Figure 27 As shown, in step S160 , the substrate 200 is removed and a drain 90 is formed. The drain 90 is located on a side of the drift layer 10 away from the heterojunction structure 40 .

[0183] In some embodiments, when or after removing the substrate 200, before forming the drain 90, the nucleation layer 210 and part of the buffer layer may be removed, such as removing the first buffer layer 220 and the second buffer layer 230, to form a drain electrode 90. Figure 27 The semiconductor device 100 includes the third buffer layer 110 and the fourth buffer layer 120 .

[0184] In other embodiments, when or after removing the substrate 200 and before forming the drain 90, all buffer layers and the nucleation layer 210 may be removed, or only the nucleation layer 210 may be removed while retaining all buffer layers. The nucleation layer and other parts of the buffer layers may also be removed, such as removing the nucleation layer 210 and the first buffer layer 220.

[0185] like Figure 28 As shown, the present application further provides a method for preparing a semiconductor device, which includes the following steps S210 to S250:

[0186] In step S210, a substrate is provided, and a drift layer is formed on one side of the substrate;

[0187] In step S220, a current blocking layer is formed in a peripheral region of a surface of the drift layer on one side in a thickness direction of the semiconductor device; a central region of the surface of the drift layer where the current blocking layer is provided is exposed from the central portion of the current blocking layer;

[0188] In step S230, a channel layer, a second trench, a barrier layer, a PGaN active layer and a gate are provided on the same side of the drift layer and the current blocking layer, wherein the channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; the second trench penetrates the channel layer in the thickness direction of the semiconductor device; the gate is located in the second trench; the barrier layer is located on a side of the channel layer away from the drift layer and in the second trench, and the barrier layer located on the side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; the PGaN active layer is located in the second trench and in contact with the barrier layer; and the gate is located on a side of the PGaN active layer away from the drift layer.

[0189] In step S240, a source electrode is formed, wherein the source electrode is at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure;

[0190] In step S250 , the substrate is removed and a drain is formed. The drain is located on a side of the drift layer away from the heterojunction structure.

[0191] The semiconductor preparation method can be used to prepare Figure 3 The semiconductor device 100' and similar semiconductor devices shown in FIG. Figure 29 and Figure 30 and other drawings illustrate the semiconductor manufacturing method.

[0192] In step S210, Figures 5 to 11 as well as Figure 29 As shown, a substrate 200 is provided, and a drift layer 10 is formed on one side of the substrate 200 .

[0193] In some embodiments, after providing the substrate 200 and before forming the drift layer 10 on one side of the substrate 200 , the method includes:

[0194] A nucleation layer 210 and a buffer layer are formed on one side of the substrate 200. The nucleation layer is an AlN layer. The buffer layer includes an AlGaN layer, an alternating multi-layer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer.

[0195] Combine Figure 29 As shown, forming the drift layer 10 on one side of the substrate 200 includes:

[0196] A drift layer 10 is formed on the side of the buffer layer facing away from the substrate 200, as shown in FIG. Figure 29 The intermediate structure shown.

[0197] like Figure 30 As shown, in step S220, a current blocking layer 20 is formed in the peripheral area of ​​the surface of the drift layer 10 on one side in the thickness direction T of the semiconductor device; the middle area of ​​the surface of the drift layer 10 where the current blocking layer 20 is provided is exposed from the middle of the current blocking layer 20.

[0198] In step S230, a channel layer 41, a second trench 201, a barrier layer 42, a PGaN active layer 50, and a gate 60 are formed on the same side of the drift layer 10 and the current blocking layer 20. The channel layer 41 covers the portion of the drift layer 10 exposed from the center of the current blocking layer 20 and a portion of the width of the current blocking layer 20. The current blocking layer 20 includes a first blocking portion 21 overlapping with the channel layer 41 and a second blocking portion 22 located outside the first blocking portion 21 and not overlapping with the channel layer 41. The second trench 201 penetrates the channel layer 41 in the thickness direction T of the semiconductor device; the gate 60 is located in the second trench 201. A barrier layer is located on a side of the channel layer away from the drift layer and in the second trench, and the barrier layer located on the side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; a PGaN active layer is located in the second trench and in contact with the barrier layer; and a gate is located on a side of the PGaN active layer away from the drift layer.

[0199] It should be noted that, in some embodiments, to facilitate the preparation of the second trench 201, a portion of the drift layer 10 may be etched away when forming the second trench 201. Accordingly, the second trench 201 penetrates a portion of the drift layer 10. Of course, in other embodiments, when forming the second trench, the etching may be performed just to the top surface of the drift layer facing the channel layer. Accordingly, the second trench may be just penetrated to the top surface of the drift layer facing the channel layer.

[0200] In step S240 , a source electrode 80 is formed. The source electrode 80 is at least located on a side of the second blocking portion 22 of the current blocking layer 20 away from the drift layer 10 and in contact with the heterojunction structure 40 .

[0201] In some embodiments, before forming the source 80, the method further includes:

[0202] A passivation layer 70 is formed. The passivation layer 70 is located on a side of the gate 60 and the barrier layer 42 facing away from the drift layer 10 .

[0203] After the source electrode 80 is formed, the source electrode 80 is located on a side of the second blocking portion 22 of the current blocking layer 20 facing away from the drift layer 10 and on a side of the passivation layer 70 facing away from the drift layer 10 .

[0204] In some other embodiments, the source may also be located only on a side of the second barrier portion away from the drift layer.

[0205] In step S250 , the substrate 200 is removed and a drain electrode 90 is formed. The drain electrode 90 is located on a side of the drift layer 10 away from the heterojunction structure 40 .

[0206] In some embodiments, when or after removing the substrate 200, before forming the drain 90, the nucleation layer 210 and part of the buffer layer may be removed, such as removing the first buffer layer 220 and the second buffer layer 230, to form a drain electrode 90. Figure 30 The semiconductor device 100 ′ includes the third buffer layer 110 and the fourth buffer layer 120 .

[0207] In other embodiments, when or after removing the substrate 200 and before forming the drain 90, all buffer layers and the nucleation layer 210 may be removed, or only the nucleation layer 210 may be removed while retaining all buffer layers. The nucleation layer and other parts of the buffer layers may also be removed, such as removing the nucleation layer 210 and the first buffer layer 220.

[0208] It should be noted that, unlike the above Figure 4 The difference between the method of preparing the semiconductor device shown is that Figure 28 The method for preparing the semiconductor device shown does not include the steps for preparing the P-type modulation layer 30. Other film layers and preparation steps can refer to the above-mentioned Figure 4 The description of the method for manufacturing the semiconductor device shown is not repeated here.

[0209] The embodiment of the method for preparing a semiconductor device provided in the embodiment of the present application and the embodiment of the semiconductor device belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0210] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: drift layer; A P-type modulation layer is provided on a central region of one side surface of the drift layer in the thickness direction of the semiconductor device; a current blocking layer, disposed on the same side surface of the drift layer as the P-type modulation layer and located at the periphery of the P-type modulation layer; a channel layer located on a side of the P-type modulation layer and the current blocking layer facing away from the drift layer, and the channel layer covers the P-type modulation layer and a portion of the current blocking layer adjacent to the P-type modulation layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; a first trench penetrating the channel layer and the P-type modulation layer in a thickness direction of the semiconductor device; a barrier layer, located on a side of the channel layer facing away from the drift layer and in the first trench, wherein the barrier layer located on the side of the channel layer facing away from the drift layer forms a heterojunction structure with the channel layer; a PGaN active layer located in the first trench and in contact with the barrier layer; a gate, located on a side of the PGaN active layer facing away from the drift layer; a source electrode, at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure; The drain is located on a side of the drift layer away from the heterojunction structure.

2. The semiconductor device according to claim 1, wherein In a thickness direction of the semiconductor device, a bottom wall of the first trench is higher than a bottom surface of the current blocking layer on a side facing the drift layer.

3. The semiconductor device according to claim 2, wherein The top surface of the current blocking layer facing away from the drift layer is flush with the top surface of the P-type modulation layer facing away from the drift layer, or the top surface of the current blocking layer facing away from the drift layer is higher than the top surface of the P-type modulation layer facing away from the drift layer.

4. The semiconductor device according to claim 1, wherein The semiconductor device is a PGaN structure GaN power device, and the gate is a Schottky metal; and / or, The material of the current blocking layer is P-type gallium nitride.

5. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a passivation layer, the passivation layer being located on a side of the gate and the barrier layer facing away from the drift layer; The source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

6. A semiconductor device, characterized in that: The semiconductor device comprises: drift layer; a current blocking layer provided in a peripheral region of a surface of the drift layer on one side in a thickness direction of the semiconductor device, wherein a middle region of the surface of the drift layer where the current blocking layer is provided is exposed from the middle of the current blocking layer; a channel layer located on the same side of the drift layer and the current blocking layer, and the channel layer covers the drift layer exposed from the middle of the current blocking layer and a partial width of the current blocking layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; a second trench penetrating the channel layer in a thickness direction of the semiconductor device; a barrier layer, located on a side of the channel layer facing away from the drift layer and in the second trench, wherein the barrier layer located on the side of the channel layer facing away from the drift layer forms a heterojunction structure with the channel layer; a PGaN active layer located in the second trench and in contact with the barrier layer; a gate, located on a side of the PGaN active layer facing away from the drift layer; a source electrode, at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure; The drain is located on a side of the drift layer away from the heterojunction structure.

7. The semiconductor device according to claim 6, wherein In the thickness direction of the semiconductor device, the bottom wall of the second trench is higher than the bottom surface of the current blocking layer on the side facing the drift layer; and / or, The semiconductor device is a PGaN structure GaN power device, and the gate is a Schottky metal; and / or, The material of the current blocking layer is P-type gallium nitride; and / or, The semiconductor device further includes a passivation layer, wherein the passivation layer is located on a side of the gate and the barrier layer away from the drift layer; The source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

8. A method for preparing a semiconductor device, characterized in that: include: providing a substrate, and forming a drift layer on one side of the substrate; forming a P-type modulation layer in a middle region of a surface of the drift layer facing away from the substrate; forming a current blocking layer on a surface of the drift layer facing away from the substrate and located outside the P-type modulation layer; A channel layer, a first trench, a barrier layer, a PGaN active layer, and a gate are formed on a side of the P-type modulation layer and the current blocking layer away from the drift layer; the channel layer covers the P-type modulation layer and a portion of the current blocking layer adjacent to the P-type modulation layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; The first trench penetrates the channel layer and the P-type modulation layer in a thickness direction of the semiconductor device; A barrier layer is located on a side of the channel layer away from the drift layer and in the first trench, and the barrier layer located on a side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; A PGaN active layer is located in the first trench and contacts the barrier layer; The gate is located on a side of the PGaN active layer away from the drift layer; forming a source electrode, wherein the source electrode is at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure; The substrate is removed and a drain is formed, wherein the drain is located on a side of the drift layer away from the heterojunction structure.

9. The method for preparing a semiconductor device according to claim 8, wherein: After providing a substrate and before forming a drift layer on one side of the substrate, the method includes: forming a nucleation layer and a buffer layer on one side of the substrate, wherein the nucleation layer is an AlN layer, and the buffer layer comprises an AlGaN layer, a staggered multi-layer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer; The forming of a drift layer on one side of the substrate comprises: A drift layer is formed on a side of the buffer layer facing away from the substrate.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: When or after removing the substrate and before forming the drain, the method further includes: removing the nucleation layer; or, The nucleation layer and at least a portion of the buffer layer are removed.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: Before forming the source, the method further includes: forming a passivation layer, wherein the passivation layer is located on a side of the gate and the barrier layer facing away from the drift layer; After the source electrode is formed, the source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

12. A method for preparing a semiconductor device, characterized in that: include: providing a substrate, and forming a drift layer on one side of the substrate; forming a current blocking layer in a peripheral region of a surface of the drift layer on one side in a thickness direction of the semiconductor device; a middle region of the surface of the drift layer where the current blocking layer is provided is exposed from the middle of the current blocking layer; A channel layer, a second trench, a barrier layer, a PGaN active layer, and a gate are formed on the same side of the drift layer and the current blocking layer, wherein the channel layer covers the drift layer exposed from the middle of the current blocking layer and a portion of the width of the current blocking layer; the current blocking layer includes a first blocking portion overlapping with the channel layer, and a second blocking portion located outside the first blocking portion and not overlapping with the channel layer; the second trench penetrates the channel layer in the thickness direction of the semiconductor device; The barrier layer is located on a side of the channel layer away from the drift layer and in the second trench, and the barrier layer located on a side of the channel layer away from the drift layer forms a heterojunction structure with the channel layer; The PGaN active layer is located in the second trench; The gate is located on a side of the PGaN active layer away from the drift layer; forming a source electrode, wherein the source electrode is at least located on a side of the second blocking portion of the current blocking layer away from the drift layer and in contact with the heterojunction structure; The substrate is removed and a drain is formed, wherein the drain is located on a side of the drift layer away from the heterojunction structure.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: After providing a substrate and before forming a drift layer on one side of the substrate, the method includes: forming a nucleation layer and a buffer layer on one side of the substrate, wherein the nucleation layer is an AlN layer, and the buffer layer comprises an AlGaN layer, a staggered multi-layer AlN / GaN layer, a low-temperature GaN layer, and a high-temperature GaN layer sequentially stacked on the nucleation layer; The forming of a drift layer on one side of the substrate comprises: forming a drift layer on a side of the buffer layer facing away from the substrate; When or after removing the substrate and before forming the drain, the method further includes: removing the nucleation layer; or, The nucleation layer and at least a portion of the buffer layer are removed.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: Before forming the source, the method further includes: forming a passivation layer, wherein the passivation layer is located on a side of the gate and the barrier layer facing away from the drift layer; After the source electrode is formed, the source electrode is located on a side of the second blocking portion of the current blocking layer away from the drift layer and on a side of the passivation layer away from the drift layer.

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