Semiconductor device, manufacturing method, power module, conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device, a preparation method, a power module, a conversion circuit, and a vehicle. The semiconductor device includes: a substrate; a semiconductor epitaxial layer located on one side of the substrate; a gate trench located on the surface of the semiconductor epitaxial layer away from the substrate; a trench gate structure located in the gate trench; a first electrode located on the side of the substrate away from the semiconductor epitaxial layer; a second electrode located on the surface of the semiconductor epitaxial layer away from the substrate and located on at least one side of the trench gate structure; and a third electrode disposed within the semiconductor epitaxial layer and located at the bottom of the trench gate structure. The semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel connecting the first electrode to the second electrode; and the second body region is used to form a second channel connecting the first electrode to the third electrode. The technical solution provided by the embodiments of the present invention reduces on-resistance while increasing the breakdown voltage of the device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle. Background Art

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) possesses excellent physical and electrical properties. Compared to silicon, SiC has a wider bandgap, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0003] However, SiC semiconductor devices still have the problem of relatively high on-resistance. Currently, a multi-channel approach or a trench gate approach is commonly used to reduce the on-resistance of power devices. Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art. Figure 1 , including a semiconductor epitaxial layer and a source electrode S and a drain electrode D located on opposite sides of the semiconductor epitaxial layer, the semiconductor epitaxial layer includes a drift region (n-drift), an n+ region and a p-base region located at the bottom of the gate G, and an n+ region and a p-base region located on the side of the gate G, Figure 1 The semiconductor device shown is a non-trench semiconductor device including multiple channels (lateral channels and vertical channels). However, for the non-trench multi-channel conduction structure, due to the large cell unit area, the effect of increasing the current density (reducing the on-resistance) is not good; trench semiconductor devices have the advantages of small cell size and high current density; however, in trench semiconductor devices, the high electric field at the bottom and corner of the trench will increase the electric field on the gate insulation layer, thereby causing the gate insulation layer to be easily broken down.

[0004] In related technologies, Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in the prior art. Figure 2 , Figure 2 The semiconductor device shown is a trench-type semiconductor device including a shielded gate structure. Providing a shielded gate structure 1 below the trench gate can improve the problem of gate insulation being easily broken down, thereby increasing the device's breakdown voltage. Furthermore, increasing the depth of the trench also helps reduce on-resistance. However, providing the shielded gate structure 1 requires a deeper trench, and the deeper the trench, the more difficult it is to fabricate the device. Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in the prior art. Figure 3Alternatively, a P+ region 2 can be formed at the bottom and sidewalls of the gate trench through ion implantation to serve as an electric field shield. However, the accumulated charge in the P+ region 2 at the gate bottom can lead to a decrease in shielding effectiveness and even failure. Therefore, how to simultaneously reduce the on-resistance of semiconductor devices and increase their breakdown voltage remains a pressing technical challenge for researchers in this field. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle, which can reduce on-resistance while increasing the breakdown voltage of the device.

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0007] substrate;

[0008] a semiconductor epitaxial layer, located on one side of the substrate;

[0009] a gate trench, located on a surface of the semiconductor epitaxial layer away from the substrate;

[0010] a trench gate structure located in the gate trench;

[0011] a first electrode, located on a side of the substrate away from the semiconductor epitaxial layer;

[0012] a second electrode, located on a surface of the semiconductor epitaxial layer away from the substrate and located on at least one side of the trench gate structure;

[0013] a third electrode, disposed in the semiconductor epitaxial layer and located at the bottom of the trench gate structure;

[0014] Among them, the semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel connecting the first electrode and the second electrode; the second body region is used to form a second channel connecting the first electrode and the third electrode.

[0015] Optionally, the semiconductor epitaxial layer includes, in sequence along a direction away from the substrate, a drift region, a first body region, and a first contact region in contact with the second electrode;

[0016] The first body region and the first contact region are both located on the same side of the gate trench as the second electrode; the first contact region includes a first contact region of a first doping type and a first contact region of a second doping type; the first contact region of the first doping type is located between the gate trench and the first contact region of the second doping type; the doping type of the first body region is the second doping type, and the doping type of the drift region is the first doping type;

[0017] The first body region contacts a sidewall of the trench gate structure.

[0018] Optionally, the semiconductor epitaxial layer further includes a second contact region covering the sidewall and bottom of the third electrode, and a second body region located between the second contact region and the drift region;

[0019] The first body region and the second body region have the same doping type; the second contact region includes a first doping type second contact region and a second doping type second contact region; the first doping type second contact region is located on a sidewall of the third electrode; and the second doping type second contact region is located at the bottom of the third electrode;

[0020] The second body region contacts at least one of a sidewall and a bottom of the trench gate structure.

[0021] Optionally, the width of the third electrode is smaller than the width of the gate trench;

[0022] The first doping type second contact region and the second body region are both located at the bottom of the gate trench, and a width of the second body region is less than or equal to a width of the gate trench; the second body region contacts the bottom of the trench gate structure;

[0023] Alternatively, the second contact region of the first doping type is located at the bottom of the gate trench, and the second body region is located at the bottom of the gate trench and extends from the bottom of the gate trench along the bottom corner of the gate trench to the sidewall of the gate trench; the second body region contacts the sidewall and bottom of the trench gate structure;

[0024] Alternatively, the first-doping type second contact region is located at the bottom of the gate trench and extends from the bottom of the gate trench along the bottom corner of the gate trench to the side wall of the gate trench; the second body region extends from the bottom of the gate trench along the surface of the first-doping type second contact region on the side away from the gate trench until it covers the surface of the first-doping type second contact region on the side away from the substrate; the second body region contacts the side wall of the trench gate structure.

[0025] Optionally, the width of the third electrode is equal to the width of the gate trench;

[0026] The first-doping type second contact region extends from the side wall of the third electrode to the side wall of the gate trench; the second body region extends from the bottom of the gate trench along the surface of the first-doping type second contact region away from the gate trench until it covers the surface of the first-doping type second contact region away from the substrate; the second body region contacts the side wall of the trench gate structure.

[0027] Optionally, the trench gate structure includes a polysilicon gate and a gate insulation layer located between the polysilicon gate and the gate trench.

[0028] Optionally, the semiconductor device further includes a dielectric isolation layer;

[0029] The dielectric isolation layer is located in the gate trench and between the third electrode and the polysilicon gate.

[0030] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0031] providing a substrate;

[0032] forming a semiconductor epitaxial layer on one side of the substrate;

[0033] forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate;

[0034] forming a third electrode at the bottom of the gate trench and forming a trench gate structure in the gate trench;

[0035] forming a second electrode on a surface of the semiconductor epitaxial layer away from the substrate; the second electrode is located on at least one side of the trench gate structure;

[0036] A first electrode is formed on a surface of the substrate away from the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel connecting the first electrode and the second electrode; and the second body region is used to form a second channel connecting the first electrode and the third electrode.

[0037] Optionally, after forming the semiconductor epitaxial layer on one side of the substrate, the method further includes:

[0038] forming a drift region, the first body region, and a first contact region contacting the second electrode in sequence in the semiconductor epitaxial layer;

[0039] Forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate includes:

[0040] The first contact region, the first body region, and a portion of the drift region are sequentially etched from a surface of the first contact region away from the substrate to form the gate trench; after the gate trench is formed, the first body region and the first contact region are both located on the same side of the gate trench as the second electrode;

[0041] Among them, the first contact region includes a first contact region of a first doping type and a first contact region of a second doping type; the first contact region of the first doping type is located between the gate trench and the first contact region of the second doping type; the doping type of the first body region is the second doping type, and the doping type of the drift region is the first doping type; the first body region contacts the sidewall of the trench gate structure.

[0042] Optionally, forming a third electrode at the bottom of the gate trench includes:

[0043] An electrode groove is formed at the bottom of the gate groove, and ion implantation is performed at the bottom of the gate groove to form a second contact region located at the sidewall and bottom of the electrode groove and a second body region located between the second contact region and the drift region; wherein the first body region and the second body region have the same doping type; the second contact region includes a first doping type second contact region and a second doping type second contact region; the first doping type second contact region is located at the sidewall of the electrode groove; the second doping type second contact region is located at the bottom of the electrode groove, and the second body region contacts at least one of the sidewall and the bottom of the trench gate structure;

[0044] The third electrode is formed in the electrode groove.

[0045] Optionally, when the width of the third electrode is equal to the width of the gate trench, forming an electrode groove at the bottom of the gate trench includes:

[0046] The gate trench and the electrode recess are formed in the same etching process.

[0047] Optionally, after forming the gate trench and the electrode groove, the method further includes:

[0048] forming a carbon film on the groove wall of the gate groove and the groove wall of the electrode groove, passivating the groove wall with argon gas and performing high-temperature annealing treatment, and then removing the carbon film;

[0049] A sacrificial oxide layer is formed on the groove wall of the gate groove and the groove wall of the electrode groove, and the sacrificial oxide layer is removed.

[0050] Optionally, forming a trench gate structure in the gate trench includes:

[0051] forming a gate insulating layer on a wall of the gate trench;

[0052] forming a polysilicon gate on a surface of the gate insulating layer away from the gate trench;

[0053] Before forming a polysilicon gate on the surface of the gate insulation layer away from the gate trench, the method further comprises:

[0054] A dielectric isolation layer is formed at the bottom of the gate trench.

[0055] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0056] According to another aspect of the present invention, there is provided a power conversion circuit, characterized in that the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0057] The power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0058] According to another aspect of the present invention, a vehicle is provided, comprising a load and the power conversion circuit described in any embodiment of the present invention, wherein the power conversion circuit is configured to convert alternating current (AC) into direct current (DC), convert AC into AC, convert DC into DC, or convert DC into AC, and then input the converted DC into AC.

[0059] The technical solution provided by an embodiment of the present invention comprises a third electrode disposed at the bottom of a trench gate structure, and a first body region and a second body region formed in a semiconductor epitaxial layer in contact with the trench gate structure. The first body region is used to form a first channel connecting the first electrode to the second electrode, and the second body region is used to form a second channel connecting the first electrode to the third electrode, thereby forming a trench-type semiconductor device with multiple channels. The multiple channels can be used to reduce on-resistance. Furthermore, the trench-type semiconductor device can also reduce the cell area, which is effective in increasing current density (reducing on-resistance). Furthermore, the body region and contact region formed by ion implantation around the third electrode can reduce the electric field at the bottom and bottom corners of the gate trench, thereby improving the problem of gate insulation layer breakdown and increasing the device's breakdown voltage. Compared to shielded gate structures, deep trench etching is not required, which can reduce the difficulty of semiconductor device fabrication. Compared to solutions with only a P+ region, the third electrode can improve the problem of reduced electric field shielding effect and failure due to accumulated charge. This achieves both reduced on-resistance and increased device breakdown voltage.

[0060] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 It is a structural schematic diagram of a semiconductor device provided in the prior art;

[0063] Figure 2 It is a structural schematic diagram of another semiconductor device provided in the prior art;

[0064] Figure 3 It is a structural schematic diagram of another semiconductor device provided in the prior art;

[0065] Figure 4 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0066] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0067] Figure 6 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0068] Figure 7 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0069] Figure 8 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0070] Figure 9 1 is a schematic structural diagram corresponding to step S120 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0071] Figure 10 1 is a schematic structural diagram corresponding to step S130 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0072] Figure 11 4 is a schematic structural diagram corresponding to step S411 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0073] Figures 12-14 FIG. 1 is a schematic structural diagram corresponding to step S412 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0074] Figure 154 is a schematic structural diagram corresponding to step S413 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0075] Figures 16 to 18 4 is a schematic structural diagram corresponding to steps S414 to S416 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0076] Figures 19 to 24 It is a structural schematic diagram corresponding to steps S421 to S426 in a method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0077] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0078] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0079] An embodiment of the present invention provides a semiconductor device, Figure 4 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, with reference to Figure 4 , semiconductor devices include:

[0080] substrate 10;

[0081] The semiconductor epitaxial layer 20 is located on one side of the substrate 10;

[0082] A gate trench is located on the surface of the semiconductor epitaxial layer 20 away from the substrate 10;

[0083] A trench gate structure 60 is located in the gate trench;

[0084] The first electrode 30 is located on a side of the substrate 10 away from the semiconductor epitaxial layer 20 ;

[0085] The second electrode 40 is located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 and is located on at least one side of the trench gate structure 60; Figure 4 The second electrodes 40 are exemplarily shown to be located on two opposite sides of the trench gate structure 60 ;

[0086] The third electrode 50 is disposed in the semiconductor epitaxial layer 20 and is located at the bottom of the trench gate structure 60;

[0087] The first electrode 30 and the second electrode 40 are electrically connected via a first channel L1 extending along the sidewalls of the gate trench; the first electrode 30 and the third electrode 50 are electrically connected via a second channel L2 extending along the sidewalls and / or bottom of the gate trench. The semiconductor epitaxial layer 20 includes a first body region 22 and a second body region 25 in contact with the trench gate structure 60. The first body region 22 forms the first channel L1 electrically connecting the first electrode 30 and the second electrode 40; the second body region 25 forms the second channel L2 electrically connecting the first electrode 30 and the third electrode 50.

[0088] Specifically, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be the same or different. In an embodiment of the present invention, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 are the same, and both may be SiC. That is, the trench power device in the embodiment of the present invention may be a trench SiC power device. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a large bandgap and has advantages such as high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios. In some embodiments of the present invention, the substrate 10 and the semiconductor epitaxial layer 20 can be provided as a whole. The substrate 10 and the semiconductor epitaxial layer 20 being integrated can be understood as the substrate 10 and the semiconductor epitaxial layer 20 being a single SiC film structure formed in the same manufacturing process. After the front surface of the entire SiC film structure is processed, the back surface of the SiC film structure is thinned and the back surface of the SiC film structure is heavily ion doped to form the substrate 10.

[0089] The trench gate structure includes a polysilicon gate 61 and a gate insulating layer 62 located between the polysilicon gate 61 and the gate trench. The material of the gate insulating layer 62 may include at least one of aluminum oxide and silicon oxide. The materials of the first electrode 30, the second electrode 40, and the third electrode 50 may all include metal materials. The first electrode 30 may be a drain electrode, and the second electrode 40 and the third electrode 50 may both be source electrodes; or the first electrode 30 may be a source electrode, and the second electrode 40 and the third electrode 50 may both be drain electrodes. The first electrode 30 and the second electrode 40 are electrically connected via a first channel L1 extending along the sidewalls of the gate trench; the first electrode 30 and the third electrode 50 are electrically connected via a second channel L2 extending along the sidewalls and / or bottom surface of the gate trench, thereby forming a multi-channel semiconductor device.

[0090] The semiconductor device provided by an embodiment of the present invention forms a trench-type semiconductor device with multiple channels by providing a third electrode at the bottom of the trench gate structure. The multiple channels can be used to reduce on-resistance, and by providing the semiconductor device in a trench-type configuration, the cell unit area can be reduced, which has a better effect on increasing current density (reducing on-resistance). In addition, the body region and contact region formed by ion implantation around the third electrode and the surrounding third electrode can reduce the electric field at the bottom and bottom corners of the gate trench, thereby improving the problem of easy breakdown of the gate insulating layer and increasing the breakdown voltage of the device. Compared with the scheme of the shielded gate structure, there is no need to etch deeper trenches, which can reduce the difficulty of preparing the semiconductor device. Compared with the scheme of simply providing a P+ region, the third electrode can improve the problem of reduced electric field shielding effect and failure due to accumulated charge. Thus, the on-resistance is reduced while the breakdown voltage of the device is improved.

[0091] The above is the core inventive concept of the present invention. The semiconductor device with multiple channels is described in detail below with reference to the accompanying drawings.

[0092] refer to Figure 4 The semiconductor epitaxial layer 20 includes a drift region 21 , a first body region 22 , and a first contact region 23 contacting the second electrode 40 , which are sequentially spaced away from the substrate 10 .

[0093] The first body region 22 and the first contact region 23 are both located on the same side of the trench gate structure 60 as the second electrode. Figure 4It is exemplarily shown that the first body region 22 and the first contact region 23 are both located on opposite sides of the trench gate structure 60; the first contact region 23 includes a first doping type first contact region 231 and a second doping type first contact region 232; the first doping type first contact region 231 is located between the gate trench and the second doping type first contact region 232; the doping type of the first body region 22 is the second doping type, and the doping type of the drift region 21 is the first doping type; the first body region 22 contacts the sidewall of the trench gate structure 60, and the first channel L1 is located in the first body region 22 between the first doping type first contact region 231 and the drift region 21.

[0094] Specifically, the doping type of the first contact region 231 of the first doping type may be N-type, and the doping type of the first contact region 232 of the second doping type may be P-type. Alternatively, the doping type of the first contact region 231 of the first doping type may be P-type, and the doping type of the first contact region 232 of the second doping type may be N-type. The doping type of the drift region 21 is the same as the doping type of the first contact region 231 of the first doping type, and the ion doping concentration of the drift region 21 is lower than the ion doping concentration of the first contact region 231 of the first doping type. The doping type of the first body region 22 is the same as the doping type of the first contact region 232 of the second doping type, and the ion doping concentration of the first body region 22 is lower than the ion doping concentration of the first contact region 232 of the second doping type.

[0095] Figure 4 In the figure, it is exemplarily shown that the first contact region 231 of the first doping type and the drift region 21 are doped with N-type dopant ions; the second contact region 232 and the body region are doped with P-type dopant ions. The P+ and N+ shown in the figure indicate that the ion doping concentration in the region is high, and the P- and N- indicate that the ion doping concentration in the region is low. Among them, the N-type dopant ions can be P (phosphorus) or N (nitrogen) ions, and the P-type dopant ions can be Al (aluminum) ions or B (boron) ions. The first channel L1 is located in the first body region 22 between the first contact region 231 of the first doping type and the drift region 21, and extends along the sidewall of the gate trench. The current flows upward from the first electrode 30 to the second electrode 40, and the first channel L1 forms an upper channel, and the first channel L1 is a vertical channel.

[0096] Based on the above embodiments, please continue to refer to Figure 4 Optionally, the semiconductor epitaxial layer 20 further includes a second contact region 24 covering the sidewall and bottom of the third electrode 50 and a second body region 25 located between the second contact region 24 and the drift region 21;

[0097] Among them, the second contact region includes a first-doping type second contact region 241 and a second-doping type second contact region 242; the first-doping type second contact region 241 is located on the side wall of the third electrode 50; the second-doping type second contact region 242 is located at the bottom of the third electrode 50, the second body region 25 is in contact with at least one of the side walls and the bottom of the trench gate structure 60, and the second channel L2 is located in the second body region 25 between the first-doping type first contact region 231 and the drift region 21.

[0098] It should be noted that the first body region 22 and the second body region 25 have the same doping type, the first doping type second contact region 241 and the first doping type first contact region 231 have the same doping type, and the second doping type second contact region 242 and the second doping type first contact region 232 have the same doping type.

[0099] Adding a conductive path at the bottom of the trench gate structure 60 increases current (reducing on-resistance) without increasing device area. The source metal (third electrode 50) at the bottom of the trench gate structure 60 isolates the drain (first electrode) from the gate insulation layer 62, protecting the fragile bottom edge of the gate oxide and improving device reliability. The P+ and P- regions formed at the bottom of the trench gate structure 60 form a body diode with a larger contact area, thereby increasing the maximum transient and surge current that the body diode can withstand, thereby improving device reliability.

[0100] Based on the above embodiments, Figure 4 In one embodiment of the present invention, the width of the third electrode 50 is smaller than the width of the gate trench; the first doping type second contact region 241 and the second body region 25 are both located at the bottom of the gate trench, and the width of the second body region 25 is smaller than or equal to the width of the gate trench ( Figure 4 The second body region 25 is exemplarily shown to have a width smaller than that of the gate trench); the second body region 25 contacts the bottom of the trench gate structure 60 , and the second channel L2 extends along the bottom surface of the gate trench.

[0101] Based on the above embodiments, Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, with reference to Figure 5 In another embodiment of the present invention, the width of the third electrode 50 is smaller than the width of the gate trench; the first doping type second contact region 241 is located at the bottom of the gate trench, and the second body region 25 is located at the bottom of the gate trench and extends from the bottom of the gate trench along the bottom corner of the gate trench to the sidewall of the gate trench; the second body region 25 contacts the bottom and sidewall of the trench gate structure 60, and the second channel L2 extends along the sidewall at the bottom corner of the gate trench and the bottom of the gate trench.

[0102] Based on the above embodiments, Figure 6 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, with reference to Figure 6 In another embodiment of the present invention, the width of the third electrode 50 is smaller than the width of the gate trench; the first-doping type second contact region 241 is located at the bottom of the gate trench and extends from the bottom of the gate trench along the bottom corner of the gate trench to the sidewall of the gate trench; the second body region 25 extends from the bottom of the gate trench along the surface of the first-doping type second contact region 241 away from the gate trench until it covers the surface of the first-doping type second contact region 241 away from the substrate 10; the second body region 25 contacts the sidewall of the trench gate structure 60, and the second channel L2 extends along the sidewall of the gate trench.

[0103] Based on the above embodiments, Figure 7 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, with reference to Figure 7 In another embodiment of the present invention, the width of the third electrode 50 is equal to the width of the gate trench; the first-doping type second contact region 241 extends from the sidewall of the third electrode 50 to the sidewall of the gate trench; the second body region 25 extends from the bottom of the gate trench along the surface of the first-doping type second contact region 241 away from the gate trench until it covers the surface of the first-doping type second contact region 241 away from the substrate 10; the second body region 25 contacts the sidewall of the trench gate structure 60, and the second channel L2 extends along the sidewall of the gate trench.

[0104] Based on the above embodiments, Figures 4 to 7 Optionally, the semiconductor device further includes a dielectric isolation layer 70; the dielectric isolation layer 70 is located in the gate trench and between the third electrode 50 and the polysilicon gate 61. Figures 4 to 6 The example shows that the vertical projection of the dielectric isolation layer 70 on the substrate 10 is larger than the vertical projection of the third electrode 50 on the substrate 10. Figure 7 The vertical projection of the dielectric isolation layer 70 on the substrate 10 is exemplarily shown to be smaller than the vertical projection of the third electrode 50 on the substrate 10. In other embodiments of the present invention, the vertical projection of the dielectric isolation layer 70 on the substrate 10 may also be equal to the vertical projection of the third electrode 50 on the substrate 10.

[0105] Specifically, since the gate insulating layer 62 is typically thinner, typically in the range of 4 nm to 5 nm, and the gate insulating layer 62 at the bottom of the gate trench is more difficult to grow than the gate insulating layer 62 located on the sidewalls of the gate trench, resulting in the gate insulating layer 62 at the bottom being thinner, a thicker dielectric isolation layer 70 is provided between the third electrode 50 and the polysilicon gate 61 to enhance the isolation between the third electrode 50 and the polysilicon gate 61. The thickness of the dielectric isolation layer 70 can be greater than or equal to the thickness of the gate insulating layer 62 located at the bottom of the gate trench. The material of the dielectric isolation layer 70 can include at least one of SiO2 and Al2O3. The dielectric isolation layer 70 can be prepared by at least one of ALD, thermal oxidation, and wet processing.

[0106] The embodiment of the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device described in any of the above embodiments. Figure 8 This is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 8 , a method for preparing a semiconductor device, comprising:

[0107] S110 , providing a substrate.

[0108] S120 , forming a semiconductor epitaxial layer on one side of the substrate.

[0109] Specifically, Figure 9 This is a schematic structural diagram corresponding to step S120 in a method for preparing a semiconductor device according to an embodiment of the present invention, with reference to Figure 9 , the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be the same or different. In an embodiment of the present invention, the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 are the same, and both may be SiC. In some embodiments of the present invention, the substrate 10 and the semiconductor epitaxial layer 20 may be provided as one piece. The substrate 10 and the semiconductor epitaxial layer 20 being one piece can be understood as the substrate 10 and the semiconductor epitaxial layer 20 being a whole SiC film layer structure formed in the same preparation process. After the front surface process is performed on the whole SiC film layer structure, the back surface of the SiC film layer structure is thinned, and the back surface of the SiC film layer structure is heavily doped with ions to form the substrate 10.

[0110] After forming the semiconductor epitaxial layer 20 on one side of the substrate 10, the process further includes forming a drift region 21, a first body region 22, and a first contact region 23 in contact with the second electrode 40 in the semiconductor epitaxial layer 20. Specifically, PECVD and photolithography techniques can be used to transfer the pattern of the photomask to a SiO2 mask layer. Based on the patterned mask layer, front ion implantation is then performed on the semiconductor epitaxial layer 20 to form the drift region 21, the first body region 22, and the first contact region 23 in contact with the second electrode 40 in the semiconductor epitaxial layer 20. The mask layer is then removed. Different patterned mask layers can be used for ion implantation in different regions. Figure 9 In the embodiment, N-type dopant ions are implanted into the first contact region 231 of the first doping type and the drift region 21 ; and P-type dopant ions are implanted into the first contact region 232 of the second doping type and the first body region 22 .

[0111] S130 , forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate.

[0112] Specifically, Figure 10 This is a schematic structural diagram corresponding to step S130 in a method for preparing a semiconductor device according to an embodiment of the present invention, with reference to Figure 10 , the first contact region 23 (first doping type first contact region 231), the first body region 22 and part of the drift region 21 can be sequentially etched from the surface of the first contact region 23 away from the substrate 10 through a photolithography process to form a gate trench 01; after the gate trench 01 is formed, the first body region 22 and the first contact region 23 are both located on opposite sides of the gate trench 01. The specific steps of forming the gate trench 01 through the photolithography process may include: depositing SiO2 as a mask layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 through a deposition process such as CVD, spin-coating a photoresist PR on the surface of the mask layer, forming a photoresist PR of a desired pattern through exposure and development, and then etching the mask layer based on the patterned photoresist PR to pattern the mask layer. The patterned mask layer exposes the preset position of the gate trench. Based on the patterned mask layer, the first doping type first contact region 231, the first body region 22 and part of the drift region 21 of the semiconductor epitaxial layer 20 are etched in sequence; wherein, the etching process can adopt a plasma dry etching process, such as RIE or ICP etching process.

[0113] S140 , forming a third electrode at the bottom of the gate trench, and forming a trench gate structure in the gate trench.

[0114] Specifically, forming the third electrode at the bottom of the gate trench includes: forming an electrode trench at the bottom of the gate trench, and performing ion implantation at the bottom of the gate trench to form a second contact region located on the sidewalls and bottom of the electrode trench, and a second body region located between the second contact region and the drift region. The first body region and the second body region have the same doping type; the second contact region includes a first-doping-type second contact region and a second-doping-type second contact region; the first-doping-type second contact region is located on the sidewalls of the electrode trench; the second-doping-type second contact region is located at the bottom of the electrode trench; and the second channel is located in the second body region between the first-doping-type first contact region and the drift region; and forming the third electrode in the electrode trench.

[0115] In one embodiment of the present invention, optionally, the width of the third electrode 50 is smaller than the width of the gate trench. Step S140 of forming the third electrode at the bottom of the gate trench includes:

[0116] S411 , forming an electrode groove at the bottom of the gate trench, the electrode groove having a width smaller than that of the gate trench.

[0117] Specifically, Figure 11 This is a schematic structural diagram corresponding to step S411 in a method for preparing a semiconductor device according to an embodiment of the present invention, with reference to Figure 11 , an electrode groove 02 having a width smaller than that of the gate trench can be formed using a SiO2 mask layer and a precise dry etching technique (such as DRIE or ICP).

[0118] S412 , performing ion implantation at the bottom of the gate trench 01 to form a second contact region 24 located on the sidewalls and bottom of the electrode recess 02 and a second body region 25 located between the second contact region 24 and the drift region 21 .

[0119] Among them, for the formation Figure 4 The semiconductor device shown in FIG. 1 is ion-implanted at the bottom of the gate trench 01. Figure 12 , the first doping type second contact region 241 and the second body region 25 are both located at the bottom of the gate trench 01, and the width of the second body region 25 is less than or equal to the width of the gate trench 01 ( Figure 12 As an example, it is shown that the width of the second body region 25 is smaller than the width of the gate trench 01 ).

[0120] For the formation Figure 5 The semiconductor device shown in FIG. 1 is ion-implanted at the bottom of the gate trench 01. Figure 13 The first doping type second contact region 241 is located at the bottom of the gate trench 01 , and the second body region 25 is located at the bottom of the gate trench 01 and extends from the bottom of the gate trench 01 along the bottom corner of the gate trench 01 to the sidewall of the gate trench 01 .

[0121] For the formation Figure 6 The semiconductor device shown in FIG. 1 is ion-implanted at the bottom of the gate trench 01. Figure 14 The first doping type second contact region 241 is located at the bottom of the gate trench 01, and extends from the bottom of the gate trench 01 along the bottom corner of the gate trench 01 to the side wall of the gate trench 01; the second body region 25 extends from the bottom of the gate trench 01 along the surface of the first doping type second contact region 241 away from the gate trench 01 until it covers the surface of the first doping type second contact region 241 away from the substrate 10.

[0122] S413 , depositing source metal, removing the source metal on the sidewall of the gate trench by wet etching to retain the source metal in the electrode groove, and performing an annealing process to form a third electrode 50 in the electrode groove.

[0123] Specifically, to form Figure 4 As an example, refer to the semiconductor device shown in Figure 15 After depositing the metal material, the metal material on the sidewall of the gate trench 01 is removed by wet etching, and the metal material located in the electrode groove 02 is retained. An annealing process is then performed to form a third electrode 50 in the electrode groove 02.

[0124] Furthermore, after ion implantation is performed at the bottom of the gate trench 01 (ie, before the source metal is deposited), the following steps are further included:

[0125] A carbon film is formed on the walls of the gate trench 01 and the electrode groove 02, and the walls are passivated with argon gas and subjected to high-temperature annealing treatment, and then the carbon film is removed;

[0126] A sacrificial oxide layer is formed on the groove wall of the gate trench 01 and the groove wall of the electrode groove 02 , and then the sacrificial oxide layer is removed.

[0127] Specifically, to activate the implanted dopant ions and eliminate lattice damage defects caused by the implanted dopant ions, the semiconductor epitaxial layer 20 needs to be activated and annealed at a high temperature, typically as high as 1600°C to 1800°C. However, at such a high activation annealing temperature, since the semiconductor epitaxial layer 20 is made of silicon carbide, Si on the silicon carbide surface easily sublimates from the SiC surface and redeposits on the wafer surface in the form of Si, Si2C, SiC2, etc., forming step clusters. This increases the surface roughness of the SiC wafer and the interface state density, seriously affecting device performance. A commonly used method for high-temperature annealing is the carbon film protection method, which is generally produced by sputtering a carbon film protective layer or by baking and curing a photoresist to form a carbon film protective layer. After the high-temperature annealing is completed, the carbon film used to protect the silicon carbide surface needs to be removed. If the carbon film is not removed cleanly, it will affect the ohmic contact and seriously affect the device's switching characteristics, conductivity, withstand voltage characteristics, and other performance. The carbon film can be removed by immersion in a chemical solution, which is usually a certain concentration of hydrochloric acid with a certain amount of nitric acid as a catalyst. Furthermore, after removing the carbon film on the surface of the semiconductor epitaxial layer 20, the process further includes: forming a sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 by a thermal oxidation process to repair the crystal lattice of the surface of the semiconductor epitaxial layer 20; and then removing the sacrificial oxide layer. The sacrificial oxide layer on the surface can be removed by BOE cleaning.

[0128] Figures 16 to 18 This is a schematic structural diagram corresponding to steps S414 to S416 in a method for preparing a semiconductor device according to an embodiment of the present invention, with reference to Figures 16 to 18 In step S140, forming a trench gate structure in the gate trench 01 includes:

[0129] S414 , forming a gate insulating layer on the wall of the gate trench.

[0130] Specifically, refer to Figure 16 At least one of SiO 2 and Al 2 O 3 may be deposited by ALD to form the gate insulating layer 62 .

[0131] S415 , forming a dielectric isolation layer at the bottom of the gate trench.

[0132] Specifically, refer to Figure 17The material of the dielectric isolation layer 70 can include at least one of SiO2 and Al2O3, and the dielectric isolation layer 70 can be prepared by at least one of ALD, thermal oxidation, and wet methods. Since the gate insulation layer 62 is typically thinner, ranging from 4nm to 5nm, and the gate insulation layer 62 at the bottom of the gate trench 01 is more difficult to grow than the gate insulation layer 62 located on the sidewalls of the gate trench 01, resulting in a thinner gate insulation layer 62 at the bottom, a thicker dielectric isolation layer 70 is provided between the third electrode 50 and the polysilicon gate 61 to enhance the isolation between the third electrode 50 and the polysilicon gate 61. The thickness of the dielectric isolation layer 70 can be greater than or equal to the thickness of the gate insulation layer 62 located at the bottom of the gate trench 01.

[0133] S416 , forming a polysilicon gate on a surface of the gate insulating layer away from the gate trench.

[0134] Specifically, refer to Figure 18 , polysilicon material can be deposited using an LPCVD process, and after the deposition is completed, polysilicon etching is performed to retain the polysilicon material located in the gate trench 01, thereby forming a polysilicon gate 61.

[0135] In another embodiment of the present invention, the width of the third electrode 50 is equal to the width of the gate trench 01 . Figures 19 to 24 This is a schematic structural diagram corresponding to steps S421 to S426 in a method for preparing a semiconductor device according to an embodiment of the present invention, which is used to form Figure 7 The semiconductor device shown. Figures 19 to 24 In step S140, forming a third electrode at the bottom of the gate trench includes:

[0136] S421 , forming a gate trench and the electrode trench in the same etching process, so that the width of the electrode trench is equal to the width of the gate trench.

[0137] Specifically, refer to Figure 19 Since the width of the third electrode 50 is equal to the width of the gate trench 01, the width of the electrode groove 02 for accommodating the third electrode 50 is equal to the width of the gate trench 01. After etching to form the gate trench 01, the semiconductor epitaxial layer 20 can be further etched in the same process to form an electrode groove 02 having the same width as the gate trench 01.

[0138] S422 , performing ion implantation at the bottom of the gate trench to form a second contact region located at the sidewall and bottom of the electrode groove and a second body region located between the second contact region and the drift region.

[0139] refer to Figure 20After ion implantation is performed at the bottom of the gate trench 01, the first-doped type second contact region 241 extends from the sidewall of the electrode groove 02 to the sidewall of the gate trench 01; the second body region 25 extends from the bottom of the gate trench 01 along the surface of the first-doped type second contact region 241 away from the gate trench 01 until it covers the surface of the first-doped type second contact region 241 away from the substrate 10.

[0140] S423, depositing source metal, removing the source metal on the sidewall of the gate trench 01 by wet etching, leaving the source metal in the electrode groove 02, and performing annealing to form the third electrode 50 in the electrode groove 02. Figure 21 .

[0141] Furthermore, after forming the gate trench 01 and the electrode groove 02 and performing ion implantation at the bottom of the gate trench 01 (ie, before depositing the source metal), the process further includes:

[0142] A carbon film is formed on the walls of the gate trench 01 and the electrode trench 02, and the walls are passivated using argon gas and subjected to high-temperature annealing, after which the carbon film is removed. A sacrificial oxide layer is formed on the walls of the gate trench 01 and the electrode trench 02, and then removed. The specific steps and effects can be referred to in the above embodiment and will not be repeated here.

[0143] In step S140, forming a trench gate structure in the gate trench 01 includes:

[0144] S424, forming a gate insulating layer 62 on the wall of the gate trench 01, and removing the gate insulating layer at the bottom of the gate trench 01 by dry etching. Figure 22 .

[0145] S425, forming a dielectric isolation layer 70 at the bottom of the gate trench 01. Figure 23 .

[0146] S426, forming a polysilicon gate 61 on the surface of the gate insulating layer 62 away from the gate trench 01. Figure 24 .

[0147] S150, forming a second electrode on the surface of the semiconductor epitaxial layer away from the substrate; the second electrode is located on at least one side of the trench gate structure. Optionally, the second electrode can be located on two opposite sides of the trench gate structure. For details, please refer to Figures 4 to 7 .

[0148] S160. A first electrode is formed on the surface of the substrate away from the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel connecting the first electrode and the second electrode; and the second body region is used to form a second channel connecting the first electrode and the third electrode.

[0149] The first electrode 30 and the second electrode 40 are connected via a first channel L1 extending along the sidewall of the gate trench; the first electrode 30 and the third electrode 50 are connected via a second channel L2 extending along the sidewall and / or bottom of the gate trench. Figures 4 to 7 .

[0150] It should be noted that before forming the first electrode 30 on the surface of the substrate 10 away from the semiconductor epitaxial layer 20 , the substrate 10 may be thinned from the side away from the semiconductor epitaxial layer 20 .

[0151] An embodiment of the present invention further provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to support the semiconductor device. The power module has the same technical effects and will not be described in detail here.

[0152] An embodiment of the present invention further provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, the semiconductor device being electrically connected to the circuit board. The circuit has the same technical effects and is not further described here.

[0153] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention, wherein the power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. The embodiments have the same technical effects and are not further described here.

[0154] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a semiconductor epitaxial layer, located on one side of the substrate; a gate trench, located on a surface of the semiconductor epitaxial layer away from the substrate; a trench gate structure located in the gate trench, the trench gate structure comprising a polysilicon gate and a gate insulating layer located between the polysilicon gate and the gate trench; a first electrode, located on a side of the substrate away from the semiconductor epitaxial layer; a second electrode, located on a surface of the semiconductor epitaxial layer away from the substrate and located on at least one side of the trench gate structure; a third electrode, disposed in the semiconductor epitaxial layer and located at the bottom of the trench gate structure; the third electrode is used to reduce the electric field at the bottom and bottom corner of the gate trench; The semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel connecting the first electrode and the second electrode; the second body region is used to form a second channel connecting the first electrode and the third electrode; The semiconductor device further includes a dielectric isolation layer; the dielectric isolation layer is located in the gate trench and between the third electrode and the polysilicon gate; When there is a gate insulation layer at the bottom of the gate trench, the top surface of the third electrode contacts the gate insulation layer, and the thickness of the dielectric isolation layer is greater than the thickness of the gate insulation layer located at the bottom of the gate trench; when there is no gate insulation layer at the bottom of the gate trench, the top surface of the third electrode contacts the dielectric isolation layer.

2. The semiconductor device according to claim 1, wherein The semiconductor epitaxial layer includes, in sequence along a direction away from the substrate, a drift region, the first body region, and a first contact region in contact with the second electrode; The first body region and the first contact region are both located on the same side of the trench gate structure as the second electrode; the first contact region includes a first contact region of a first doping type and a first contact region of a second doping type; the first contact region of the first doping type is located between the gate trench and the first contact region of the second doping type; the doping type of the first body region is the second doping type, and the doping type of the drift region is the first doping type; The first body region contacts a sidewall of the trench gate structure.

3. The semiconductor device according to claim 2, wherein The semiconductor epitaxial layer further includes a second contact region covering the sidewall and bottom of the third electrode and a second body region located between the second contact region and the drift region; The first body region and the second body region have the same doping type; the second contact region includes a first doping type second contact region and a second doping type second contact region; the first doping type second contact region is located on a sidewall of the third electrode; and the second doping type second contact region is located at the bottom of the third electrode; The second body region contacts at least one of a sidewall and a bottom of the trench gate structure.

4. The semiconductor device according to claim 3, wherein The width of the third electrode is smaller than the width of the gate trench; The first doping type second contact region and the second body region are both located at the bottom of the gate trench, and a width of the second body region is less than or equal to a width of the gate trench; the second body region contacts the bottom of the trench gate structure; Alternatively, the second contact region of the first doping type is located at the bottom of the gate trench, and the second body region is located at the bottom of the gate trench and extends from the bottom of the gate trench along the bottom corner of the gate trench to the sidewall of the gate trench; the second body region contacts the sidewall and bottom of the trench gate structure; Alternatively, the first doping type second contact region is located at the bottom of the gate trench and extends from the bottom of the gate trench along the bottom corner of the gate trench to the sidewall of the gate trench; the second body region extends from the bottom of the gate trench along the surface of the first doping type second contact region on a side away from the gate trench until it covers the surface of the first doping type second contact region on a side away from the substrate; The second body region contacts a sidewall of the trench gate structure.

5. The semiconductor device according to claim 3, wherein The width of the third electrode is equal to the width of the gate trench; The first-doping type second contact region extends from the sidewall of the third electrode to the sidewall of the gate trench; the second body region extends from the bottom of the gate trench along the surface of the first-doping type second contact region away from the gate trench until it covers the surface of the first-doping type second contact region away from the substrate; The second body region contacts a sidewall of the trench gate structure.

6. A method for preparing a semiconductor device, characterized in that: For preparing the semiconductor device according to any one of claims 1 to 5, comprising: providing a substrate; forming a semiconductor epitaxial layer on one side of the substrate; forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate; forming a third electrode at the bottom of the gate trench and forming a trench gate structure in the gate trench; forming a second electrode on a surface of the semiconductor epitaxial layer away from the substrate; the second electrode is located on at least one side of the trench gate structure; A first electrode is formed on a surface of the substrate away from the semiconductor epitaxial layer; wherein the semiconductor epitaxial layer includes a first body region and a second body region in contact with the trench gate structure; the first body region is used to form a first channel connecting the first electrode and the second electrode; and the second body region is used to form a second channel connecting the first electrode and the third electrode.

7. The method for preparing a semiconductor device according to claim 6, wherein: After forming a semiconductor epitaxial layer on one side of the substrate, the method further includes: forming a drift region, the first body region, and a first contact region contacting the second electrode in sequence in the semiconductor epitaxial layer; Forming a gate trench on a surface of the semiconductor epitaxial layer away from the substrate includes: The first contact region, the first body region, and a portion of the drift region are sequentially etched from a surface of the first contact region away from the substrate to form the gate trench; after the gate trench is formed, the first body region and the first contact region are both located on the same side of the gate trench as the second electrode; Among them, the first contact region includes a first contact region of a first doping type and a first contact region of a second doping type; the first contact region of the first doping type is located between the gate trench and the first contact region of the second doping type; the doping type of the first body region is the second doping type, and the doping type of the drift region is the first doping type; the first body region contacts the sidewall of the trench gate structure.

8. The method for preparing a semiconductor device according to claim 7, wherein: forming a third electrode at the bottom of the gate trench, comprising: An electrode groove is formed at the bottom of the gate groove, and ion implantation is performed at the bottom of the gate groove to form a second contact region located at the sidewall and bottom of the electrode groove and a second body region located between the second contact region and the drift region; wherein the first body region and the second body region have the same doping type; the second contact region includes a first doping type second contact region and a second doping type second contact region; the first doping type second contact region is located at the sidewall of the electrode groove; the second doping type second contact region is located at the bottom of the electrode groove, and the second body region contacts at least one of the sidewall and the bottom of the trench gate structure; The third electrode is formed in the electrode groove.

9. The method for preparing a semiconductor device according to claim 7, wherein: When the width of the third electrode is equal to the width of the gate trench, forming an electrode groove at the bottom of the gate trench comprises: The gate trench and the electrode recess are formed in the same etching process.

10. The method for preparing a semiconductor device according to claim 8, wherein: After forming the gate trench and the electrode groove, the method further includes: forming a carbon film on the groove wall of the gate groove and the groove wall of the electrode groove, passivating the groove wall with argon gas and performing high-temperature annealing treatment, and then removing the carbon film; A sacrificial oxide layer is formed on the groove wall of the gate groove and the groove wall of the electrode groove, and the sacrificial oxide layer is removed.

11. The method for manufacturing a semiconductor device according to claim 6, wherein: forming a trench gate structure in the gate trench, comprising: forming a gate insulating layer on a wall of the gate trench; forming a polysilicon gate on a surface of the gate insulating layer away from the gate trench; Before forming a polysilicon gate on the surface of the gate insulation layer away from the gate trench, the method further comprises: A dielectric isolation layer is formed at the bottom of the gate trench.

12. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to any one of claims 1 to 5, wherein the substrate is used to carry the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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