A three-dimensional memory and its preparation method

Abstract

The present invention provides a three-dimensional memory and a preparation method thereof. The present invention optimizes the upper and lower electrode layers into left and right electrode layers, thereby optimizing the traditional horizontal memory unit into a vertical memory unit. The effective area of ​​a single memory unit is increased, and the area of ​​a single memory unit can be smaller to save the occupied area of ​​the memory unit; the increase in the effective area of ​​the device can improve the storage performance, optimize and improve the operating efficiency and reliability of the device. Moreover, the arrangement of the vertical memory unit will not affect the deposition and phase change performance of the memory layer even if there is a protrusion in the first main connection structure in contact with the first electrode layer; and when the second electrode layer is formed, there is no problem of etching through the memory layer, thereby avoiding affecting the performance of the memory unit. And only two contact hole mask processes are required, saving one contact hole mask process, which can effectively reduce production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] New memory devices, such as phase-change RAM (PRAM) and ferroelectric RAM (FeRAM), integrate memory cells in the back-end-of-line (BEOL) process. The storage performance of a memory cell is proportional to the effective area of ​​the storage and electrode layers within the cell.

[0003] The memory cell of a traditional two-dimensional (2D) memory device consists of upper and lower electrode layers, and a central storage layer. These layers are deposited layer by layer using atomic layer deposition (ALD). The storage layer is made of phase-change or ferroelectric materials. However, as semiconductor manufacturing processes shrink, the memory cell area of ​​traditional 2D memories decreases, further reducing the effective area of ​​the storage and electrode layers, thus impacting memory performance. Furthermore, the fabrication of the connection structure between the upper and lower electrode layers of the memory cell requires multiple photomask steps, increasing production costs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a three-dimensional memory and a preparation method thereof, which can save the occupied area of ​​the storage unit and increase the effective area of ​​the device, thereby improving the storage performance, and can save the mask process and reduce the production cost.

[0005] To address the above-mentioned problem, the present invention provides a method for fabricating a three-dimensional memory device. The method comprises the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a first dielectric layer covering a surface of the substrate, first main connection structures extending through the first dielectric layer in a second direction and arranged at intervals along the first direction, and a first electrode layer formed on a surface of the first dielectric layer and in one-to-one contact with the first main connection structures, wherein the first direction is parallel to the substrate surface and the second direction is perpendicular to the substrate surface; forming a memory layer and a second electrode layer, the memory layer covering at least a sidewall of the first electrode layer and having an extension extending to the surface of the first dielectric layer, the second electrode layer covering the memory layer, and having a maximum thickness of the second electrode layer greater than a thickness of the first electrode layer in the second direction, wherein the first electrode layer, the memory layer, and the second electrode layer constitute memory cells of the three-dimensional memory device; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer and all of the memory cells; and forming a second main connection structure extending through the second dielectric layer in the second direction and in contact with the second electrode layer.

[0006] In some embodiments, the first main connection structure and the second main connection structure are made of a first metal material, the first electrode layer and the second electrode layer are made of a second metal material, and the first metal material and the second metal material are different.

[0007] In some embodiments, the material of the storage layer is a ferroelectric material or a phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the materials of the first main connection structure and the second main connection structure are both metal tungsten, and the materials of the first electrode layer and the second electrode layer are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

[0008] In some embodiments, the steps of forming a semiconductor substrate specifically include: providing a substrate, having a first dielectric layer formed on the surface of the substrate, having first contact holes formed in the first dielectric layer that penetrate the first dielectric layer along the second direction and are arranged at intervals along the first direction; filling the first contact holes with a first metal material to form the first main connection structure; depositing a second metal material and patterning it to form a first electrode layer on the surface of the first dielectric layer that is in one-to-one contact with the first main connection structure.

[0009] In some embodiments, the steps of depositing and patterning the second metal material specifically include: depositing a second metal material layer on the surface of the first dielectric layer; forming a patterned first protective layer on the surface of the second metal material layer; etching the second metal material layer using the patterned first protective layer as a mask and the first dielectric layer as an etching stop layer to form the first electrode layer that is in one-to-one contact with the first main connection structure, and the first protective layer is retained and covers the surface of the first electrode layer.

[0010] In some embodiments, the steps of forming the storage layer and the second electrode layer specifically include: depositing a storage material to form a storage material layer covering the first dielectric layer and all the first electrode layers; depositing a second metal material to form a second electrode material layer covering the storage material layer, wherein the maximum thickness of the second electrode material layer in the second direction is greater than the thickness of the first electrode layer; forming a patterned second protective layer on the surface of the second electrode material layer, wherein the patterned second protective layer can at least block a side wall of the first electrode layer and a portion of the first dielectric layer corresponding to the side wall; etching the second electrode material layer and the storage material layer using the patterned second protective layer as a mask and the first dielectric layer as an etching stop layer, etching the remaining storage material layer to form the storage layer, and etching the remaining second electrode material layer to form the second electrode layer, and the second protective layer remains and covers the surface of the second electrode layer.

[0011] In some embodiments, the patterned second protective layer can also shield the corresponding area of ​​the top surface of the first electrode layer; the storage layer also covers the top surface of the first electrode layer, and the second electrode layer completely covers the storage layer.

[0012] In some embodiments, the step of forming the second dielectric layer includes: forming an etch barrier layer, the etch barrier layer covering the first dielectric layer and all the storage units, and the second dielectric layer covering the etch barrier layer; the step of forming the second main connection structure specifically includes: using the etch barrier layer as an etch stop layer, etching in the second dielectric layer to form a second contact hole exposing the second electrode layer; depositing a first metal material and planarizing it to form the second main connection structure in the second contact hole.

[0013] In some embodiments, the top surface of the second main connection structure is flush with the top surface of the second dielectric layer; and the orthographic projection of the second main connection structure on the first dielectric layer is within the range of the orthographic projection of the extension portion on the first dielectric layer.

[0014] In some embodiments, the step of forming the second main connection structure includes depositing a second metal material and patterning the metal material to form a metal structure on the surface of the second dielectric layer that is in one-to-one contact with the second main connection structure.

[0015] In some embodiments, the first main connection structure and the second main connection structure are made of a first metal material, the first electrode layer, the second electrode layer and the metal structure are made of a second metal material, and the first metal material and the second metal material are different.

[0016] In some embodiments, a first auxiliary connection structure is formed simultaneously with the formation of the first main connection structure. The first auxiliary connection structure penetrates the first dielectric layer along the second direction and is spaced apart from the first main connection structure. A second auxiliary connection structure is formed simultaneously with the formation of the second main connection structure. The second auxiliary connection structure penetrates the second dielectric layer along the second direction and contacts the first auxiliary connection structure. One of the metal structures is also in contact with an adjacent second auxiliary connection structure.

[0017] In order to solve the above problems, the present invention also provides a three-dimensional memory, comprising: a substrate; a first dielectric layer covering the surface of the substrate; a first main connection structure penetrating the first dielectric layer along a second direction and arranged at intervals along the first direction, wherein the first direction is parallel to the substrate surface and the second direction is perpendicular to the substrate surface; a first electrode layer formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure; a storage layer covering at least one side wall of the first electrode layer and having an extension extending to the surface of the first dielectric layer; a second electrode layer covering the storage layer, and the maximum thickness of the second electrode layer in the second direction is greater than the thickness of the first electrode layer, wherein the first electrode layer, the storage layer, and the second electrode layer constitute storage cells of the three-dimensional memory; a second dielectric layer covering the first dielectric layer and all the storage cells; and a second main connection structure penetrating the second dielectric layer along the second direction and in contact with the second electrode layer.

[0018] In some embodiments, the first main connection structure and the second main connection structure are made of a first metal material, the first electrode layer and the second electrode layer are made of a second metal material, and the first metal material and the second metal material are different.

[0019] In some embodiments, the material of the storage layer is a ferroelectric material or a phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the materials of the first main connection structure and the second main connection structure are both metal tungsten, and the materials of the first electrode layer and the second electrode layer are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

[0020] In some embodiments, the three-dimensional memory further includes: a metal structure formed on the surface of the second dielectric layer and in one-to-one contact with the second main connection structure, wherein the metal structure is made of the same material as the second electrode layer and different from the material of the second main connection structure.

[0021] In some embodiments, the three-dimensional memory further includes: a first auxiliary connection structure, formed using the same process as the first main connection structure, the first auxiliary connection structure penetrating the first dielectric layer along the second direction and spaced apart from the first main connection structure in the first direction; a second auxiliary connection structure, formed using the same process as the second main connection structure, the second auxiliary connection structure penetrating the second dielectric layer along the second direction and contacting the first auxiliary connection structure; wherein one of the metal structures is also in contact with an adjacent second auxiliary connection structure.

[0022] The above technical solution optimizes the traditional horizontal memory cell into a vertical memory cell by optimizing the upper and lower electrode layers into left and right electrode layers. This increases the effective area of ​​each memory cell, allowing for a smaller area and saving on the memory cell footprint. This increase in device effective area improves memory performance and optimizes device operating efficiency and reliability. Furthermore, the vertical memory cell configuration ensures that even if a protrusion in the first main connection structure in contact with the first electrode layer is formed during the formation of the first main connection structure, this does not affect the deposition and phase change properties of the memory layer, thereby avoiding any impact on the memory cell performance. Furthermore, when forming the second electrode layer, etching through the memory layer is eliminated, further avoiding any impact on the memory cell performance. Furthermore, only two contact hole photomask processes are required, eliminating one contact hole photomask process, effectively reducing production costs. This invention addresses the prior art issue of reducing the effective area of ​​the memory layer and electrode layer of the memory cell as semiconductor process technology shrinks, thereby reducing the storage performance of the memory device. It also eliminates the need for a photomask process, effectively reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic diagram of the device structure of a memory in the prior art;

[0025] Figure 2 A schematic diagram of the steps of a method for preparing a three-dimensional memory according to an embodiment of the present invention;

[0026] Figures 3 to 6 A schematic diagram of the device structure of a semiconductor substrate provided by one embodiment of the present invention;

[0027] Figures 7 to 10 A schematic diagram of a device structure for forming a storage layer and a second electrode layer according to an embodiment of the present invention;

[0028] Figure 11 A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention;

[0029] Figure 12-13 A schematic diagram of a device structure for forming a second main connection structure according to an embodiment of the present invention;

[0030] Figure 14 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0032] See also Figure 1 , which is a schematic diagram of the device structure of the memory in the prior art. Figure 1 As shown, the existing memory includes: a supporting layer 10, a first dielectric layer 111 formed on the supporting layer 10, a first connecting structure 121 formed in the first dielectric layer 111, a second dielectric layer 112 formed on the first dielectric layer 111, a first conductive structure 131 formed in the second dielectric layer 112 and in contact with the first connecting structure 121, a second connecting structure 122 formed in the second dielectric layer 112 and in contact with the first conductive structure 131, a storage unit 14 formed on the second dielectric layer 112 and in contact with the second connecting structure 122, a third dielectric layer 113 covering the second dielectric layer 112 and covering the storage unit 14, a third connecting structure 123 formed in the third dielectric layer 113 and in contact with the storage unit 14, and a second conductive structure 132 formed on the surface of the third dielectric layer 113 and in contact with the third connecting structure 123. The memory cell 14 is composed of a lower electrode layer, a middle memory layer, and an upper electrode layer. The support layer 10 may be a substrate, the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 may be corresponding dielectric layers, and the first conductive structure 131 and the second conductive structure 132 may be corresponding metal structures.

[0033] The storage performance of the memory cell 14 is proportional to the effective area of ​​the storage layer and electrode layer. However, as semiconductor manufacturing processes shrink, the area of ​​the storage layer and electrode layer decreases, resulting in a reduction in the effective area of ​​the storage layer and electrode layer, which in turn affects the storage performance of the memory. Furthermore, when manufacturing this conventional memory, the preparation of the first connection structure 121, the second connection structure 122, and the third connection structure 123 requires three photomask processes, increasing production costs.

[0034] In order to solve the problem in the prior art that as the semiconductor process is miniaturized, the area of ​​the storage layer and electrode layer of the memory cell becomes smaller, resulting in a reduction in the effective area of ​​the storage layer and electrode layer, thereby affecting the storage performance of the memory, the present invention provides a three-dimensional (3D) structured three-dimensional memory and a preparation method thereof, which can save the occupied area of ​​the memory cell and increase the effective area of ​​the device, thereby improving the storage performance, optimizing and enhancing the operating efficiency and reliability of the device, and can also save on mask processes and reduce production costs.

[0035] An embodiment of the present invention provides a method for manufacturing a three-dimensional memory.

[0036] Please also refer to Figures 2 to 14 ,in, Figure 2 A schematic diagram of the steps of a method for preparing a three-dimensional memory according to an embodiment of the present invention; Figures 3 to 6 A schematic diagram of the device structure of a semiconductor substrate provided by one embodiment of the present invention; Figures 7 to 10 A schematic diagram of a device structure for forming a storage layer and a second electrode layer according to an embodiment of the present invention; Figure 11 A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention; Figure 12-13 A schematic diagram of a device structure for forming a second main connection structure according to an embodiment of the present invention; Figure 14 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention.

[0037] like Figure 2 As shown, the method for preparing a three-dimensional memory described in this embodiment includes the following steps: S21, forming a semiconductor substrate, the semiconductor substrate including a substrate, a first dielectric layer covering a surface of the substrate, first main connection structures extending through the first dielectric layer in a second direction and spaced apart along the first direction, and a first electrode layer formed on a surface of the first dielectric layer and in one-to-one contact with the first main connection structures; S22, forming a storage layer and a second electrode layer, the storage layer covering at least a sidewall of the first electrode layer and having an extension extending to a surface of the first dielectric layer, the second electrode layer covering the storage layer, and a maximum thickness of the second electrode layer in the second direction being greater than a thickness of the first electrode layer, wherein the first electrode layer, the storage layer, and the second electrode layer constitute storage cells of the three-dimensional memory; S23, forming a second dielectric layer, the second dielectric layer covering the first dielectric layer and all the storage cells; and S24, forming a second main connection structure, the second main connection structure extending through the second dielectric layer in the second direction and in contact with the second electrode layer.

[0038] Please refer to step S21 and Figure 6, forming a semiconductor substrate, the semiconductor substrate including a substrate 30, a first dielectric layer 31 covering the surface of the substrate 30, first main connection structures 321 extending through the first dielectric layer 31 along a second direction D2 and arranged at intervals along the first direction D1, and a first electrode layer 33 formed on the surface of the first dielectric layer 31 and in one-to-one contact with the first main connection structures 321. The first direction D1 is parallel to the surface of the substrate 30, and the second direction D2 is perpendicular to the surface of the substrate 30.

[0039] In this embodiment, the material of the first electrode layer 33 is different from the material of the first main connection structure 321 .

[0040] In this embodiment, the steps of forming a semiconductor substrate specifically include: (1) providing a substrate 30, wherein the first dielectric layer 31 is formed on the surface of the substrate 30, and the first contact holes 320 are formed in the first dielectric layer 31 along the second direction D2 and penetrate the first dielectric layer 31 and are arranged at intervals along the first direction D1. Figure 3 (2) Filling the first contact hole 320 with a first metal material to form the first main connection structure 321, as shown. Figure 4 (3) Depositing and patterning a second metal material to form the first electrode layer 33 on the surface of the first dielectric layer 31 in one-to-one contact with the first main connection structure 321, as shown. Figure 6 Specifically, the second metal material is different from the first metal material.

[0041] In this embodiment, the steps of depositing and patterning the second metal material specifically include: (31) depositing a second metal material layer 330 on the surface of the first dielectric layer 31, and forming a patterned first protective layer 38 on the surface of the second metal material layer 330, such as Figure 5 As shown; (32) using the patterned first protective layer 38 as a mask and the first dielectric layer 31 as an etching stop layer, etching the second metal material layer 330 to form the first electrode layer 33 in one-to-one contact with the first main connection structure 321, and the first protective layer 38 is retained and covered on the surface of the first electrode layer 33, as shown Figure 6 The second metal material layer 330 can be deposited and grown by atomic layer deposition (ALD).

[0042] In this embodiment, the material of the first dielectric layer 31 can be an oxide (OX) material, such as silicon oxide (SiO). The material of the first main connecting structure 321 can be tungsten. The material of the first electrode layer 33 is selected from aluminum, copper, or an aluminum-copper alloy, preferably an aluminum-copper alloy. Aluminum-copper alloys are relatively hard and generally consist of 97% aluminum and 3% copper. Aluminum-copper alloys have similar chemical properties to aluminum metal, are lightweight, and have high tensile strength, making them suitable for replacing expensive copper wire. The material of the first protective layer 38 can be an oxynitride, such as silicon oxynitride (SiON).

[0043] In this embodiment, a gate structure 39 is further formed on the surface of the substrate 30. The first dielectric layer 31 further covers the gate structure 39. The first main connection structure 321 is disposed on both sides of the gate structure 39 along the first direction D1. The gate structure 39 includes a polysilicon gate 391, a gate oxide layer 392 located below the polysilicon gate 391, and sidewall spacers 393 located on the sidewalls of the polysilicon gate 391. Figure 3 shown.

[0044] In this embodiment, the top surface of the first main connection structure 321 is flush with the top surface of the first dielectric layer 31 .

[0045] In this embodiment, the first electrode layer 33 is in one-to-one contact with the first main connection structure 321 , and a plurality of first electrode layers 33 are disposed on the surface of the first dielectric layer 31 at intervals.

[0046] Please refer to step S22 and Figure 10 , forming a storage layer 41 and a second electrode layer 42, the storage layer 41 at least covering a side wall of the first electrode layer 33 and having an extension portion 411 extending to the surface of the first dielectric layer 31; the second electrode layer 42 covers the storage layer 41, and the maximum thickness H2 of the second electrode layer 42 in the second direction D2 is greater than the thickness H1 of the first electrode layer 33; wherein the first electrode layer 33, the storage layer 41, and the second electrode layer 42 constitute a storage unit of the three-dimensional memory.

[0047] In this embodiment, the steps of forming the storage layer 41 and the second electrode layer 42 specifically include: (1) depositing a storage material to form a storage material layer 410 covering the first dielectric layer 31 and all of the first electrode layer 33, such as Figure 7 (2) depositing a second metal material to form a second electrode material layer 420 covering the storage material layer 410, wherein the maximum thickness H2 of the second electrode material layer 420 in the second direction D2 is greater than the thickness H1 of the first electrode layer 33; Figure 8(3) A patterned second protective layer 43 is formed on the surface of the second electrode material layer 420. The patterned second protective layer 43 can at least block a side wall of the first electrode layer 33 and a portion of the first dielectric layer 31 corresponding to the side wall, as shown. Figure 9 (4) Using the patterned second protective layer 43 as a mask and the first dielectric layer 31 as an etching stop layer, the second electrode material layer 420 and the storage material layer 410 are etched, the remaining storage material layer 410 is etched to form the storage layer 41, and the remaining second electrode material layer 420 is etched to form the second electrode layer 42. The second protective layer 43 is retained and covers the surface of the second electrode layer 42, as shown. Figure 10 shown.

[0048] In this embodiment, the patterned second protective layer 43 can also shield the corresponding area on the top surface of the first electrode layer 33; the storage layer 41 also covers the top surface of the first electrode layer 33; and the second electrode layer 42 completely covers the storage layer 41. Specifically, when the first protective layer 38 is located on the top surface of the first electrode layer 33, the storage layer 41 completely covers the top surface of the first protective layer 38 located on the top surface of the first electrode layer 33.

[0049] In some embodiments, the storage material layer 410 may be deposited and grown using maskless atomic layer deposition (ALD). The material of the storage layer 41 is a ferroelectric material or a phase change material. The material of the second protective layer 43 may be a nitride oxide, such as silicon oxynitride (SiON).

[0050] In this embodiment, the second electrode layer 42 and the first electrode layer 33 are arranged in pairs, forming a vertical (along the direction D2 in the figure) memory cell with the intermediate memory layer 41, which can save the occupied area of ​​the memory cell and increase the effective area of ​​the device. The arrangement of the vertical memory cell in this embodiment makes it possible to avoid the problem of etching through the memory layer when forming the second main connection structure 361 (upper contact hole process), thereby further avoiding affecting the performance of the memory cell. And compared to Figure 1 The present embodiment only requires two dielectric layers and two contact hole (VIA) mask processes, which saves one contact hole mask process and can effectively reduce production costs.

[0051] In this embodiment, a plurality of memory cells are formed and distributed at intervals, and adjacent memory cells are separated by a second dielectric layer 35 formed subsequently.

[0052] Please refer to step S23 and Figure 11, forming a second dielectric layer 35 , wherein the second dielectric layer 35 covers the first dielectric layer 31 and all the storage units.

[0053] The material of the second dielectric layer 35 may be the same as that of the first dielectric layer 31 , both being oxide (OX) materials, for example, both being silicon oxide (SiO).

[0054] Please refer to step S24 and Figure 13 , forming a second main connection structure 361 , wherein the second main connection structure 361 penetrates the second dielectric layer 35 along the second direction D2 and contacts the second electrode layer 42 .

[0055] In this embodiment, the material of the second main connection structure 361 can be the same as that of the first main connection structure 321 , such as metal tungsten. The material of the second main connection structure 361 is different from that of the first electrode layer 33 and the second electrode layer 42 .

[0056] In this embodiment, the top surface of the second main connection structure 361 is flush with the top surface of the second dielectric layer 35. The orthographic projection of the second main connection structure 361 on the first dielectric layer 31 is within the range of the orthographic projection of the extension portion 411 on the first dielectric layer 31.

[0057] In this embodiment, the step of forming the second dielectric layer 35 includes: forming an etching stop layer 50, the etching stop layer 50 covers the first dielectric layer 31 and all the storage layer units, and the second dielectric layer 35 covers the etching stop layer 50. Accordingly, the step of forming the second main connection structure 361 specifically includes: (1) using the etching stop layer 50 as an etching stop layer, etching in the second dielectric layer 35 to form a second contact hole 350 exposing the second electrode layer 42, as shown in FIG. Figure 12 (2) depositing a first metal material and planarizing it to form the second main connection structure 361 in the second contact hole 350, as shown in FIG. Figure 13 shown.

[0058] like Figure 14 As shown, in this embodiment, the step of forming the second main connection structure 361 includes depositing a second metal material and patterning it to form a metal structure 37 on the surface of the second dielectric layer 35 that is in one-to-one contact with the second main connection structure 361. The metal structure 37 is made of the same material as the first electrode layer 33, but different from the material of the second main connection structure 361. The metal structure 37 serves as a lead structure or a pad.

[0059] In this embodiment, a first auxiliary connection structure 322 is formed simultaneously with the formation of the first main connection structure 321. The first auxiliary connection structure 322 penetrates the first dielectric layer 31 along the second direction D2 and is spaced apart from the first main connection structure 321 in the first direction D1. A second auxiliary connection structure 362 is also formed simultaneously with the formation of the second main connection structure 361. The second auxiliary connection structure 362 penetrates the second dielectric layer 35 along the second direction D2 and contacts the first auxiliary connection structure 322. One of the metal structures 37 is also in contact with an adjacent second auxiliary connection structure 362, such as Figure 14 shown.

[0060] The memory cell of the three-dimensional memory prepared in this embodiment optimizes the upper and lower electrode layers into left and right electrode layers, thereby realizing the transformation of the traditional lateral memory cell (Cell) (such as Figure 1 The memory cell 14 shown is optimized as a longitudinal memory cell (along the direction D2 shown in the figure). The effective area of ​​a single memory cell is increased, and a smaller footprint of a single memory cell can be achieved to save the area occupied by the memory cell. The increase in the effective area of ​​the device can improve the storage performance and optimize the operating efficiency and reliability of the device. Moreover, the arrangement of the longitudinal memory cell in this embodiment makes it possible that when forming the first main connection structure 321 (lower contact hole process), even if the lower contact hole process causes a protrusion in the first main connection structure 321 in contact with the first electrode layer 33 (the left electrode layer shown in the figure), it will not affect the deposition and phase change performance of the memory layer 41, thereby avoiding affecting the performance of the memory cell; and when forming the second main connection structure 361 (upper contact hole process), there is no problem of etching through the memory layer 41, thereby further avoiding affecting the performance of the memory cell. And compared to Figure 1 While the conventional method requires three dielectric layers and three contact hole (VIA) mask processes, this embodiment only requires two dielectric layers and two contact hole (VIA) mask processes, eliminating one contact hole mask process and effectively reducing production costs. This embodiment solves the problem in the prior art where, as semiconductor process scaling decreases, the area of ​​the memory cell's storage layer and electrode layer decreases, resulting in a reduction in the effective area of ​​the storage layer and electrode layer, which in turn affects the memory performance. Furthermore, it eliminates the mask process and effectively reduces production costs.

[0061] Based on the same inventive concept, the present invention also provides a three-dimensional memory prepared by the above method of the present invention.

[0062] See also Figures 3 to 14The three-dimensional memory device of this embodiment includes a substrate 30, a first dielectric layer 31, a first main connection structure 321, a first electrode layer 33, a storage layer 41, a second electrode layer 42, a second dielectric layer 35, and a second main connection structure 361. The first electrode layer 33, the storage layer 41, and the second electrode layer 42 constitute a storage cell of the three-dimensional memory device.

[0063] In this embodiment, the first main connection structure 321 and the second main connection structure 361 are made of a first metal material, the first electrode layer 33 and the second electrode layer 42 are made of a second metal material, and the first metal material and the second metal material are different.

[0064] Specifically, the first dielectric layer 31 covers the surface of the substrate 30. The material of the first dielectric layer 31 can be an oxide (OX) material, such as silicon oxide (SiO).

[0065] Specifically, the first main connection structures 321 extend through the first dielectric layer 31 along the second direction D2 and are spaced apart along the first direction D1. The first direction D1 is parallel to the surface of the substrate 30, and the second direction D2 is perpendicular to the surface of the substrate 30. The first main connection structures 321 are made of tungsten metal. The top surfaces of the first main connection structures 321 are flush with the top surface of the first dielectric layer 31.

[0066] Specifically, the first electrode layer 33 is formed on the surface of the first dielectric layer 31 and is in one-to-one contact with the first main connection structure 321. Multiple first electrode layers 33 are spaced apart and arranged on the surface of the first dielectric layer 31. The material of the first electrode layer 33 is selected from aluminum, copper, or an aluminum-copper alloy, preferably an aluminum-copper alloy.

[0067] Specifically, the storage layer 41 covers a side wall of the first electrode layer 33 and has an extension portion 411 extending to the surface of the first dielectric layer 31. The storage layer 41 also covers the top surface of the first electrode layer 33. Specifically, the storage layer 41 includes an extension portion 411 extending to the surface of the first dielectric layer 31, a first covering portion 412 covering a side wall of the first electrode layer 33, and a second covering portion 413 covering the top surface of the first electrode layer 33. Figure 10 The material of the storage layer 41 is a ferroelectric material or a phase change material.

[0068] Specifically, the second electrode layer 42 covers the storage layer 41, and the maximum thickness H2 of the second electrode layer 42 in the second direction D2 is greater than the thickness H1 of the first electrode layer 33. Specifically, the second electrode layer 42 completely covers the storage layer 41. The first electrode layer 33, the storage layer 41, and the second electrode layer 42 are arranged along the first direction D1 to form a vertical storage cell of the three-dimensional memory. The material of the second electrode layer 42 is selected from aluminum, copper, or an aluminum-copper alloy, preferably an aluminum-copper alloy.

[0069] Specifically, the second dielectric layer 35 covers the first dielectric layer 31 and all the memory cells. The material of the second dielectric layer 35 can be the same as that of the first dielectric layer 31, both being oxide (OX) materials, such as silicon oxide (SiO).

[0070] Specifically, the second main connection structure 361 penetrates the second dielectric layer 35 along the second direction D2 and contacts the second electrode layer 42. The material of the second main connection structure 361 can be metal tungsten.

[0071] In this embodiment, the top surface of the second main connection structure 361 is flush with the top surface of the second dielectric layer 35. The orthographic projection of the second main connection structure 361 on the first dielectric layer 31 is within the range of the orthographic projection of the extension portion 411 on the first dielectric layer 31.

[0072] In this embodiment, a gate structure 39 is further formed on the surface of the substrate 30. The first dielectric layer 31 further covers the gate structure 39. First main connection structures 321 are disposed along a first direction D1 on both sides of the gate structure 39. The gate structure 39 includes a polysilicon gate 391, a gate oxide layer 392 located below the polysilicon gate 391, and sidewall spacers 393 located on the sidewalls of the polysilicon gate 391.

[0073] In this embodiment, the material of the storage layer 41 is a ferroelectric material or a phase change material; the materials of the first dielectric layer 31 and the second dielectric layer 35 are both oxide materials; the material of the first main connection structure 321 and the second main connection structure 361 is metal tungsten; the material of the first electrode layer 33 and the second electrode layer 42 is the same, and both are selected from one of aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy.

[0074] In this embodiment, the three-dimensional memory further includes: a first protective layer 38 covering the surface of the first electrode layer 33; and a second protective layer 43 covering the surface of the second electrode layer 42. The materials of the first protective layer 38 and the second protective layer 43 can be nitride oxide, such as silicon oxynitride (SiON).

[0075] In this embodiment, the three-dimensional memory device further includes a metal structure 37 formed on the surface of the second dielectric layer 35 and in one-to-one contact with the second main connection structure 361. The metal structure 37 serves as a lead structure or pad. The metal structure 37 is made of the same material as the first electrode layer 33, but different from the material of the second main connection structure 361.

[0076] In this embodiment, the three-dimensional memory further includes: a first auxiliary connection structure 322, which is formed using the same process as the first main connection structure 321, and penetrates the first dielectric layer 31 along the second direction D2 and is spaced apart from the first main connection structure 321 in the first direction D1. A second auxiliary connection structure 362, which is formed using the same process as the second main connection structure 361, and penetrates the second dielectric layer 35 along the second direction D2 and contacts the first auxiliary connection structure 322. One of the metal structures 37 also contacts an adjacent second auxiliary connection structure 362, such as Figure 14 shown.

[0077] In the above description, descriptions of well-known components and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to in detail.

[0078] It should be noted that, in this article, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also includes other elements not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the element defined by the sentence "also includes a..." does not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without conflict.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: The method comprises the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a first dielectric layer covering the surface of the substrate, a first main connection structure penetrating the first dielectric layer along a second direction and arranged at intervals along the first direction, and a first electrode layer formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure, wherein the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface; forming a storage layer and a second electrode layer, wherein the storage layer at least covers a side wall of the first electrode layer and has an extension extending to the surface of the first dielectric layer, the material of the storage layer is a phase change material, the second electrode layer covers the storage layer, and the maximum thickness of the second electrode layer in the second direction is greater than the thickness of the first electrode layer, wherein the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory, and the first electrode layer and The second electrode layer is an asymmetric structure, and the storage unit is a phase change storage unit; a second dielectric layer is formed, and the second dielectric layer covers the first dielectric layer and all the storage units; and a second main connection structure is formed, and the second main connection structure penetrates the second dielectric layer along the second direction and contacts the second electrode layer; a second metal material is deposited and patterned to form a metal structure on the surface of the second dielectric layer that contacts the second main connection structure one-to-one; a first auxiliary connection structure is formed while forming the first main connection structure, and the first auxiliary connection structure penetrates the first dielectric layer along the second direction and is spaced apart from the first main connection structure; a second auxiliary connection structure is formed while forming the second main connection structure, and the second auxiliary connection structure penetrates the second dielectric layer along the second direction and contacts the first auxiliary connection structure; wherein one of the metal structures is also in contact with an adjacent second auxiliary connection structure.

2. The method according to claim 1, characterized in that The first main connection structure and the second main connection structure are made of a first metal material, the first electrode layer and the second electrode layer are made of a second metal material, and the first metal material is different from the second metal material.

3. The method according to claim 1, characterized in that The materials of the first dielectric layer and the second dielectric layer are both oxide materials, the materials of the first main connection structure and the second main connection structure are both metal tungsten, and the materials of the first electrode layer and the second electrode layer are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

4. The method according to claim 1, characterized in that The steps of forming a semiconductor substrate specifically include: providing a substrate, the first dielectric layer being formed on the surface of the substrate, the first dielectric layer having first contact holes formed in the first dielectric layer and penetrating the first dielectric layer along the second direction and arranged at intervals along the first direction; filling the first contact hole with a first metal material to form the first main connection structure; depositing a second metal material and patterning it to form the first electrode layer on the surface of the first dielectric layer, which is in one-to-one contact with the first main connection structure.

5. The method according to claim 4, characterized in that The steps of depositing and patterning the second metal material specifically include: depositing a second metal material layer on the surface of the first dielectric layer; forming a patterned first protective layer on the surface of the second metal material layer; etching the second metal material layer using the patterned first protective layer as a mask and the first dielectric layer as an etching stop layer to form the first electrode layer that is in one-to-one contact with the first main connection structure, and the first protective layer is retained and covers the surface of the first electrode layer.

6. The method according to claim 1, characterized in that The steps of forming the storage layer and the second electrode layer specifically include: depositing a storage material to form a storage material layer covering the first dielectric layer and all the first electrode layers; depositing a second metal material to form a second electrode material layer covering the storage material layer, wherein the maximum thickness of the second electrode material layer in the second direction is greater than the thickness of the first electrode layer; forming a patterned second protective layer on the surface of the second electrode material layer, wherein the patterned second protective layer can at least shield a side wall of the first electrode layer and a portion of the first dielectric layer corresponding to the side wall; etching the second electrode material layer and the storage material layer using the patterned second protective layer as a mask and the first dielectric layer as an etching stop layer, etching the remaining storage material layer to form the storage layer, etching the remaining second electrode material layer to form the second electrode layer, and retaining and covering the surface of the second electrode layer.

7. The method according to claim 6, characterized in that The patterned second protection layer can also shield the corresponding area of ​​the top surface of the first electrode layer; the storage layer also covers the top surface of the first electrode layer, and the second electrode layer completely covers the storage layer.

8. The method according to claim 1, characterized in that The step of forming the second dielectric layer includes: forming an etching barrier layer, the etching barrier layer covers the first dielectric layer and all the storage units, and the second dielectric layer covers the etching barrier layer; the step of forming the second main connection structure specifically includes: using the etching barrier layer as an etching stop layer, etching in the second dielectric layer to form a second contact hole exposing the second electrode layer; depositing a first metal material and planarizing it to form the second main connection structure in the second contact hole.

9. The method according to claim 1, characterized in that: The top surface of the second main connection structure is flush with the top surface of the second dielectric layer; the orthographic projection of the second main connection structure on the first dielectric layer is located within the range of the orthographic projection of the extension portion on the first dielectric layer.

10. The method according to claim 1, characterized in that The first main connection structure and the second main connection structure are made of a first metal material, the first electrode layer, the second electrode layer and the metal structure are made of a second metal material, and the first metal material is different from the second metal material.

11. A three-dimensional memory, characterized in that: include: substrate; A first dielectric layer, covering the surface of the substrate; A first main connection structure penetrates the first dielectric layer along a second direction and is arranged at intervals along the first direction, wherein the first direction is parallel to the substrate surface and the second direction is perpendicular to the substrate surface; a first electrode layer is formed on the surface of the first dielectric layer and is in one-to-one contact with the first main connection structure; a storage layer covers at least one side wall of the first electrode layer and has an extension extending to the surface of the first dielectric layer, and the material of the storage layer is a phase change material; a second electrode layer covers the storage layer, and the maximum thickness of the second electrode layer in the second direction is greater than the thickness of the first electrode layer, wherein the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory, the first electrode layer and the second electrode layer are asymmetric structures, and the storage unit is a phase change A storage unit; a second dielectric layer covering the first dielectric layer and all the storage units; and a second main connection structure penetrating the second dielectric layer along the second direction and in contact with the second electrode layer; a metal structure formed on the surface of the second dielectric layer and in one-to-one contact with the second main connection structure; a first auxiliary connection structure formed by the same process as the first main connection structure, the first auxiliary connection structure penetrating the first dielectric layer along the second direction and spaced from the first main connection structure in the first direction; a second auxiliary connection structure formed by the same process as the second main connection structure, the second auxiliary connection structure penetrating the second dielectric layer along the second direction and in contact with the first auxiliary connection structure; wherein one of the metal structures is also in contact with an adjacent second auxiliary connection structure.

12. The three-dimensional memory according to claim 11, characterized in that: The first main connection structure and the second main connection structure are made of a first metal material, the first electrode layer and the second electrode layer are made of a second metal material, and the first metal material is different from the second metal material.

13. The three-dimensional memory according to claim 11, characterized in that: The materials of the first dielectric layer and the second dielectric layer are both oxide materials, the materials of the first main connection structure and the second main connection structure are both metal tungsten, and the materials of the first electrode layer and the second electrode layer are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

14. The three-dimensional memory according to claim 11, characterized in that: The metal structure is made of the same material as the second electrode layer, but is different from the second main connection structure.

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