Method for improving flatness of dsg processed silicon wafer
By optimizing the NT calculation logic and processing parameters, the problem of unstable flatness of DSG silicon wafers was solved, improving the flatness control accuracy and ease of operation of silicon wafers, and meeting the high flatness requirements of integrated circuit manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 杭州中欣晶圆半导体股份有限公司
- Filing Date
- 2024-08-06
- Publication Date
- 2026-05-29
AI Technical Summary
In existing technologies, the flatness of silicon wafers processed by DSG is unstable, resulting in poor operability and making it difficult to meet the high flatness requirements of integrated circuit manufacturing processes.
By using NT calculation logic to control the PV value within the pixel, adjusting the silicon wafer shape and grinding wheel direction, and optimizing DSG processing parameters such as cooling water flow rate and barometer accuracy, the flatness of the silicon wafer surface is ensured, including trough-type cleaning machine cleaning and grinding wheel tilt angle control.
This achieves stability and ease of operation for silicon wafer flatness, reduces the occurrence of flatness defects, and improves the control accuracy of flatness parameters.
Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon wafer processing technology, and more specifically to a method for improving the flatness of silicon wafers processed by DSG. Background Technology
[0002] As the linewidth of integrated circuit processes continues to shrink, the requirements for the flatness of silicon wafer surfaces in integrated circuit manufacturing processes are becoming increasingly stringent. The surface condition of silicon wafers caused by pre-polishing processes has a significant impact on the final flatness parameters such as SFQR, ESFQR, and NT level, especially the DSG process. Silicon wafers processed by DSG have two characteristics: a central bulge or depression and an outer ring shape.
[0003] The reason for these two characteristics is the processing principle of the machine itself. During double-sided grinding of silicon wafers, the depth and distribution of the grinding wheel teeth on the silicon wafer surface affect the surface roughness of the silicon wafer, and the movement trajectory of the teeth on the silicon wafer affects the flatness of the silicon wafer. The cooling water flow rate of the machine affects the grinding rate of the teeth, and the shape of the silicon wafer after wire cutting affects the fit between the teeth and the silicon wafer during processing.
[0004] The existing processing method involves changing the grinding position, adjusting the zero point of the air gauge and setting the tilt angle, and then confirming the zero point adjustment using the air gauge. Because the shape and morphology of silicon wafers are inconsistent, frequent adjustments to the grinding position and tilt angle are required, which greatly reduces the operability during processing.
[0005] During DSG processing of silicon wafers, the grinding texture density gradually decreases along the radial direction of the wafer, increasing towards the center. Therefore, the surface shape of the processed wafers is mostly a bowl shape. The grinding position is adjusted by the zero point of a barometer to change the tilt angle. The movement trajectory of the grinding teeth on the wafer, the machine's cooling water flow rate, and the shape of the wafer after wire cutting all affect the flatness of the wafer after DSG. DSG stands for Double Side Grinding, a silicon wafer processing technique. Summary of the Invention
[0006] This invention primarily addresses the shortcomings of existing technologies by providing a method for improving the flatness of silicon wafers processed using DSG (Digital Sequencing). This method offers advantages such as ease of operation and high stability. It solves the problem of unstable flatness variables in silicon wafers after DSG processing. It effectively reduces flatness defects caused by DSG processing, achieving a significant improvement in flatness parameters.
[0007] The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions:
[0008] A method for improving the flatness of silicon wafers processed by DSG includes the following steps:
[0009] Step 1: Find ways to improve the PV value within a pixel by using NT calculation logic.
[0010] Step 2: Controlling the shape of silicon wafers after wire cutting. The shape of silicon wafers after wire cutting of a single batch is consistent, and the overall shape is potato chip-shaped with the same bending direction.
[0011] Step 3: Pre-processing of silicon wafers with DSG. First, clean the silicon wafers with a tank cleaning machine to eliminate stress.
[0012] Step 4: The left grinding wheel rotates in the same direction as the carrier ring, while the right grinding wheel rotates in the opposite direction. The speed ratio between the grinding wheel and the carrier ring is 4000 / 30. Adjust the grinding position so that the left and right air pressure count values and displacement values are consistent to ensure that the front of the silicon wafer shows a complete grinding wheel mark. Then, the silicon wafer is processed by DSG.
[0013] Step 5: Post-processing of silicon wafer DSG, using Kuroda 300tt to measure the diameter profile change of the silicon wafer, and controlling the PV value of special morphology to be within 5um.
[0014] Preferably, the NT calculation logic uses each pixel contained within the FQA region to define a window of a certain size centered on that pixel, and uses the PV of the NT height of all pixels contained within the window as the SQA value THA@0.05% for that pixel; the FQA region, or Fixed Quality Area, is called the quality assurance area, which is the majority of the central part of the wafer surface.
[0015] Preferably, the SQA values of each pixel in the SQA Map are sorted from largest to smallest, and the total number of valid pixels N is recorded. The target THA sequence position m is calculated as: a specified percentage (0.05%) × the total number of valid pixels N. The target position m is then indexed according to the SQA sorting sequence to obtain the target THA@0.05% value. SQA: Surface quality analysis. The SQA Map is a surface quality analysis map.
[0016] Preferably, bending is controlled within ±2µm, torsional deformation within 7µm, silicon wafer diameter variation is less than 3µm per 50mm, LBW cross-sectional variation rate is less than 3µm, and the LBW measurement direction is consistent with the tangential direction. LBW refers to the equipment model, flatness measuring instrument LBW-3020FR.
[0017] Preferably, the silicon wafer diameter variation is less than 3 micrometers per 50 millimeters as measured by LBW before DSG processing.
[0018] As a preferred option, the cooling water flow rate is controlled at 1.5 to 1.8 L / min during DSG processing.
[0019] As a preferred option, the DSP machine tool adjusts the disk shape according to the morphology after DSG processing, and the amount of material removed during processing is guaranteed to be above 14.5um.
[0020] As a preferred option, the grinding wheel angle should not be tilted in one direction for an extended period of time. Grinding and alignment should be performed after processing 2000 pieces per cycle to avoid leaving any un-ground areas. The verticality of the machine's static pressure plate and the accuracy of the barometer should be calibrated every 3 months.
[0021] The present invention can achieve the following effects:
[0022] This invention provides a method for improving the flatness of silicon wafers processed by DSG (Diverterless Steel Gear). Compared with existing technologies, it has the advantages of convenient operation and good operational stability. It solves the problem of unstable flatness variables in silicon wafers after DSG processing. It effectively reduces flatness defects caused by DSG processing and achieves effective improvement in flatness parameters. Detailed Implementation
[0023] The technical solution of the invention will be further described in detail below through examples.
[0024] Example: A method for improving the flatness of silicon wafers processed by DSG, comprising the following steps:
[0025] Step 1: Find ways to improve the PV value within a pixel by using NT calculation logic.
[0026] The NT calculation logic uses each pixel contained within the FQA region as the center of a window of a defined size. The PV of the NT height of all pixels contained within the window is used as the SQA value THA@0.05% for that pixel. The FQA region, or Fixed Quality Area, is the majority of the central part of the wafer surface. The SQA values of each pixel within the SQA Map are sorted from largest to smallest, and the total number of valid pixels N is recorded. The specified percentage (0.05%) × the total number of valid pixels N = the target THA sequence position m is calculated. The target position m is indexed according to the SQA sorting sequence to obtain the target THA@0.05% value.
[0027] Step 2: Controlling the shape of silicon wafers after wire cutting. Each batch of wire-cut silicon wafers should have a consistent shape, exhibiting a potato chip-like shape with consistent bending direction. Bending should be controlled within ±2µm, torsional deformation within 7µm, the wafer diameter variation per 50mm should be less than 3µm, the LBW cross-sectional change rate should be less than 3µm, and the LBW measurement direction should be consistent with the wire cutting direction.
[0028] Step 3: Before DSG processing, the diameter of the silicon wafer is measured using LBW to ensure that the variation is less than 3 micrometers per 50 mm. The silicon wafer undergoes pre-processing DSG treatment, first being cleaned with a tank-type cleaning machine to eliminate stress on the wafer.
[0029] Step 4: The left grinding wheel rotates in the same direction as the carrier ring, while the right grinding wheel rotates in the opposite direction. The speed ratio between the grinding wheel and the carrier ring is 4000 / 30. Adjust the grinding position until the left and right air pressure count values and displacement values are consistent. Then, the silicon wafer undergoes DSG processing. During DSG processing, the cooling water flow rate is controlled at 1.5–1.8 L / min.
[0030] Step 5: Post-processing of silicon wafers via DSG. The diameter profile variation of the silicon wafer is measured using a Kuroda 300tt, and the PV value for special morphologies is controlled to be within 5µm. The DSP machine adjusts the disk shape according to the post-DSG morphology, ensuring a removal amount of at least 14.5µm.
[0031] The grinding wheel tilt angle should not be tilted in one direction for a long time. Grinding and alignment should be performed after processing 2000 pieces / time to avoid some areas not being ground. The verticality of the machine's static pressure plate and the accuracy of the barometer should be calibrated every 3 months.
[0032] In summary, this method for improving the flatness of silicon wafers processed by DSG has the advantages of convenient operation and good operational stability. It solves the problem of unstable flatness variables in silicon wafers after DSG processing. It effectively reduces flatness defects caused by DSG processing and achieves effective improvement in flatness parameters. The flatness parameters SFQR are controlled within 30µm, ESFQR within 50µm, NT2*2 within 4µm, and NT10*10 within 10µm.
[0033] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.
Claims
1. A method for improving the flatness of silicon wafers processed by DSG, characterized in that... The following steps are included: Step 1: Find ways to improve the PV value within a pixel by using NT calculation logic; The NT calculation logic uses each pixel contained within the FQA region as the center of a window of a defined size. The PV of the NT height of all pixels contained within the window is used as the SQA value THA@0.05% for that pixel. The FQA region, or Fixed Quality Area, is the majority of the central part of the wafer surface. The SQA values of each pixel in the SQA Map are sorted from largest to smallest, and the total number of valid pixels N is recorded. The specified percentage (0.05%) × the total number of valid pixels N = the target THA sequence position m is calculated. The target position m is indexed according to the SQA sorting sequence to obtain the target THA@0.05% value. Step 2: Controlling the shape of silicon wafers after wire cutting. The shape of silicon wafers after wire cutting of a single batch is consistent, and the overall shape is potato chip-shaped with the same bending direction. Step 3: Pre-processing of silicon wafers with DSG: First, clean the silicon wafers with a tank cleaning machine to eliminate stress. Step 4: The left grinding wheel rotates in the same direction as the carrier ring, and the right grinding wheel rotates in the opposite direction. The speed ratio between the grinding wheel and the carrier ring is 4000 / 30. Adjust the grinding position so that the left and right air pressure count values and displacement values are consistent. Then the silicon wafer is processed by DSG. Step 5: Post-processing of silicon wafer DSG, using Kuroda 300tt to measure the diameter profile change of the silicon wafer, and controlling the PV value of special morphology to be within 5um.
2. The method for improving the flatness of DSG-processed silicon wafers according to claim 1, characterized in that: Bending is controlled within ±2µm, torsional deformation is controlled within 7µm, the silicon wafer diameter changes by less than 3µm per 50mm, the LBW cross-section change rate is less than 3µm, and the LBW measurement direction is consistent with the line tangent direction.
3. The method for improving the flatness of DSG-processed silicon wafers according to claim 1, characterized in that: Before DSG processing, the diameter of the silicon wafer was measured by LBW to be less than 3 micrometers per 50 millimeters.
4. The method for improving the flatness of DSG-processed silicon wafers according to claim 1, characterized in that: During DSG machining, the cooling water flow rate is controlled at 1.5 to 1.8 L / min.
5. The method for improving the flatness of DSG-processed silicon wafers according to claim 1, characterized in that: The DSP machine adjusts the disk shape according to the morphology after DSG processing, and the amount of material removed during processing is guaranteed to be above 14.5um.
6. The method for improving the flatness of DSG-processed silicon wafers according to claim 1, characterized in that: The grinding wheel tilt angle should not be tilted in one direction for a long time. Grinding and alignment should be performed after processing 2000 pieces / time to avoid some areas not being ground. The verticality of the machine's static pressure plate and the accuracy of the barometer should be calibrated every 3 months.