Signal generating device, method, analog-digital hybrid test board and test machine

Abstract

The present application relates to a signal generating device, method, analog-to-digital hybrid test board and test machine, wherein the signal generating device comprises: an arbitrary waveform generator, a read-write control module, an external clock chip and a storage device; the external clock chip is used to output a sampling clock of a fixed frequency to a digital-to-analog conversion device; the read-write control module connects the arbitrary waveform generator and the storage device, and is used to read the original waveform from the storage device according to the received read request instruction, and return the read original waveform to the arbitrary waveform generator; the arbitrary waveform generator is used to resample the received original waveform to generate a reconstructed waveform matching the frequency of the sampling clock; wherein the reconstructed waveform is used for the digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip. By resampling the original waveform to generate a reconstructed waveform, the external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device, and the digital-to-analog conversion can also be completed, thereby improving the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a signal generating device, method, analog-digital hybrid testing board and testing machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to test various parameters of the device under test (DUT) to eliminate defective products and control the quality of semiconductor devices before they leave the factory. In analog testing, especially high-speed analog testing, the test signals transmitted to the device under test often have very high requirements for harmonics, signal-to-noise ratio, amplitude, signal frequency, etc. When the tester implements the IQ function, it is necessary to ensure the synchronization of the IQ channels.

[0003] The traditional test signal generation scheme is to adjust the sampling clock phase of the DAC (digital-to-analog converter) of the IQ channel by changing the frequency of the clock signal output by the clock circuit to synchronize the IQ channel. This method of outputting test signals by adjusting the DAC sampling clock phase has complex control logic, cumbersome operation, and low test efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a signal generating device, method, analog-to-digital hybrid test board and test machine that can improve test efficiency in order to address the above problems.

[0005] The first aspect of the present application provides a signal generating device, comprising: an arbitrary waveform generator, a read-write control module, an external clock chip and a storage device;

[0006] The external clock chip is used to output a sampling clock of a fixed frequency to the digital-to-analog conversion device;

[0007] The read-write control module is connected to the arbitrary waveform generator and the storage device, and is used to read the original waveform from the storage device according to the received read request instruction, and return the read original waveform to the arbitrary waveform generator;

[0008] The arbitrary waveform generator is used to resample the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock; wherein the reconstructed waveform is used by the digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0009] In one embodiment, the arbitrary waveform generator comprises:

[0010] A waveform request module, connected to the read-write control module and the waveform data processing module, used to send a read request instruction to the read-write control module, and send the original waveform returned by the read-write control module to the waveform data processing module;

[0011] The waveform data processing module is used to resample the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0012] In one embodiment, the arbitrary waveform generator further includes:

[0013] A synchronization control module is connected to the waveform data processing module and is used to cache the reconstructed waveform in an internal cache module and output the reconstructed waveform in the internal cache module after receiving a trigger signal.

[0014] In one embodiment, the waveform data processing module includes:

[0015] A calibration module, connected to the waveform request module, for calibrating the received original waveform and outputting calibrated waveform data;

[0016] The digital resampling module is connected to the calibration module and is used to perform resampling processing on the calibrated waveform data to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0017] In one of the embodiments, the calibration module includes at least one of a DC calibration module and an AC amplitude calibration module.

[0018] In one embodiment, the digital resampling module includes:

[0019] An input waveform data cache module is connected to the calibration module, the effective position calculation module and the effective data cache module, and is used to cache the calibrated waveform data, and send a start signal to the effective position calculation module when the number of cached data is greater than a set threshold number; and read the effective data corresponding to the effective position from the cached data according to the received read enable signal, and send the read effective data to the effective data cache module for caching;

[0020] The effective position calculation module is connected to the effective coefficient generation module, and is used to calculate according to the set step and initial phase after receiving the start signal, obtain effective position information and send it to the effective coefficient generation module, and send a read enable signal to the input waveform data cache module;

[0021] The effective coefficient generation module is connected to the data calculation module and the effective data cache module, and is used to read coefficients from the pre-stored multiple sets of coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module;

[0022] The effective data cache module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal;

[0023] The data calculation module is used to perform convolution calculation according to the received effective coefficients and effective data to obtain a reconstructed waveform.

[0024] In one of the embodiments, the effective data cache module stores the effective data in parallel into continuous internal cache units using a shifting method; and / or the effective coefficient generation module reads out two adjacent groups of coefficients according to the integer position information of the effective position information, and calculates the two groups of coefficients read using a linear interpolation algorithm according to the decimal position information of the effective position information to obtain effective coefficients.

[0025] In one embodiment, the data calculation module performs convolution calculation according to the received effective coefficients and effective data, including:

[0026]

[0027] Among them, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

[0028] In one embodiment, the signal generating device further comprises:

[0029] Delay module, the arbitrary waveform generator is connected to the corresponding digital-to-analog conversion device through the delay module, and each arbitrary waveform generator is also used to synchronously send valid data to the corresponding digital-to-analog conversion device according to the accompanying clock sent by the digital-to-analog conversion device.

[0030] In one embodiment, the signal generating device further comprises:

[0031] The service decoding module is connected to the host computer, the external clock chip, the read-write control module and the arbitrary waveform generator, and performs parameter configuration on the external clock chip and the arbitrary waveform generator according to the instructions issued by the host computer, and stores the original waveform in the storage device through the read-write control module.

[0032] A second aspect of the present application provides a signal generation method, comprising:

[0033] The external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device;

[0034] The read / write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator;

[0035] The arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock; wherein the reconstructed waveform is used by the digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0036] A third aspect of the present application provides an analog-digital hybrid test board, comprising the above-mentioned signal generating device.

[0037] A fourth aspect of the present application provides a test machine, comprising a communication board, a backplane and the above-mentioned analog-digital hybrid test board.

[0038] In the above-mentioned signal generating device, method, analog-to-digital hybrid test board and test machine, the external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device, and the read-write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator. The arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock, so as to be used as a digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip. By resampling the original waveform to generate a reconstructed waveform, the external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device to complete the digital-to-analog conversion, without the need for the external clock chip to adjust the frequency of the sampling clock, thereby simplifying the operation and improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a structural block diagram of a signal generating device in one embodiment;

[0040] Figure 2 is a structural principle diagram of a signal generating device in one embodiment;

[0041] Figure 3 A schematic diagram of the structure of a waveform data processing module in one embodiment;

[0042] Figure 4 is a schematic diagram of the principle of digital resampling in one embodiment;

[0043] Figure 5 FIG. 4 is a flow chart of a signal generating method in one embodiment. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0048] In one embodiment, Figure 1 As shown, a signal generating device is provided, including an arbitrary waveform generator (AWG) 110, a read-write control module 120, an external clock chip 130 and a storage device 140, wherein the read-write control module 120 is connected to the arbitrary waveform generator 110 and the storage device 140. Further, the signal generating device may also include a digital-to-analog converter (DAC) 150 connected to the arbitrary waveform generator 110. The external clock chip 130 is used to output a sampling clock of a fixed frequency to the digital-to-analog converter 150, and the read-write control module 120 is used to read the original waveform from the storage device 140 according to the received read request instruction, and return the read original waveform 140 to the arbitrary waveform generator 110. The arbitrary waveform generator 110 is used to resample the received original waveform to generate a reconstructed waveform matching the frequency of the sampling clock, and the reconstructed waveform is used by the digital-to-analog converter 150 to perform digital-to-analog conversion according to the sampling clock output by the external clock chip 130.

[0049] The arbitrary waveform generator 110 generates a reconstructed waveform that matches the frequency of the sampling clock, which may mean that the sampling rate of the reconstructed waveform is the same as the frequency of the sampling clock, or that the error between the sampling rate of the reconstructed waveform and the frequency of the sampling clock is within an allowable range. The external clock chip 130 may be a PLL (Phase Locked Loop) clock chip, and the storage device 140 may be a DDR (Double Data Rate) storage device composed of DDR4 particles. The number of arbitrary waveform generators 110 may be one or more, and the number of digital-to-analog conversion devices 150 corresponds to the number of arbitrary waveform generators 110. For example, for the IQ channel of the test machine, an arbitrary waveform generator 110 and a digital-to-analog converter 150 can be set respectively. After the read-write control module 120 reads the original waveform according to the received read request instruction, the read original waveform is returned to the arbitrary waveform generator 110 of the corresponding channel. After receiving the original waveform, the arbitrary waveform generator 110 performs DC (direct current) calibration, AC (alternating current) calibration, resampling and other processing, and then generates a reconstructed waveform and sends it to the corresponding digital-to-analog converter 150 for digital-to-analog conversion processing to obtain an analog waveform signal output, which is used to test the semiconductor chip under test. In order to meet the needs of the digital-to-analog converter 150, the frequency of the original waveform arbitrarily set by the user is less than or equal to the frequency of the sampling clock output by the external clock chip 130.

[0050] Furthermore, if Figure 2 As shown, the signal generating device further includes a service decoding module 160, which is connected to the host computer, the external clock chip 130, the read-write control module 120 and the arbitrary waveform generator 110, and performs parameter configuration on the external clock chip 130 and the arbitrary waveform generator 110 according to the instructions issued by the host computer, and stores the original waveform in the storage device 140 through the read-write control module 120. The read-write control module 120 and the storage device 140 can be connected through an Avalon interface.

[0051] Specifically, the arbitrary waveform generator 110, the read / write control module 120 and the service decoding module 160 can be arranged in an FPGA (Field-Programmable Gate Array), and the external clock chip 130, the storage device 140 and the digital-to-analog conversion device 150 are located outside the FPGA. The port PLL_CTRL of the service decoding module 160 is connected to the external clock chip 130 through an SPI (Serial Peripheral Interface) interface, and the parameters of the external clock chip 130 are configured so that the external clock chip 130 outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device 150. The external clock chip 130 can be configured to output the sampling clock at the maximum allowed frequency (such as 400MHz), or it can be configured to output the sampling clock at other frequencies. The port DDR_RQE of the service decoding module 160 is connected to the read / write control module 120, and the waveform read / write control of the storage device 140 is realized through the read / write control module 120. The port AWG_CTRL of the service decoding module 160 is connected to the arbitrary waveform generator 110 , and sends control signal parameters to control the arbitrary waveform generator 110 to perform waveform resampling.

[0052] After the signal generating device is powered on, the service decoding module 160 automatically configures the external clock chip 130 to output a sampling clock with a fixed frequency through the SPI interface, and the host computer writes the original waveform into the storage device 140 through the service decoding module 160 and the read-write control module 120. The host computer also sends the control signal parameters to the arbitrary waveform generator 110 through the service decoding module 160, and the arbitrary waveform generator 110 sends a read request instruction to the read-write control module 120 according to the received control signal parameters, and resamples the original waveform returned by the read-write control module 120 to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0053] Continue to refer to Figure 2, the IQ two-way DAC chip is the same DAC chip, and the sampling clock of the DAC chip is set to a fixed maximum sampling clock (400MHz). Since the sampling rate of the original waveform in the storage device 140 is set arbitrarily by the user, but the DAC chip works with a fixed maximum sampling clock, the original waveform is resampled by the arbitrary waveform generator 110, and the original waveform of any sampling rate stored in the storage device 140 is resampled to the fixed maximum sampling clock while ensuring that the waveform information (amplitude, frequency) remains unchanged. The sampling rate of the obtained reconstructed waveform is the same as the frequency of the sampling clock of the DAC chip. At the same time, during the resampling process, the initial phase of the reconstructed waveform generated by the resampling can be changed by setting the initial phase. The generated reconstructed waveform is output to the DAC chip to realize the arbitrary sampling rate and arbitrary phase adjustable functions of the IQ channel. The use of two ordinary DAC chips can realize the IQ function, and the functions of two non-IQ channels can also be realized. There is no need for the external clock chip 130 to adjust the frequency of the sampling clock, which simplifies the operation and improves the test efficiency.

[0054] In one embodiment, the arbitrary waveform generator 110 includes a waveform request module 112 and a waveform data processing module 114. The waveform request module 112 is connected to the read-write control module 120 and the waveform data processing module 114, and is used to send a read request instruction to the read-write control module 120, and send the original waveform returned by the read-write control module 120 to the waveform data processing module 114; the waveform data processing module 114 is used to resample the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0055] The waveform request module 112 includes a waveform request unit 1122, a RAM (Random Access Memory) storage unit 1124, and a data selection unit 1126. The waveform request unit 1122 is connected to the read / write control module 120, the RAM storage unit 1124, and the data selection unit 1126. The data selection unit 1126 is connected to the RAM storage unit 1124 and the waveform data processing module 114. Furthermore, the waveform request unit 1122 and the data selection unit 1126 are also connected to the service decoding module 160.

[0056] The waveform request unit 1122 initiates a read request instruction to the read-write control module 120 according to the control signal parameters (including PRE_START instruction, AWG_CTRL_SIGNAL instruction, etc.) issued by the service decoding module 160, requesting to read the corresponding original waveform. Among them, the AWG_CTRL_SIGNAL instruction may include information such as the waveform length, the starting address of the original waveform in the storage device 140, and the number of repeated transmissions of the waveform. When the PRE_START instruction is 1, only the original waveform of the I channel is requested from the read-write control module 120, when the PRE_START instruction is 2, only the original waveform of the Q channel is requested from the read-write control module 120, and when the PRE_START instruction is 3, the original waveforms of both IQ channels are requested from the read-write control module 120. After the read-write control module 120 responds to the read request instruction, the original waveforms of both IQ channels are output to the waveform request unit 1122 according to the requested channel data information. After receiving the original waveform, the waveform request unit 1122 determines whether it needs to be written into the RAM storage unit 1124 according to the waveform length. If the waveform length is less than a preset threshold length (e.g., 1024), it is written into the RAM storage unit 1124. Otherwise, the waveform request unit 1122 directly outputs the original waveform to the data selection unit 1126. The data selection unit 1126 determines the source of the original waveform according to the waveform length parameter (e.g., AWG_Digital_CTRL_SIGNAL instruction) issued by the service decoding module 160. If the waveform length is less than the preset threshold length, the RAM storage unit 1124 outputs the original waveform. Otherwise, the waveform request unit 1122 directly outputs the original waveform, and the data selection unit 1126 sends the original waveform to the waveform data processing module 114 for resampling.

[0057] Since the length of the original waveform may be very small, the DDR bandwidth utilization is very low at a very small clock length, which is not enough to support the continuous output of the waveform. At this time, the original waveform needs to be stored in the RAM storage unit 1124, and the original waveform output is controlled from the RAM storage unit 1124 to reduce the impact of the large sacrifice of DDR bandwidth when small data. The RAM storage unit 1124 can support waveform repeated reading operations, continuous waveform output, and stop reading operations. When the waveform length is relatively small, the original waveform is stored in the RAM storage unit 1124, and the RAM storage unit 1124 is used to achieve continuous output of the waveform.

[0058] In one embodiment, Figure 2As shown, the arbitrary waveform generator 110 also includes a synchronization control module 116, which is connected to the waveform data processing module 114 and is used to cache the reconstructed waveform in the internal cache module, and output the reconstructed waveform in the internal cache module after receiving the trigger signal. Specifically, the synchronization control module 116 is also connected to the business decoding module 160, and the synchronization control module 116 caches the received reconstructed waveform in the internal FIFO (First Input First Output) buffer, and after receiving the trigger signal TRIG sent by the business decoding module 160, the reconstructed waveform in the FIFO buffer is output to the digital-to-analog conversion device 150. Similarly, taking the test machine including the IQ channel as an example, the synchronization control module 116 in the IQ channel is used for synchronization control, and the reconstructed waveforms of the two channels can be synchronously sent to the IQ two-way DAC chip.

[0059] It can be understood that the specific structure of the waveform data processing module 114 is not unique. The waveform data processing module 114 may include a calibration module and a digital resampling module. The calibration module is connected to the waveform request module 112, and is used to calibrate the received original waveform and output the calibrated waveform data; the digital resampling module is connected to the calibration module, and is used to resample the calibrated waveform data to generate a reconstructed waveform that matches the frequency of the sampling clock.

[0060] Among them, Figure 3 As shown, the calibration module may specifically include at least one of a DC calibration module 41 and an AC amplitude calibration module 42. Taking the calibration module including both the DC calibration module 41 and the AC amplitude calibration module 42 as an example, the DC calibration module 41 and the AC amplitude calibration module 42 are both connected to the service decoding module 160, the DC calibration module 41 is connected to the data selection unit 1126 in the waveform request module 112, and the AC amplitude calibration module 42 is connected to the DC calibration module 41 and the digital resampling module. The DC calibration module 41 performs DC calibration on the received original waveform according to the DC calibration coefficient issued by the service decoding module 160 and sends it to the AC amplitude calibration module 42 to ensure that the amplitude accuracy of the channel data meets the index requirements. Since the IQ channel has a high requirement for the flatness of AC, the AC amplitude calibration module 42 is also used to perform AC amplitude calibration on the waveform after DC calibration according to the AC calibration coefficient issued by the service decoding module 160 to ensure that the amplitude accuracy of the channel data meets the index requirements, and the AC amplitude calibration module 42 transmits the waveform after AC amplitude calibration to the digital resampling module.

[0061] The storage device 140 stores the original waveform with the frequency set by the host computer (the frequency can be variable, such as 100MHZ, that is, the original waveform with any frequency set by the user), and the external clock chip 130 is set with a fixed maximum sampling clock frequency. The function of the digital resampling module is to resample the original waveform into a reconstructed waveform with a fixed maximum sampling clock frequency (400M) (both the waveform data and the sampling frequency are converted, and based on the maximum sampling clock frequency, the original waveform is converted into a reconstructed waveform corresponding to the maximum sampling clock frequency).

[0062] The principle of resampling is to use the SINC function to perform waveform recovery for a continuous signal. Since the arbitrary waveform generator 110 resamples the original waveform of any frequency to a fixed maximum sampling frequency, the function it implements can be summarized as an interpolation of any decimal multiple. For a known continuous waveform x(n), if you want to restore it to x(t) at any time, use the Sinc function to perform data resampling and recovery. Through the first 8 points and the last 8 points of the position of the valid point to be restored, the actual value of the restored point is obtained through the convolution operation of these 16 data and 16 Sinc continuous coefficients.

[0063] In order to restore the ideal SINC function, in theory, an infinite number of sets of coefficients are needed for calculation, which is obviously not feasible. Therefore, the SINC function model is segmented into 1024 sets of coefficients, each with 16 coefficients, which are stored in ROM. The valid coefficients are read from the ROM according to the valid position information. Since it is impossible to store an infinite number of sets of coefficients, in order to achieve higher accuracy, the stored coefficients are not used directly when calculating the valid coefficients. Instead, each segment of coefficients is considered to be continuous. The valid coefficients of any point can be obtained by using a linear weighted algorithm.

[0064] Based on this, continue to refer to Figure 3 The digital resampling module may include an input waveform data cache module 43, an effective position calculation module 44, an effective coefficient generation module 45, an effective data cache module 46 and a data calculation module 47. The input waveform data cache module 43 is connected to the calibration module, the effective position calculation module 44 and the effective data cache module 46. The effective position calculation module 44 is connected to the effective coefficient generation module 45. The effective coefficient generation module 45 is connected to the data calculation module 47 and the effective data cache module 46. The effective data cache module 46 is connected to the data calculation module 47.

[0065] Among them, the input waveform data cache module 43 is specifically connected to the AC amplitude calibration module 42 in the calibration module, and is used to cache the calibrated waveform data, and send a start signal SINC_START to the effective position calculation module 44 when the number of cached data is greater than the set threshold number; and read the valid data corresponding to the valid position from the cached data according to the received read enable signal, and send the read valid data to the effective data cache module 46 for caching; the effective position calculation module 44 is used to calculate according to the set step and initial phase after receiving the start signal SINC_START, obtain the effective position information and send it to the effective coefficient generation module 45, and send a read enable signal to the input waveform data cache module 43; the effective coefficient generation module 45 is used to read coefficients from multiple sets of pre-stored coefficients according to the effective position information, obtain the effective coefficients and send them to the data calculation module 47, and send a data read enable signal to the effective data cache module 46; the effective data cache module 46 is used to read the cached effective data according to the received data read enable signal and send it to the data calculation module 47; the data calculation module 47 performs convolution calculation according to the received effective coefficients and effective data to obtain the reconstructed waveform. The convolution formula is as follows:

[0066]

[0067] Among them, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point (there are 16 valid coefficients in total), DATA_IN represents the valid data corresponding to this valid position (also 16 points, the first 8 points and the last 8 points of this valid position), and after 16 multiplications and additions of the valid coefficient and the original waveform, the corresponding reconstruction point of the reconstructed waveform is calculated.

[0068] The value of the threshold number is not unique and can be set according to actual needs. The service decoding module 160 is connected to the effective position calculation module 44 to configure the step STEP and the initial phase PHASE. By controlling the step STEP and the initial phase PHASE, the digital resampling module can resample the initial waveform of the variable sampling frequency into a reconstructed waveform of the fixed maximum sampling frequency. At the same time, since the digital resampling module performs digital resampling, the phase adjustment of the output waveform can also be achieved, and the accuracy can reach up to 1ps.

[0069] Specifically, after the input waveform data buffer module 43 receives the calibrated waveform data output by the AC amplitude calibration module 42, it can be cached in an internal cache unit (such as FIFO). When the number of cached data is greater than the set threshold number (such as 16), the input waveform data buffer module 43 sends a start signal SINC_START to the effective position calculation module 44. The effective position calculation module 44 starts working after receiving the start signal SINC_START, and performs effective position calculation according to the step STEP and initial phase PHASE information sent by the service decoding module 160. The effective position can be understood as the reconstructed waveform point position, and the calculated effective position information is composed of 16-bit integer + 48-bit decimal. Among them, the initial position of the reconstructed waveform is determined by the initial phase PHASE, and the initial position refers to the effective position of the first point of the reconstructed waveform. The relationship between the reconstructed waveform point position and the original waveform point position is: reconstructed waveform point position = (original waveform point position - 1) * STEP + 1 + PHASE. The original waveform point position is also the point position of the calibrated waveform data. DC calibration and AC amplitude calibration will not change the point position of the original waveform.

[0070] Among them, step STEP = user-set sampling rate (sampling rate of the original waveform) / fixed maximum sampling rate (frequency of the sampling clock). Since the user-set sampling rate is less than or equal to the fixed maximum sampling rate, the value of STEP is less than or equal to 1, which can be understood as an interpolation operation of any multiple. Among them, step STEP consists of 16-bit integer + 48-bit decimal. Since the fixed maximum sampling rate is set to 400MHz, the 48-bit decimal can support uhz and above, and sampling rate resampling with an accuracy of uhz can be achieved. Since the arbitrary waveform generator 110 has a fixed 400MHz sampling rate output, in order to achieve the sampling rate resolution, the purpose of uHZ adjustment can be achieved. Assuming A=400MHz=400*2^10*2^10Hz, B=1uHz=(1 / 2^10*2^10)Hz, then A / B=400*2^10*2^10Hz / (1 / 2^10*2^10)Hz=400*2^4 =49bit. Since the SINC algorithm divides the coefficients into 1024 parts, the minimum position information requires 400*2^40 / 1024bit=39bit, and 48bit is used in this solution. Among them, the initial phase PHASE=the number of points in a waveform cycle / (360° / the phase of the reconstructed waveform), and the output result is composed of 16-bit integer + 48-bit decimal, which can perform ps-level phase adjustment.

[0071] After obtaining the effective position information according to the set step STEP and initial phase PHASE, the effective position calculation module 44 outputs the effective position information to the effective coefficient generation module 45, and sends a read enable signal to the input waveform data cache module 43 according to the determined effective position. The input waveform data cache module 43 reads a data and sends it to the effective data cache module 46 according to the read enable signal sent by the effective position calculation module 44. At this time, the data stored in the effective data cache module 46 is the effective data of the effective position. After the effective coefficient generation module 45 calculates the effective coefficient of the effective position, the effective data cache module 46 reads the effective data and sends it to the data calculation module 47 for calculation.

[0072] The effective coefficient generation module 45 can store multiple groups (for example, 1024 groups) of coefficients (16 coefficients in each group) in the internal ROM (read-only memory) unit in advance. After receiving the effective position information, the effective coefficient generation module 45 can read out two adjacent groups of coefficients according to the integer position information of the effective position information, and use a linear interpolation algorithm to calculate the two groups of coefficients read according to the decimal position information of the effective position information to obtain the effective coefficients.

[0073] Specifically, the effective coefficient generation module 45 reads the pre-stored coefficients in the ROM unit according to the effective position information. Since there are only 1024 groups of pre-stored coefficients, the precision of 48-bit decimals cannot be satisfied. At this time, two adjacent groups of coefficients (one group of 16 coefficients) are read out according to the integer position information of the effective position information, and then the two groups of coefficients are calculated according to the decimal position information of the effective position information, using the linear interpolation algorithm: y_coe[n]=COE1[n]*tim_valid+COE2[n]*(1-tim_valid), n is 0-15, and the most accurate effective coefficients (16 coefficients) are obtained. Among them, COE1 represents the first group of coefficients in the two adjacent groups of coefficients read out, COE2 represents the second group of coefficients in the two adjacent groups of coefficients read out (the first group of coefficients and the second group of coefficients are both 16), tim_valid represents the decimal position information in the effective position information, and y_coe represents the effective coefficients (16 coefficients) in the decimal position of the actual effective position information obtained by linear interpolation.

[0074] The valid data cache module 46 can store the valid data in parallel into continuous internal cache units (such as FIFO) by using a shifting method. Specifically, the valid data cache module 46 stores the valid data in parallel into 16 FIFOs by using a shifting method. The specific manifestation of parallel storage is that the latest input data is stored in FIFO1, and the data in the original FIFO1 is stored in FIFO2, and the data in the original FIFO2 is stored in FIFO3, ..., that is, the 16 FIFOs store 16 continuous data.

[0075] After the effective coefficient generation module 45 generates an effective coefficient, it outputs the effective coefficient to the data calculation module 47, and simultaneously initiates a data read enable signal to the effective data cache module 46. According to the data read enable signal, the effective data cache module 46 simultaneously reads out 16 effective data from the 16 FIFOs and outputs them to the data calculation module 47. The data calculation module 47 performs a 16-order convolution calculation based on the effective coefficient output by the effective coefficient generation module 45 and the effective data output by the effective data cache module 46, calculates the resampled reconstructed waveform, and outputs it to the subsequent synchronization control module 116.

[0076] The following example illustrates that, assuming condition 1: the user sets the sampling rate (the frequency of the original waveform) to 202Mhz, assuming condition 2: the phase of the reconstructed waveform is set to 3.6°, assuming condition 3: the waveform file is 100 points, representing 2 cycles. At this time: Step STEP = user-set sampling rate / fixed maximum sampling rate = 202 / 400 = 0.505, initial phase PHASE = number of points in a waveform cycle / (360° / phase of the reconstructed waveform) = (100 / 2) / (360° / 3.6°) = 0.5. Figure 4 As shown in the figure, the effective position of the first point in the reconstructed waveform is determined by the initial phase PHASE, and the number of points in the reconstructed waveform corresponds to the effective position in the original waveform. The relationship between the position of the reconstructed waveform points and the position of the original waveform points is: the position of the reconstructed waveform points = (the position of the original waveform points - 1) * STEP + 1 + PHASE = (the position of the original waveform points - 1) * 0.505 + 1 + 0.5, such as: 1----1.500, 2----2.005, 3----2.510, 4-----3.015. Figure 4 As shown in the figure, it explains the effect of the user-set frequency, waveform points, and initial phase on resampling, as well as their relationship with the effective position.

[0077] In one embodiment, the signal generating device further includes a delay module, and the arbitrary waveform generator 110 is connected to the corresponding digital-to-analog conversion device 150 through the delay module. Each arbitrary waveform generator 110 is also used to synchronously send valid data to the corresponding digital-to-analog conversion device 150 according to the accompanying clock sent by the digital-to-analog conversion device 150. Figure 2As shown, the delay module may specifically include an IDELAY unit and an ODELAY unit. Since different routings may result in different delays, the IDELAY unit and the ODELAY unit are used to adjust the delay of the reconstructed waveform transmission so that the DAC chip meets the setup and hold time. The synchronization control module 116 in the arbitrary waveform generator 110 is connected to the corresponding digital-to-analog conversion device 150 through the delay module, and the synchronization control module 116 and the delay module can be connected through an LVDS (Low-Voltage Differential Signaling) interface. The digital-to-analog conversion device 150 outputs the accompanying clock data_clk to the synchronization control module 116, and the synchronization control module 116 outputs the reconstructed waveform according to the accompanying clock data_clk.

[0078] Taking the test machine including IQ dual channels as an example, the DAC chips of the two channels will send the accompanying clock data_clk. Since the sampling clocks input by the two DAC chips have the same source and frequency, only one of the sampling clocks can be used as the common sampling clock of the two DAC chips. The DAC chip outputs the accompanying clock data_clk to the synchronization control module 116, and the synchronization control module 116 outputs the reconstructed waveform to the DAC chip according to the accompanying clock data_clk.

[0079] In order to ensure data synchronization, after receiving the trigger signal TRIG, the synchronization control module 116 first converts the trigger signal TRIG across the clock domain to the clock domain of the accompanying clock data_clk of the I-channel DAC chip, and then determines whether the working mode is the IQ mode according to the working mode issued by the service decoding module 160. If it is the IQ mode, it is determined that as long as the trigger signal TRIG of one channel is pulled high, that is, the synchronization control modules 116 of the two channels are controlled to read data from the FIFO at the same time, and output data according to the accompanying clock data_clk of the I-channel DAC chip as the clock, so that the IQ two-channel data can be output synchronously; when the working mode is not the IQ mode, the synchronization control modules 116 of the two IQ channels control the IQ two-channel data output according to the TRIG signals received by each.

[0080] Reference Figure 2 and Figure 3, the complete processing process of the original waveform is described below: after the signal generating device is powered on, the host computer communicates with the business decoding module 160, writes the original waveform into the storage device 140 through the business decoding module 160, configures the external clock chip 130 to output a sampling clock of a fixed frequency, and sends control signal parameters to the arbitrary waveform generator 110 for parameter configuration, specifically including configuring the control signal parameters of the waveform request unit 1122, the waveform length parameters of the data selection unit 1126, the DC calibration parameters of the DC calibration module 41, the AC calibration parameters of the AC amplitude calibration module 42, the step and initial phase of the effective position calculation module 44, etc.

[0081] The waveform request unit 1122 sends a read request instruction to the read-write control module 120 to request to read the original waveform according to the configured control signal parameters. After receiving the original waveform, the waveform request unit 1122 determines whether it needs to be written into the RAM storage unit 1124 according to the waveform length. If the waveform length is less than the preset threshold length, it is written into the RAM storage unit 1124, otherwise the waveform request unit 1122 directly outputs the original waveform to the data selection unit 1126. The data selection unit 1126 determines the source of the original waveform according to the waveform length parameter issued by the business decoding module 160, obtains the original waveform from the RAM storage unit 1124 or the waveform request unit 1122, and sends it to the waveform data processing module 114 for resampling processing.

[0082] In the waveform data processing module 114, the DC calibration module 41 and the AC amplitude calibration module 42 perform DC calibration and AC amplitude calibration on the original waveform in sequence according to the configured DC calibration coefficient and AC calibration coefficient, and then send the original waveform to the input waveform data cache module 43 for cache. When the number of cached data is greater than the set threshold number, the input waveform data cache module 43 sends a start signal SINC_START to the effective position calculation module 44. After receiving the start signal SINC_START, the effective position calculation module 44 calculates the effective position information according to the configured step and initial phase and sends it to the effective coefficient generation module 45, and sends a read enable signal to the input waveform data cache module 43. The input waveform data cache module 43 reads the effective data corresponding to the effective position from the cached data according to the received read enable signal, and sends the read effective data to the effective data cache module 46 for cache. The effective coefficient generation module 45 reads the coefficients from the pre-stored multiple sets of coefficients according to the effective position information, obtains the effective coefficients and sends them to the data calculation module 47, and sends the data read enable signal to the effective data cache module 46. The valid data cache module 46 reads the cached valid data according to the received data read enable signal and sends it to the data calculation module 47. The data calculation module 47 performs convolution calculation according to the received valid coefficients and valid data to obtain a reconstructed waveform.

[0083] The reconstructed waveform calculated by the data calculation module 47 is sent to the synchronization control module 116 for caching. After receiving the trigger signal TRIG sent by the service decoding module 160, the synchronization control module 116 uses the accompanying clock data_clk of the DAC chip as the clock and sends the cached reconstructed waveform to the DAC chip through the delay module. The DAC chip performs digital-to-analog conversion on the received reconstructed waveform according to the sampling clock output by the external clock chip 130, and obtains an analog waveform signal and outputs it to the device under test for testing.

[0084] In one embodiment, Figure 5 As shown, a signal generation method is also provided, including:

[0085] Step S110: the external clock chip outputs a sampling clock with a fixed frequency to the digital-to-analog conversion device.

[0086] Step S120: the read / write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator.

[0087] Step S130: the arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock; wherein the reconstructed waveform is used by the digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

[0088] It can be understood that the specific implementation of the above-mentioned signal generating method has been explained in detail in the above-mentioned signal generating device, and will not be repeated here.

[0089] In one embodiment, an analog-digital hybrid test board is also provided, comprising the above-mentioned signal generating device.

[0090] In one embodiment, a test machine is also provided, including a communication board, a backplane and the above-mentioned analog-digital hybrid test board. The communication board is connected to the analog-digital hybrid test board through the backplane. In addition, the test machine also includes a host computer that communicates with the communication board. The host computer can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0091] The above-mentioned signal generating device, method, analog-digital hybrid test board and test machine have the following advantages:

[0092] 1. This application uses a DAC chip to fix the sampling clock frequency. After power-on initialization, there is no need to repeatedly configure the external clock chip, which reduces the clock chip locking time caused by changing the sampling clock and improves test efficiency.

[0093] 2. This application uses a DAC chip to fix the sampling clock frequency, and performs resampling operations through a digital domain algorithm to achieve arbitrary sampling rate design, which can achieve uHZ sampling rate resolution adjustment. This indicator requirement is an indicator requirement that is difficult to achieve by the existing method of adjusting the sampling rate through a clock chip.

[0094] 3. This application can realize both IQ functions and non-IQ functions, making it more flexible and convenient to use and improving the efficiency of equipment use.

[0095] 4. The control method of this application facilitates the expansion, reuse, and transplantation of program channels and can be directly used in other projects. For program updates, only channels need to be added or reduced, which facilitates program code maintenance.

[0096] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A signal generating device, characterized in that: include: Arbitrary waveform generator, read-write control module, external clock chip and storage device; The external clock chip is used to output a sampling clock of a fixed frequency to the digital-to-analog conversion device; The read-write control module is connected to the arbitrary waveform generator and the storage device, and is used to read the original waveform from the storage device according to the received read request instruction, and return the read original waveform to the arbitrary waveform generator; The arbitrary waveform generator is used to resample the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock; wherein the arbitrary waveform generator calculates effective position information based on control signal parameters, determines effective coefficients based on the effective position information, and reads effective data corresponding to the effective position from the original waveform, and then convolves the effective coefficients and the read effective data to obtain a reconstructed waveform; the reconstructed waveform is used by a digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

2. The signal generating device according to claim 1, characterized in that: The arbitrary waveform generator comprises: A waveform request module, connected to the read-write control module and the waveform data processing module, used to send a read request instruction to the read-write control module, and send the original waveform returned by the read-write control module to the waveform data processing module; The waveform data processing module is used to resample the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock.

3. The signal generating device according to claim 2, characterized in that: The arbitrary waveform generator also includes: A synchronization control module is connected to the waveform data processing module and is used to cache the reconstructed waveform in an internal cache module and output the reconstructed waveform in the internal cache module after receiving a trigger signal.

4. The signal generating device according to claim 2, characterized in that: The waveform data processing module comprises: A calibration module, connected to the waveform request module, for calibrating the received original waveform and outputting calibrated waveform data; The digital resampling module is connected to the calibration module and is used to perform resampling processing on the calibrated waveform data to generate a reconstructed waveform that matches the frequency of the sampling clock.

5. The signal generating device according to claim 4, characterized in that: The calibration module includes at least one of a DC calibration module and an AC amplitude calibration module.

6. The signal generating device according to claim 4, characterized in that: The digital resampling module comprises: An input waveform data cache module is connected to the calibration module, the effective position calculation module and the effective data cache module, and is used to cache the calibrated waveform data, and send a start signal to the effective position calculation module when the number of cached data is greater than a set threshold number; and read the effective data corresponding to the effective position from the cached data according to the received read enable signal, and send the read effective data to the effective data cache module for caching; The effective position calculation module is connected to the effective coefficient generation module, and is used to calculate according to the set step and initial phase after receiving the start signal, obtain effective position information and send it to the effective coefficient generation module, and send a read enable signal to the input waveform data cache module; The effective coefficient generation module is connected to the data calculation module and the effective data cache module, and is used to read coefficients from the pre-stored multiple sets of coefficients according to the effective position information, obtain effective coefficients and send them to the data calculation module, and send a data read enable signal to the effective data cache module; The effective data cache module is connected to the data calculation module and is used to read the cached effective data and send it to the data calculation module according to the received data read enable signal; The data calculation module is used to perform convolution calculation according to the received effective coefficients and effective data to obtain a reconstructed waveform.

7. The signal generating device according to claim 6, characterized in that: The effective data cache module stores the effective data in parallel into continuous internal cache units using a shifting method; and / or the effective coefficient generation module reads out two adjacent groups of coefficients according to the integer position information of the effective position information, and calculates the two groups of coefficients read using a linear interpolation algorithm according to the decimal position information of the effective position information to obtain effective coefficients.

8. The signal generating device according to claim 6, characterized in that: The data calculation module performs convolution calculation according to the received effective coefficients and effective data, including: ； Among them, DATA_VALID represents the reconstruction point of the reconstructed waveform, COE represents the valid coefficient corresponding to the valid position of the reconstruction point, and DATA_IN represents the valid data corresponding to the valid position.

9. The signal generating device according to any one of claims 1 to 8, characterized in that: Also includes: Delay module, the arbitrary waveform generator is connected to the corresponding digital-to-analog conversion device through the delay module, and each arbitrary waveform generator is also used to synchronously send valid data to the corresponding digital-to-analog conversion device according to the accompanying clock sent by the digital-to-analog conversion device.

10. The signal generating device according to any one of claims 1 to 8, characterized in that: Also includes: The service decoding module is connected to the host computer, the external clock chip, the read-write control module and the arbitrary waveform generator, and performs parameter configuration on the external clock chip and the arbitrary waveform generator according to the instructions issued by the host computer, and stores the original waveform in the storage device through the read-write control module.

11. A signal generating method, characterized in that: include: The external clock chip outputs a sampling clock of a fixed frequency to the digital-to-analog conversion device; The read / write control module reads the original waveform from the storage device according to the received read request instruction, and returns the read original waveform to the arbitrary waveform generator; The arbitrary waveform generator resamples the received original waveform to generate a reconstructed waveform that matches the frequency of the sampling clock; wherein the arbitrary waveform generator calculates effective position information based on control signal parameters, determines effective coefficients based on the effective position information, and reads effective data corresponding to the effective position from the original waveform, and then convolves the effective coefficients and the read effective data to obtain a reconstructed waveform; the reconstructed waveform is used by a digital-to-analog conversion device to perform digital-to-analog conversion according to the sampling clock output by the external clock chip.

12. An analog-digital hybrid test board, characterized in that: The invention comprises the signal generating device according to any one of claims 1 to 10.

13. A testing machine, characterized in that: It comprises a communication board, a backplane and the analog-digital hybrid test board card as claimed in claim 12.

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