Data access structure for hbm architecture

Abstract

The application discloses a data access structure for an HBM architecture, and relates to the field of integrated circuits. The HBM architecture comprises at least two storage stacks, each of which comprises at least M storage space groups, each of which comprises at least N HBM spaces that are continuous in address, each of which is provided with two connection nodes, and the two connection nodes are connected to data channels of a data processing device. Raw data stored in the HBM is normalized into a plurality of continuous data blocks in sequence, and the data blocks are sequentially stored in address blocks in the M*N storage space groups. The address blocks at the same address bit in adjacent storage space groups store two continuous data blocks, and the data blocks in the same storage space group are accessed according to address depth. The scheme can realize the advantages of synchronous access of multiple HBM, reduction of transmission delay, simplification of data synchronization, batch task design and the like.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of integrated circuits, and in particular to a data access structure for HBM architecture. BACKGROUND

[0002] HBM stands for High Bandwidth Memory, which is a stacked memory technology. In principle, it is to stack multiple DDRs together through silicon through (TVS) technology, etc., so as to realize a large-capacity, high-bit-width DDR combined array. HBM can be packaged with CPU, GPU and FPGA, etc. on one chip to realize high-bandwidth access. For example, Nvidia A100 GPU uses 80GB of HBM2 memory, and the entire memory bandwidth reaches 2TB / s.

[0003] The latest Versal HBM series FPGA of Xilinx contains two HBM2e memory stacks, each with a capacity of 8GB or 16GB. Each stack has 8 AXI HBM memory controllers, and each memory controller can be divided into two semi-independent 64-bit pseudo channels for addressing the dedicated part of the HBM. The maximum capacity of the Versal HBM series FPGA is 32G, and the maximum throughput is 819 GB / s.

[0004] Since HBM is stacked by multiple DDRs, and has multiple memory controllers, it has multiple relatively independent memory spaces. When using HBM, each memory space can be used independently, or multiple memory spaces can be used as a continuous space. When each memory space of HBM is used independently, the address and data of each space are independent of each other and irrelevant. When storing and accessing, each space needs to be operated independently, which is complex. When HBM is used as a continuous memory space, global address access is required. A switch can be used to convert the global address to the internal address of the independent space to achieve global access. However, when there are many access interfaces, the switch design will become very large, and the layout and wiring will be difficult, and the data will also be blocked, causing large delay. SUMMARY

[0005] Embodiments of the present application provide a data access structure for HBM architecture, which solves the problem of data blocking and delay in HBM space access. The HBM architecture includes at least two memory stacks HBM Stack, each memory stack includes at least M memory space groups HBM Group, each memory space group includes at least N HBM spaces that are continuous in address, each HBM space is provided with two connection nodes, and the two connection nodes are connected to the data channel of the data processing device respectively;

[0006] The original data for storage in the HBM is normalized into a plurality of continuous data blocks in sequence, and the data blocks are sequentially stored in address blocks in M*N HBM spaces, the address blocks at the same address bit in adjacent storage space groups store two continuous data blocks, and the data blocks in the same storage space group are accessed according to the address depth.

[0007] Specifically, the normalized data blocks are of the same size, and the data blocks are sliced according to data lines and arranged by rows.

[0008] Specifically, when the data blocks are pictures, the pixels are sliced into a plurality of data lines, and each data line represents the pixel length of the image; when the data blocks are M*N-dimensional vector matrices, each sliced data line represents a single vector with a dimension of A.

[0009] Specifically, the normalized original data is divided by rows and labeled and sorted into a plurality of data lines, the odd data lines are spliced into an odd data sequence in order of label size, the even data lines are spliced into an even data sequence in order of label size, and the odd data sequence and the even data sequence are spliced together to form a data block.

[0010] In the storage space group, each address block is divided into a first storage area and a second storage area, the target data block allocated to the address block is split into an odd data sequence and an even data sequence, and is respectively stored in the first storage area and the second storage area.

[0011] Specifically, the HBM space in each storage space group includes a plurality of storage units, and the data bit width of each storage unit is equal to the data bit width of the connection node.

[0012] Each data line is divided into a plurality of data segments according to the data bit width of the storage unit, and the HBM space for storage and the storage unit position in the HBM space are determined according to the number of divided data segments.

[0013] Specifically, the plurality of continuous data segments are sequentially stored in the storage units of N HBM spaces, the storage units at the same address bit in adjacent HBM spaces store two continuous data segments, and the data segments in the same HBM space are accessed according to the address depth.

[0014] Specifically, the storage units of each HBM space are divided into a first sub-storage area and a second sub-storage area, the data segments of the odd data lines are stored in the storage units in the first sub-storage area, and the data segments of the even data are stored in the storage units in the second sub-storage area; the first sub-storage areas in the N HBM spaces collectively form a first storage area, and the second sub-storage areas in the N HBM spaces collectively form a second storage area.

[0015] Specifically, the first sub-storage area in each HBM space is connected to the first data channel of the data processing device through a connection node to transmit odd data rows; and the second sub-storage area is connected to the second data channel of the data processing device through another connection node to transmit even data rows.

[0016] Specifically, the data processing device includes M groups of data channels, which correspond to M groups of storage space groups respectively; each group of data channels includes a first data channel for transmitting odd data rows and a second data channel for transmitting even data rows.

[0017] In the same storage space group, the first sub-storage areas of all HBM spaces are connected to the first data channel through respective connection nodes, and the second sub-storage areas of all HBM spaces are connected to the second data channel through respective connection nodes.

[0018] Specifically, the M groups of data channels simultaneously read odd data rows and even data rows from all HBM spaces according to a timing sequence.

[0019] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0020] Multi-HBM synchronous access; the HBM is divided into multiple different groups, and each group includes different spaces. Each space is an independent HBM storage space and has a continuous physical space. The addresses of different HBM spaces are continuous, but the physical spaces are discontinuous. The addresses and physical spaces of different groups can also be discontinuous.

[0021] Low fan-out design; data reading and writing are performed in units of groups, and there is no data interaction between different groups. Therefore, when performing layout and wiring, the data reading and writing control module will only connect around the respective HBM groups, and will not be connected to other HBM groups, thereby avoiding cross-wiring between different groups and reducing the fan-out of the wiring.

[0022] Low latency design; since the data reading and writing module is arranged around the respective HBM groups, the distance to the memory is short, so the latency of data reading and writing is low. In addition, the data is stored and read in an odd-even row manner, so that the data of the two channels in the same HBM space is independent, reducing the waiting caused by data conflict, improving the efficiency and reducing the task latency.

[0023] Simplify data synchronization; data line is stored in one or more different HBM Spaces according to the bit width requirement calculated by hardware. Since the structure of each HBM Space is the same, the read-write control logic is the same, the data path is similar, and the data arrival time is similar. In this way, only a simple data cache is needed to easily realize the synchronization of data. Similarly, the structures of different HBM Groups are the same, the control logic is the same, the data path is similar, and the synchronization between tasks can be easily realized. Therefore, there is no longer a need for a complex cache structure to ensure the simultaneous arrival of data, simplifying the data synchronization process.

[0024] Batch task design; two external interfaces of the same HBM Group can be task divided according to the odd and even row data, and different HBM Groups can also be task divided. Therefore, the architecture supports batch tasks to be performed at the same time when in use. At the same time, due to the similarity of the structure and layout, the execution time of different tasks is similar, facilitating batch management.

[0025] Data slice management; in order to improve the data read-write efficiency, the data is processed by slicing in the architecture. That is, the data stored in each HBM is not a complete and valid data, but a data that is reorganized and reordered by multiple HBMs to obtain a complete data. Through the slicing of the data, the architecture has greater flexibility and higher parallel processing capability. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a structural schematic diagram of an HBM architecture;

[0027] Figure 2 is a structural schematic diagram of a data access structure for an HBM architecture provided by the present application;

[0028] Figure 3 is a storage schematic diagram of a data block in an HBM Group;

[0029] Figure 4 is a structural schematic diagram of a data block shown in an exemplary embodiment of the present application;

[0030] Figure 5 shown in the middle is a schematic diagram of dividing a data segment by 16B bit width;

[0031] Figure 6 is a schematic diagram of the internal data storage form of an HBM Group;

[0032] Figure 7 is a structural schematic diagram of an HBM data access system. DETAILED DESCRIPTION

[0033] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0034] In this paper, "multiple" refers to two or more. "And / or" describes the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0035] Figure 1 is a structural diagram of the HBM architecture, and the present application takes the HBM on the Versal HBM series FPGA as an example for illustration, and the access mode on other HBMs is similar. Figure 1 In the figure, the overall architecture of synchronously accessing the Versal HBM is shown, and the FPGA of this series has two storage stacks HBM Stack, namely Stack 0 and Stack 1 in the figure. Figure 1 In the figure, the overall architecture of synchronously accessing the Versal HBM is shown, and the FPGA of this series has two storage stacks HBM Stack, namely Stack 0 and Stack 1 in the figure. Each stack has 8 memory controllers (MC) on it, each memory has 2 pseudo channels (PC) on it, and each pseudo channel has 2 read-write nodes (NMU) on it, a total of 64 connection nodes. Through these connection nodes, users can access the storage units of the HBM. The architecture and access scheme of the present application do not discuss the internal structure of the memory controller and the pseudo channel, and focus on the division of the internal space of the HBM and the access to the specific internal space through the connection nodes.

[0036] Figure 2 is a structural diagram of the data access structure for the HBM architecture provided by the present application, which includes at least two storage stacks HBM Stack, and each storage stack includes at least M storage space groups HBM Group. Each HBM Group includes at least N HBM spaces (HBM Space) that are continuous in address, and each HBM Space is provided with two connection nodes NUM, and the two connection nodes are respectively connected to the data channels of the data processing device. Figure 1Taking the HBM architecture as an example, there are two HBM Stacks, each containing four HBM Groups. Each HBM Group has four contiguous HBM Spaces. Assuming the total HBM storage space is 32GB, each HBM Space is divided into 32 independent storage spaces, each with a storage space of 1GB. In use, one or more HBM Spaces are merged into a space group. This design uses four HBM Spaces merged into one HBM Group, but other numbers are also possible; this application does not specify a particular group.

[0037] Considering the issues of data access and processing efficiency and latency in related technologies, this application chooses to process the raw data during the storage stage. Specifically, the raw data originally intended for storage in HBM is normalized sequentially. Normalization aims to complete data segmentation and numbering, especially in the data storage domain, where data segmentation and partitioned storage are necessary to improve transmission efficiency. Before storage, this application segments the raw data into several consecutive data blocks, and these data blocks are sequentially stored in address blocks within M*N HBM spaces. Address blocks with the same address in adjacent storage space groups store two consecutive data blocks, and data blocks within the same storage space group are accessed according to address depth.

[0038] First, we define the basic unit of data storage and transfer as a data block, which can be divided into multiple data lines. For example, when the data content is an image, an image can be considered a data block. Since each image in storage has the same number of pixels and pixel depth, the normalized size of each block is the same. Within an image data block, the dataline refers to the pixel length of the image; each image can be segmented according to its pixel length. When the data content is a vector matrix, an M*N matrix is ​​a data block, representing a complete and meaningful set of data. Each data line of a slice is represented as a single vector of dimension M.

[0039] Figure 3is a schematic diagram of data block storage in HBM Group, and after several continuous divisions, data block block is sequentially stored in the address block in M*N HBM space, and the address block with the same address bit in the adjacent storage space group stores two continuous data blocks, and the data blocks in the same storage space group are accessed according to the address depth. Taking two storage stacks as an example, HBM Group 0-HBM Group 7 are represented, block 0 is stored in HBM Group 0, block 1 is stored in HBM Group 1, and so on, block 7 is stored in HBM Group 7, and block 8 is stored in HBM Group 0, and so on. Moreover, in order to clarify the storage order and position, block 0-block 7 can be stored in parallel to improve the storage efficiency, and in the same HBM Group, the data blocks are sequentially stored in the corresponding address block according to the address bit size, and the matrix storage array is formed from the data structure, and the data blocks are sequentially stored in each row, and the adjacent data blocks in each row are continuous in structure. The advantage of such storage is that the continuity of data storage is ensured, and the balance of data is ensured, and the read and write data volume of each HBM Group is also the same.

[0040] In some other embodiments, the data block block can also be further divided and processed according to the data line dataline, and the read and write efficiency can be improved by further division and storage. Specifically, in the storage stage, the normalized original data is divided by row and labeled and sorted into several data lines, the odd data lines are spliced into an odd data sequence according to the label size order, and the even data lines are spliced into an even data sequence according to the label size order, and then the odd data sequence and the even data sequence are spliced together to form a data block.

[0041] Figure 4 is a structural schematic diagram of the data block shown in the example embodiment of the application, the data structure of block 0 is composed of the order of even data sequence+odd data sequence, and all the even data lines in the even data sequence are arranged in the order of line 0, line 2, …, line h-2, and correspondingly, all the odd data lines in the odd data sequence are arranged in the order of line 1, line 3, …, line h-1, where h is an even number. When storing, the target data block is first divided into two sub-sequences according to the odd data sequence and the even data sequence. At the same time, each address block in the HBM Group is further divided into a first storage area and a second storage area, the first storage area is used to store the divided odd data sequence, and the second storage area is divided into the even data sequence. Of course, the first storage area and the second storage area are continuous in address, Figure 4In some other embodiments, the odd data sequence can be arranged in front and the even data sequence can be arranged behind to split and store the data block.

[0042] Because the odd data sequence and the even data sequence contain a large number of odd data lines and even data lines, the data lines can be further divided. In particular, for those data lines whose bit width exceeds the bit width of the connection node NUM or the data channel. For this purpose, the present application divides the original address block into the smallest storage unit, that is, each HBM space in the storage space group contains a plurality of storage units, and the storage unit is the smallest storage space of the storage device, and the data needs to be further divided into the storage unit. The data bit width of each storage unit is equal to the data bit width of the connection node, and the data bit width of the storage unit is used to divide each data line to obtain a target number of data segments, and then the continuous data segments are placed in the corresponding storage unit.

[0043] For example, if the data bit width of an HBM read-write interface is 16B and the data bit width used by the hardware for calculation is 64B, then one data line needs to be stored in 4 HBM spaces, and each HBM space stores 1 / 4 of the data line data. When the data needs to be read, 16B of data is read from each HBM space, and a 64B data output is synthesized to the hardware calculation unit. After the data line is sliced, the data is stored in 4 different HBM spaces, and the data amount in each storage is 1 / 4 of the original. When synchronous caching is performed, the data size that needs to be cached is also 1 / 4 of the original, thereby greatly reducing the cache amount. Figure 5 The figure shows a schematic diagram of dividing data segments with a 16B bit width, wherein [0:15] is the first data segment segment 0, [16:31] is the second data segment segment 1, [32:47] is the third data segment segment 2, and so on.

[0044] For the internal storage of a complete HBM Group, the divided continuous data segments are sequentially stored in the storage units of N HBM spaces. The storage units at the same address bit in adjacent HBM spaces store two continuous data segments, and the data segments in the same HBM space are accessed according to the address depth. For specific storage forms, refer to Figure 6For example, the storage unit of each HBM Space is divided into a first sub-storage area and a second sub-storage area. The data segments of the odd data rows are stored in the storage unit in the first sub-storage area, and the data segments of the even data rows are stored in the storage unit in the second sub-storage area. In fact, the first sub-storage areas in the N HBM Spaces collectively form a first storage area, and the second sub-storage areas in the N HBM Spaces collectively form a second storage area. All the second sub-storage areas in which the even data sequences in all the HBM Spaces are located collectively form a second storage area.

[0045] Figure 6 In the example shown in FIG. 6, only the storage of the even data sequences in the second sub-storage area is shown. Assuming that the line 0 is divided into 8 data segments, the data segments are sequentially stored in the HBM Space 0 to the HBM Space 3 according to the address depth. The 8 data segments are divided into two rows, and two storage units are used in each HBM Space. The data is sequentially stored according to the address depth, so that the data is stored in a horizontal continuous and vertical deep manner. Figure 2 In the example shown in FIG. 6, only the storage of the even data sequences in the second sub-storage area is shown. Assuming that the line 0 is divided into 8 data segments, the data segments are sequentially stored in the HBM Space 0 to the HBM Space 3 according to the address depth. The 8 data segments are divided into two rows, and two storage units are used in each HBM Space. The data is sequentially stored according to the address depth, so that the data is stored in a horizontal continuous and vertical deep manner. Figure 2 In the example shown in FIG. 6, only the storage of the even data sequences in the second sub-storage area is shown. Assuming that the line 0 is divided into 8 data segments, the data segments are sequentially stored in the HBM Space 0 to the HBM Space 3 according to the address depth. The 8 data segments are divided into two rows, and two storage units are used in each HBM Space. The data is sequentially stored according to the address depth, so that the data is stored in a horizontal continuous and vertical deep manner.

[0046] In some embodiments, the present application also provides an HBM data access system, as shown in FIG. 7. Figure 7 As shown in FIG. 7, the data processing device includes M groups of data channels, which correspond to M groups of storage spaces. Each group of data channels includes a first data channel for transmitting odd data rows and a second data channel for transmitting even data rows.

[0047] In the same storage space group, the first sub-storage area of all HBM spaces is connected to the first data channel through the respective connection nodes, and the second sub-storage area of all HBM spaces is connected to the second data channel through the respective connection nodes. The first sub-storage area in each HBM space is connected to the first data channel of the data processing device through a connection node to transmit odd data rows, and the second storage area is connected to the second data channel of the data processing device through another connection node to transmit even data rows. Figure 7 The data processing device uses data channel 0 and data channel 1 and the read-write control unit and the calculation unit in the data processing device to form an access calculation block of a data block, to synchronously access and calculate even data rows and odd data rows in HBM Group 0, to realize parallel processing, and the connection of HBM Group 1 and the data processing device is the same. M groups of data channels simultaneously read odd data rows and even data rows from all HBM spaces according to a timing sequence, to realize a high concurrency effect.

[0048] When performing data read-write operations, each HBM Group provides two data channels, and each channel is connected to a different Space inside the HBM Group. Data channel 0 is connected to the NMU 0 interface of each Space of HBM Group 0, for reading all even row data stored in the Space. Data channel 1 is connected to the NMU 1 interface of each Space of Group 0, for reading all odd row data stored in each Space. The data of each space is merged into a complete data when output by the HBM Group and output to the respective calculation unit for processing. Similarly, data channel 2 and data channel 3 are connected to HBM Group 1 for data read-write. The subsequent data interfaces are sequentially similar. The benefits of such reading are as follows. First, from the hardware structure, the data read-write control unit and the calculation unit are arranged and wired around the respective HBM Group. Different groups are independent of each other and do not exchange data, thereby avoiding cross-wiring between different groups. In addition, from the data storage and processing, different groups are independent of each other, which allows different tasks to be performed independently, and the HBM is divided into different groups, and the read-write mode of each group is the same, facilitating synchronous management.

[0049] In summary, the data block splitting processing scheme of the present application and the beneficial effects brought by the architecture are as follows:

[0050] Multi-HBM synchronous access; HBM is divided into multiple different Groups, and each Group contains different Spaces. Each Space is an independent HBM storage space with continuous physical space. The addresses of different HBM Spaces are continuous, but the physical spaces are not continuous. The addresses and physical spaces of different Groups can also be discontinuous.

[0051] Low fan-out design; data reading and writing are performed in units of Groups, and there is no data interaction between different Groups. Therefore, when performing layout and routing, the data reading and writing control module will only connect around the respective HBM Groups, and will not be connected to other HBM Groups, thereby avoiding cross-wiring between different Groups and reducing the fan-out of the wiring.

[0052] Low latency design; since the data reading and writing module is arranged around the respective HBM Groups, it is close to the memory, so the latency of data reading and writing is low. In addition, the data is stored and read in an odd-even row manner, so that the data of two channels in the same HBM Space is independent, reducing the waiting time caused by data conflict, improving efficiency while reducing task latency.

[0053] Simplify data synchronization; when storing data, the data line is stored in one or more different HBM Spaces according to the bit width requirement calculated by the hardware. Since the structure of each HBM Space is the same, the reading and writing control logic is the same, the data path is similar, and the data arrival time is also similar. In this way, only a simple data buffer is needed to easily achieve data synchronization. Similarly, the structures of different HBM Groups are the same, the control logic is the same, the data paths are similar, and the synchronization between tasks can also be easily achieved. Therefore, there is no longer a need for complex buffer structures to ensure that data arrives at the same time, simplifying the data synchronization process.

[0054] Batch task design; the two external interfaces of the same HBM Group can be divided into tasks according to the odd-even row data, and different HBM Groups can also be divided into different tasks. Therefore, this architecture supports batch tasks to be performed simultaneously when in use. At the same time, due to the similarity of the structure and layout, the execution time of different tasks is similar, making it convenient to manage batch tasks.

[0055] Data slice management; in order to improve the data reading and writing efficiency, the data is processed by slicing in this architecture. That is, the data stored in each HBM is not a complete and valid data, but needs to be reorganized and reordered by multiple HBMs to obtain a complete data. By slicing the data, the architecture has greater flexibility and higher parallel processing capability.

[0056] The above describes the preferred embodiments of the present application; it should be understood that the present application is not limited to the specific embodiments described above, wherein the equipment and structures not described in detail should be understood as being implemented in the ordinary way in the art; any person skilled in the art, without departing from the technical solutions of the present application, can make many possible changes and modifications, or modify equivalent embodiments of equivalent changes, which do not affect the essential content of the present application; therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, still belongs to the scope of protection of the technical solutions of the present application.

Claims

1. A data access structure for a HBM architecture, the HBM architecture comprising at least two memory stacks, each memory stack comprising at least M memory space groups, characterized in that, Each storage space group contains at least N HBM spaces that are continuous in address, each HBM space is provided with two connection nodes, and the two connection nodes are respectively connected to data channels of the data processing device; Raw data for storage in the HBM is normalized into a plurality of continuous data blocks in sequence, and the data blocks are sequentially stored in address blocks in the M*N HBM spaces, the address blocks at the same address bit in adjacent storage space groups store two continuous data blocks, and the data blocks in the same storage space group are accessed according to address depth.

2. The data access structure for HBM architecture according to claim 1, wherein, The normalized data blocks are of the same size, and the data blocks are sliced according to data lines and arranged by rows.

3. The data access structure for HBM architecture according to claim 2, wherein, When the data blocks are pictures, the pixels are sliced into a plurality of data lines, and each data line represents the length of the pixels of the image; when the data blocks are M*N-dimensional vector matrices, each slice of the data line represents a single vector with a dimension of M.

4. The data access structure for HBM architecture according to claim 2, wherein, The normalized raw data is divided by rows and labeled to form a plurality of data lines, the odd data lines are spliced into an odd data sequence in order of label size, and the even data lines are spliced into an even data sequence in order of label size; the odd data sequence and the even data sequence are spliced together to form a data block. In the storage space group, each address block is divided into a first storage area and a second storage area, the target data block allocated to the address block is split into an odd data sequence and an even data sequence, and is respectively stored in the first storage area and the second storage area.

5. The data access structure for HBM architecture according to claim 4, wherein, Each HBM space in each storage space group contains a plurality of storage units, and the data bit width of each storage unit is equal to the data bit width of the connection node. Each data line is divided into a plurality of data segments according to the data bit width of the storage unit, and the storage HBM space and the storage unit position in the HBM space are determined according to the number of divided data segments.

6. The data access structure for HBM architecture according to claim 5, wherein, The plurality of continuous data segments are sequentially stored in the storage units of the N HBM spaces, the storage units at the same address bit in adjacent HBM spaces store two continuous data segments, and the data segments in the same HBM space are accessed according to address depth.

7. The data access structure for HBM architecture according to claim 6, wherein, The storage units of each HBM space are divided into a first sub-storage area and a second sub-storage area, the data segments of the odd data lines are stored in the storage units in the first sub-storage area, and the data segments of the even data are stored in the storage units in the second sub-storage area; the first sub-storage areas in the N HBM spaces collectively form a first storage area, and the second sub-storage areas in the N HBM spaces collectively form a second storage area.

8. The data access structure for HBM architecture according to claim 7, wherein, The first sub-storage area in each HBM space is connected to the first data channel of the data processing device through a connection node to transmit the odd data lines, and the second storage area is connected to the second data channel of the data processing device through another connection node to transmit the even data lines.

9. The data access structure for HBM architecture according to claim 8, wherein, The data processing device contains M groups of data channels corresponding to M storage space groups; each group of data channels contains a first data channel for transmitting odd data lines and a second data channel for transmitting even data lines; In the same storage space group, the first sub-storage areas of all HBM spaces are respectively connected to the first data channel through respective connection nodes, and the second sub-storage areas of all HBM spaces are respectively connected to the second data channel through respective connection nodes.

10. The data access structure for HBM architecture according to claim 9, wherein, The M group data channels simultaneously read odd data rows and even data rows from all HBM spaces according to timing.

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