A pseudo two-stage pipelined processor based on RV32I instructions and its control method

Abstract

This application discloses a pseudo-two-stage pipelined processor based on RV32I instructions and its control method. The processor includes a first pseudo-two-stage pipeline structure and a second pseudo-two-stage pipeline structure. The first pseudo-two-stage pipeline structure includes a first pseudo-two-stage pipeline and a second pseudo-two-stage pipeline. The second pseudo-two-stage pipeline structure includes a first pseudo-two-stage pipeline and a second pseudo-two-stage pipeline. The control method includes acquiring and judging RV32I instructions; if the RV32I instruction is a first instruction type, the first pseudo-two-stage pipeline structure is selected for instruction execution; if the RV32I instruction is a second instruction type, the second pseudo-two-stage pipeline structure is selected for instruction execution. The embodiments of this application can reduce the power consumption of the processor during data processing without increasing the processor's area structure, thereby improving the processor's performance ratio. This application can be widely applied in the field of integrated circuit structure technology.

Description

Technical Field

[0001] This application relates to the field of integrated circuit architecture technology, and in particular to a pseudo two-stage pipelined processor based on RV32I instructions and its control method. Background Technology

[0002] Traditional RISC-V processors that follow a parallel data path have limitations in reducing power consumption and area due to the constraints of the number of registers. On the other hand, RISC-V processors that follow a serial data path architecture cannot adequately balance performance.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a pseudo two-stage pipelined processor based on RV32I instructions and its control method, which can reduce the cycle time required for data transfer between modules, thereby reducing the power consumption of the processor for data processing without increasing the processor's area structure.

[0005] To achieve the above objectives, one aspect of this application proposes a pseudo-two-stage pipelined processor based on the RV32I instruction set. The processor includes a first pseudo-two-stage pipeline structure and a second pseudo-two-stage pipeline structure. The first pseudo-two-stage pipeline structure includes a first pseudo-two-stage pipeline and a second pseudo-two-stage pipeline. The second pseudo-two-stage pipeline structure includes a first pseudo-two-stage pipeline and a second pseudo-two-stage pipeline. The output of the first pseudo-two-stage pipeline is connected to the input of the second pseudo-two-stage pipeline, and the output of the first pseudo-two-stage pipeline is connected to the input of the second pseudo-two-stage pipeline. Wherein:

[0006] The first stage of the first pseudo-secondary pipeline is used to acquire RV32I instructions and execute the RV32I instructions;

[0007] The second stage of the first pseudo-secondary pipeline is used to access and write back the data generated by executing the RV32I instructions.

[0008] The first stage of the second pseudo-secondary pipeline is used to acquire RV32I instructions and pre-execute the RV32I instructions;

[0009] The second pseudo-secondary pipeline stage is used to execute the RV32I instructions and write back the generated data.

[0010] In some embodiments, the first stage of the first pseudo-secondary pipeline includes a first instruction fetch module, a first decoding module, a first register file module, and a first execution module. The output of the first instruction fetch module is connected to the input of the first decoding module, the first output of the first decoding module is connected to the input of the first register file module, and the second output of the first decoding module is connected to the input of the first execution module.

[0011] The first instruction acquisition module is used to acquire RV32I instructions, wherein the RV32I instructions include fetch signals and fetch addresses;

[0012] The first decoding module is used to obtain the operation requirements of the RV32I instruction, the immediate value of the RV32I instruction, the source register address of the RV32I instruction, and the destination register address of the RV32I instruction;

[0013] The first register file module is used to store the data generated by the RV32I instruction;

[0014] The first execution module is used to perform data execution processing according to the operation requirements of the RV32I instruction.

[0015] In some embodiments, the second stage of the first pseudo-secondary pipeline includes a storage access module and a first write-back module. The input of the storage access module is connected to the first output of the first execution module, the first input of the first write-back module is connected to the second output of the first execution module, and the output of the storage access module is connected to the second input of the first write-back module, wherein:

[0016] The storage access module is used to access the stored data in the data storage device;

[0017] The first write-back module is used to write back the data generated by the first execution module to the first register file module or to write back the stored data of the access data storage device to the first register file module.

[0018] In some embodiments, the first stage of the second pseudo-secondary pipeline includes a second instruction fetch module, a second decoding module, a second register file module, and a pre-execution module. The output of the second instruction fetch module is connected to the input of the second decoding module, the output of the second decoding module is connected to the input of the second register file module, and the output of the second register file module is connected to the input of the pre-execution module.

[0019] The second instruction acquisition module is used to acquire RV32I instructions, which include fetch signals and fetch addresses;

[0020] The second decoding module is used to obtain the operation requirements of the RV32I instruction, the immediate value of the RV32I instruction, the source register address of the RV32I instruction, and the destination register address of the RV32I instruction;

[0021] The second register file module is used to store the data generated by the RV32I instructions;

[0022] The pre-execution module is used to perform data execution processing in advance according to the operational requirements of the RV32I instruction.

[0023] In some embodiments, the second stage of the second pseudo-secondary pipeline includes an idle cycle module, a second execution module, and a second write-back module. The input of the idle cycle module is connected to the output of the pre-execution module, the output of the idle cycle module is connected to the input of the second execution module, and the output of the second execution module is connected to the input of the second write-back module, wherein:

[0024] The idle cycle module is used to perform idle processing on the processor;

[0025] The second execution module is used to perform data execution processing according to the operation requirements of the RV32I instruction;

[0026] The second write-back module is used to write the data generated by the second execution module back to the second register file module.

[0027] In some embodiments, a dual-channel structure is further introduced into the first instruction fetching module, the second instruction fetching module, the pre-execution module, the first register file module, and the second register file module. The dual-channel structure includes a main shift register and a secondary shift register, wherein:

[0028] The main shift register is used to shift or temporarily store the data generated by the current instruction when no data conflict occurs or when the sub-shift register still holds the data generated by the previous instruction.

[0029] The secondary shift register is used to shift or temporarily store the data generated by the current instruction when the primary shift register still holds the data generated by the previous instruction.

[0030] To achieve the above objectives, another aspect of this application proposes a control method for a pseudo two-stage pipelined processor based on RV32I instructions, the control method comprising:

[0031] Obtain RV32I instructions and perform judgment;

[0032] If the RV32I instruction is of the first instruction type, then the first pseudo-secondary pipeline structure is selected for instruction execution processing;

[0033] If the RV32I instruction is of the second instruction type, then the second pseudo-secondary pipeline structure is selected for instruction execution processing.

[0034] In some embodiments, the first pseudo-secondary pipeline structure performs instruction execution processing, including:

[0035] The RV32I instruction is acquired and decoded to obtain the first decoding result.

[0036] Determine whether the first decoded result is a non-source register dependent instruction. If it is, proceed directly to the instruction execution stage. If it is not, first read the instruction from the register file and then proceed to the instruction execution stage to generate the instruction execution result.

[0037] The instruction execution results are stored and written back to complete the instruction execution process of the first pseudo-secondary pipeline structure.

[0038] In some embodiments, the second pseudo-secondary pipeline structure performs instruction execution processing, including:

[0039] The RV32I instruction is acquired and decoded to obtain the second decoding result.

[0040] Based on the second decoding result, pre-execution processing of the instructions is performed to obtain the pre-execution result;

[0041] Based on the pre-execution results, execution and write-back operations are performed to complete the instruction execution processing of the second pseudo-secondary pipeline structure.

[0042] In some embodiments, a dual-channel structure is introduced for instruction execution processing, wherein the dual-channel structure is used to shift or temporarily store the current instruction.

[0043] The embodiments of this application include at least the following beneficial effects: This application provides a pseudo two-stage pipelined processor based on RV32I instructions and its control method. This scheme adopts a first pseudo two-stage pipeline structure and a second pseudo two-stage pipeline structure. Both the first pseudo two-stage pipeline structure and the second pseudo two-stage pipeline structure adopt a serial data path structure, which can reduce the cycle required for data transfer between modules, thereby reducing the power consumption of the processor in data processing without increasing the area of ​​the processor. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a pseudo two-stage pipelined processor based on the RV32I instruction provided in an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of the dual-channel structure provided in the embodiments of this application;

[0046] Figure 3 This is a schematic diagram of the processor data path structure of the pseudo-two-stage pipeline structure provided in the embodiments of this application;

[0047] Figure 4 This is a data processing schematic diagram of a control method for a pseudo two-stage pipelined processor based on RV32I instructions provided in an embodiment of this application.

[0048] Reference numerals: 1. First pseudo-secondary pipeline structure; 2. Second pseudo-secondary pipeline structure. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of processors and control methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0050] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0051] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0053] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0054] Embedded IoT devices are typically used for information sensing and signal processing, and often need to operate continuously for days or longer in environments with limited power supplies. These devices do not have high performance requirements but are quite sensitive to power consumption. Therefore, a low-power processor is needed to manage the operation of the entire system. RISC-V is an emerging open-source instruction set architecture that allows users to remove redundant hardware and implement the instruction set in a modular way. The flexibility of RISC-V makes it possible to design low-power processors suitable for specific IoT nodes.

[0055] In the low-power design techniques of RISC-V processors, retaining only the integer instruction set is an important method for maintaining low power consumption. Furthermore, different architectures can be adopted to reduce power consumption and area.

[0056] Some shortcomings exist in related technologies. For example, the open-source RISC-V processor SERV sets the data path to 1-bit, significantly reducing the number of registers required for processing instructions, thereby optimizing power consumption and area overhead, with a power consumption of 55μW / MHz@0.8V. However, this architecture severely impacts processor performance due to its excessively long data transmission time. Another example is a single-cycle RISC-V processor, which achieves a power consumption of 14.7mW@50MHz and a thickness of 0.24mm. 2 The chip area is limited. A single-cycle design is characterized by all operations of an instruction being completed within a single cycle. Compared to other processor architectures, the advantage of a single-cycle design is that it doesn't require many registers to store data generated during instruction processing, thus saving area and power consumption. However, it inevitably puts enormous pressure on the timing of the critical path, making the design more difficult. Another example is a non-pipelined multi-cycle RISC-V processor, which can construct different data transfer paths for different instructions in the instruction set through configuration parameters. The non-pipelined multi-cycle design breaks down an instruction into multiple tasks, each requiring one or more cycles. Only one instruction is processed at a time. This design improves average performance by 54.7% compared to traditional non-pipelined multi-cycle architectures. However, this architecture requires a large number of registers, resulting in additional area and power consumption overhead. Furthermore, because processing a new instruction requires waiting for the previous instruction to complete, the performance of processors using this architecture is also somewhat limited.

[0057] In view of this, this application proposes a pseudo-two-stage pipelined processor based on the RV32I instruction set, building upon the serial data path architecture. A traditional pipelined architecture refers to completing one task of the instruction's lifecycle per cycle. However, in processors following a serial data path, data transfer between modules takes at least 32 clock cycles, making it difficult to implement a traditional pipelined architecture. Therefore, the processor proposed in this work introduces an additional shift register to divide and combine a portion of the instruction cycle's tasks into two stages that consume the same number of clock cycles, achieving a simulated pipeline effect within the serial data path. Based on this pseudo-pipeline structure, a low-power RISC-V processor based on the RV32I instruction set is implemented.

[0058] Reference Figure 1 , Figure 1 This is a schematic diagram of a pseudo two-stage pipelined processor based on the RV32I instruction set, provided in an embodiment of the present invention. (Refer to...) Figure 1 The processor includes a first pseudo-secondary pipeline structure 1 and a second pseudo-secondary pipeline structure 2. The first pseudo-secondary pipeline structure includes a first pseudo-secondary pipeline stage 1 and a first pseudo-secondary pipeline stage 2. The second pseudo-secondary pipeline structure includes a second pseudo-secondary pipeline stage 1 and a second pseudo-secondary pipeline stage 2. The output terminal of the first pseudo-secondary pipeline stage 1 is connected to the input terminal of the first pseudo-secondary pipeline stage 2, and the output terminal of the second pseudo-secondary pipeline stage 1 is connected to the input terminal of the second pseudo-secondary pipeline stage 2.

[0059] In this embodiment, the first pseudo-two-stage pipeline structure includes an instruction fetch section, a decode section, a register file section, an execution section, a memory access section, and a write-back section. The instruction fetch section and the decode section are connected, the decode section is connected to both the register file section and the execution section, and the execution section is connected to both the memory access section and the write-back section. The second pseudo-two-stage pipeline structure includes an instruction fetch section, a decode section, a register file section, a preprocessing section, an idle cycle section, an execution section, and a write-back section. These sections are connected sequentially.

[0060] The first stage of the first pseudo-secondary pipeline is used to fetch and execute RV32I instructions;

[0061] The first pseudo-secondary pipeline includes a first instruction fetch module, a first decoding module, a first register file module, and a first execution module. The output of the first instruction fetch module is connected to the input of the first decoding module, the first output of the first decoding module is connected to the input of the first register file module, and the second output of the first decoding module is connected to the input of the first execution module. The first instruction fetch module is used to fetch RV32I instructions, which include fetch signals and fetch addresses. The first decoding module is used to fetch the operation requirements, immediate values, source register addresses, and destination register addresses of the RV32I instructions. The first register file module is used to store the data generated by the RV32I instructions. The first execution module is used to perform data execution processing according to the operation requirements of the RV32I instructions.

[0062] The second stage of the first pseudo-secondary pipeline is used to access and write back data generated by executing RV32I instructions.

[0063] The second stage of the first pseudo-secondary pipeline includes a storage access module and a first write-back module. The input of the storage access module is connected to the first output of the first execution module, the first input of the first write-back module is connected to the second output of the first execution module, and the output of the storage access module is connected to the second input of the first write-back module. The storage access module is used to access the stored data in the data storage device. The first write-back module is used to write the data generated by the first execution module back to the first register file module or to write the accessed stored data in the data storage device back to the first register file module.

[0064] The first stage of the second pseudo-secondary pipeline is used to fetch RV32I instructions and pre-execute RV32I instructions;

[0065] The first stage of the second pseudo-secondary pipeline includes a second instruction fetch module, a second decoding module, a second register file module, and a pre-execution module. The output of the second instruction fetch module is connected to the input of the second decoding module, the output of the second decoding module is connected to the input of the second register file module, and the output of the second register file module is connected to the input of the pre-execution module. The second instruction fetch module is used to fetch RV32I instructions, which include fetch signals and fetch addresses. The second decoding module is used to fetch the operation requirements, immediate values, source register addresses, and destination register addresses of the RV32I instructions. The second register file module is used to store the data generated by the RV32I instructions. The pre-execution module is used to pre-process the data according to the operation requirements of the RV32I instructions.

[0066] The second pseudo-secondary pipeline is used to execute RV32I instructions and write back the generated data.

[0067] The second pseudo-second-stage pipeline includes an idle cycle module, a second execution module, and a second write-back module. The input of the idle cycle module is connected to the output of the pre-execution module, the output of the idle cycle module is connected to the input of the second execution module, and the output of the second execution module is connected to the input of the second write-back module. The idle cycle module is used to perform idle processing on the processor. The second execution module is used to perform data execution processing according to the operation requirements of the RV32I instructions. The second write-back module is used to write the data generated by the second execution module back to the second register file module.

[0068] To further clarify, the instruction fetch section, comprising the first and second instruction fetch modules, sends a fetch signal and fetch address to the program memory, fetches the instruction from the program memory, and issues it to the decode module, taking one clock cycle. The first and second decode modules retrieve the corresponding operation requirements, immediate values, source register address, and destination register address from the instruction. The kernel selects the appropriate pseudo-pipeline structure based on the operation requirements of the instruction. If the first pseudo-secondary pipelining structure is used, the kernel further determines whether to issue the decoded information from the instruction to the register file section or the execution section. If the current instruction is a source register dependent instruction, the information is issued to the register file section; otherwise, it is issued to the execution section, taking one clock cycle in total. The first and second register file modules store the data generated by the instruction operation; when a write signal is received, the data is stored. Upon receiving the corresponding address and read signal, data is sent to the execution module, taking a total of 34 clock cycles. The first and second execution modules handle the required operations for each instruction, also taking 34 clock cycles. The pre-execution section exists only in the second pseudo-secondary pipeline structure and is used to pre-process some data. The memory access section accesses memory to read or store data. Since not all instructions require memory access, they are shown as dashed lines in the diagram. Instructions that do not require memory access idle for 3 cycles during this period. The idle cycle module allows the processor core to idle for 3 cycles. The first and second write-back modules write the executed data back to the register file, taking a total of 33 clock cycles.

[0069] In this embodiment, a dual-channel structure is introduced for the first instruction fetch module, the second instruction fetch module, the pre-execution module, the first register file module, and the second register file module. The dual-channel structure includes a main shift register and a secondary shift register. The main shift register is used to shift or temporarily store the data generated by the current instruction when no data conflict occurs or when the secondary shift register still holds the data generated by the previous instruction. The secondary shift register is used to shift or temporarily store the data generated by the current instruction when the main shift register still holds the data generated by the previous instruction.

[0070] Specifically, such as Figure 2 As shown, to avoid deploying two pseudo-pipeline structures simultaneously, a dual-channel structure with two shift registers is deployed in the instruction fetch unit, pre-execution unit, and storage data processing unit. The dual-channel structure includes a main shift register and a secondary shift register. The main shift register is used to shift or temporarily store data when no data conflict occurs or when the secondary shift register still holds data generated by the previous instruction. The secondary shift register is used to shift or temporarily store data generated by the current instruction when the main shift register still holds data generated by the previous instruction.

[0071] Please see Figure 4 This application also provides a control method for a pseudo two-stage pipelined processor based on RV32I instructions, which can implement the above-mentioned pseudo two-stage pipelined processor based on RV32I instructions. The control method includes:

[0072] S1. Obtain RV32I instructions and make a judgment;

[0073] S2. If the RV32I instruction is of the first instruction type, then the first pseudo-secondary pipeline structure is selected for instruction execution processing.

[0074] Specifically, the RV32I instruction is obtained and decoded to obtain the first decoding result; it is determined whether the first decoding result is a non-source register dependent instruction. If it is, the instruction execution stage is directly entered; otherwise, the instruction is first read from the register file and then the instruction execution stage is entered to generate the instruction execution result; the instruction execution result is stored and written back to complete the instruction execution process of the first pseudo-secondary pipeline structure.

[0075] In this embodiment, the processor core selects either a first pseudo-two-stage pipeline or a second pseudo-two-stage pipeline based on the instruction type in the RV32I instruction set. The first pseudo-two-stage pipeline describes the pseudo-pipeline structure used in most cases for instruction types. The first stage of the pseudo-pipeline starts with instruction fetch (IF), and each instruction fetch and decode (ID) task takes one clock cycle (CLK). The kernel determines the next task to execute based on the decoding result. If the current instruction is a non-source register dependent instruction, it can directly enter the execution (EX) stage; otherwise, it needs to read the register file first. After the kernel completes execution, it enters the second stage. The second stage contains only two tasks: write back (WB) and memory access (MA). If the current instruction requires it, the write back and memory access tasks are executed as needed. If the current instruction is a store-in or store-out instruction, the second stage will first access memory and then perform the write back task. Otherwise, the kernel will idle for three clock cycles (dummy) before writing back to adapt the overall structure to fetch or store instructions. While entering the second stage, the kernel fetches and processes new instructions, repeating this process to form a pipeline-like structure.

[0076] In the first pseudo-two-stage pipeline architecture, instructions processed using this architecture divide the instruction cycle into six tasks: instruction fetch, decode, register file read, execute, memory access, and write-back. Instruction fetch, decode, register file read, and execute are placed in the first stage of the pseudo-two-stage pipeline, while memory access and write-back are placed in the second stage. After the processor boots up, the pseudo-pipeline also starts, first processing the instruction fetch task within the instruction cycle. At this point, as... Figure 3As shown, the instruction fetch module sends a 32-bit parallel instruction address signal to the program memory. Upon receiving this signal, the program memory sends a 32-bit instruction signal to the decoding unit in the processor. This leads to the decoding stage of the pipeline. At this stage, the module decodes the instruction according to the RV32I instruction set specification and uses a shift register to convert the decoded result into a serial output for subsequent pipeline steps. Simultaneously, a series of control signals are generated to control the pipeline operation. Furthermore, the decoding unit serially sends an address signal to the source register to retrieve the corresponding value, and the source register serially sends data rs1_data or rs2_data. This process takes a total of 32 CLKs. The execution stage and the register file fetch stage are embedded in the same stage. Signals output from the register file are immediately sent to the corresponding units, such as the ALU or instruction fetch unit, for serial execution of corresponding operations, such as logical calculations and calculation of jump addresses. For instructions that require memory access, the memory access address is calculated by the pre-execution unit. Subsequently, the kernel determines the operation of the second-stage pipeline based on whether the current instruction is a memory-related instruction or requires a write-back. If the current instruction requires memory access, the memory access must be performed first, taking three clock cycles from the kernel issuing the memory address to the kernel receiving the returned handshake signal. If the current instruction does not require memory access, the kernel will idle for three clock cycles to ensure overall timing consistency. If the current instruction requires register write-back, all data to be written back, including immediate data imm_dat, arithmetic data ALU_dat, shift data shift_dat, address data pc_dat, and memory data mem_dat, are converged in a data selector, and the required data is serially shifted into a shift register according to the instruction. This shift register acts as a D flip-flop in the parallel design, used to isolate the two-stage pipeline. Data is serially shifted out of the shift register in the second stage and sent to the register file to achieve write-back. The write-back process takes a total of 33 clock cycles. Upon entering the second stage of the pseudo-pipeline, the instruction fetch unit issues a new instruction fetch address and begins processing a new instruction. This process is repeated in a loop to achieve the effect of simulating a two-stage pipeline.

[0077] S3. If the RV32I instruction is of the second instruction type, then the second pseudo-secondary pipeline structure is selected for instruction execution.

[0078] Specifically, the RV32I instruction is acquired and decoded to obtain a second decoding result; instruction pre-execution processing is performed based on the second decoding result to obtain a pre-execution result; and execution and write-back operations are performed based on the pre-execution result to complete the instruction execution processing of the second pseudo-secondary pipeline structure.

[0079] In this embodiment, the second pseudo-secondary pipeline structure is the pipeline structure followed when processing branch jump, shift, or compare set instructions. Unlike the first pseudo-secondary pipeline structure, after accessing registers in the first stage, pre-execution of data is required, while execution is scheduled in the second stage. Branch jump and compare set instructions are conditional execution instructions; during pre-execution, the conditions required by the instructions are calculated and judged. The kernel then performs further corresponding operations in the second stage based on the judgment result. After entering the second stage, the kernel first idles for three clock cycles to accommodate store-and-fetch instructions. Execution and write-back operations are embedded in the same stage, and the data obtained during execution can be immediately returned to the register serially.

[0080] In the second pseudo-second-stage pipeline, the pipeline structure is used when the instruction to be processed is a branch jump, shift, or compare set instruction from the RV32I instruction set. Similar to the first pseudo-second-stage pipeline, the second pseudo-second-stage pipeline also requires instruction fetching and decoding, each taking two clock cycles. Since these instruction types all require values ​​from the source register, after the decoding stage, a register fetch stage is entered. Unlike the first pseudo-second-stage pipeline, the pre-execution task and the register fetch task are embedded in the same time period. The pre-execution task is used to process some necessary data first. For branch jump instructions, the pre-execution stage is used to calculate the jump condition, and based on the calculation result, the jump is executed in the second-stage pipeline. For shift instructions, the pre-execution stage is used to shift the data obtained from the source register into a shift register, which is then used in the second-stage pipeline for shifting. For compare set instructions, the pre-execution stage is used to compare two numbers, and the comparison result is used to assign a value to the destination register in the execution stage of the second-stage pipeline. Since none of the instructions involved require memory access, after entering the second stage of the pseudo-pipeline, the kernel needs to idle for three clock cycles to ensure consistency with the first pseudo-second-stage pipeline structure before entering the execution phase. The execution phase and write-back phase are placed in the same time period, and data generated during the execution phase can be immediately returned to the registers serially. Among the three types of instructions conforming to the second pseudo-second-stage pipeline structure, branch jump instructions do not require write-back to registers. Figure 1 The write-back phase is indicated by a dashed box.

[0081] The data flow in the second pseudo-secondary pipeline structure can also be... Figure 3 As can be seen, after the decoding task is completed, the data is sent serially to the pre-execution unit. The pre-execution unit is equipped with a shift register, which can be used to temporarily store the shift values ​​or branch jump calculation addresses required by shift-type instructions. Subsequently, in the second-stage pipeline, the corresponding instruction operations can still be executed using data shifting in the pre-execution unit.

[0082] Furthermore, based on the proposed pseudo-two-stage pipeline architecture of the RISC-V processor data path, such as... Figure 3 As shown, the data path structure includes a register file module, an instruction fetch module, a program memory, a decoding unit, a pre-execution unit, a storage data processing unit, a data memory, an arithmetic logic unit (ALU), and several shift registers. The register file module stores instruction-related data; the instruction fetch module calculates the instruction fetch address; the program memory stores the input instruction signals and sends the instructions to the decoding unit; the decoding unit decodes the instructions to obtain information, generates several control signals, and converts parallel signals into serial signals via shift registers, sending them to the instruction fetch module, the pre-execution unit, and the ALU; the pre-execution unit calculates the address required for storage access or temporarily stores data from the register file; the storage data processing unit temporarily stores data to be written to the data memory or receives return data from the data memory, and converts parallel data into serial data via shift registers and writes it back to the register file; the data memory stores data generated by S-type instructions; the arithmetic logic unit performs addition, subtraction, Boolean operations, and comparison operations on the data; and the shift registers perform serial-to-parallel conversion of the data to implement a serial data path and perform calculations on the data during the shifting process.

[0083] It should be further explained that, Figure 3 The dashed lines indicate that data is transmitted in parallel at 32-bit intervals along this path, while the solid lines indicate that data is transmitted serially at 1-bit intervals. Instructions are fetched from program memory and sent to the decoding unit, which generates a series of control signals. The immediate values ​​in the instructions are decoded and converted into 1-bit values ​​via a shift register (Shift Register, SR) before being sent to the pre-execution unit or the Algorithm Logic Unit (ALU) for computation. All data that needs to be written back to the register file, including the immediate value data imm_dat, the arithmetic data ALU_dat, the shift data shift_dat, the address data pc_dat, and the storage data mem_dat, converge in a data selector and, according to the instruction, shift the required data into a shift register. This shift register acts as a D flip-flop in the parallel design, isolating the two pipeline stages. Data is shifted out of the shift register in the second stage and sent to the register file for write-back.

[0084] Furthermore, regarding the dual-channel structure in this embodiment, implementing both pipelined structures simultaneously would lead to data conflicts. Since the kernel needs to occupy a shift register to perform two consecutive operations on data related to the same instruction during the processing of certain instructions, this structure was implemented to avoid consecutive instructions occupying the same shift register of the same module. Figure 2 The system contains a primary and a secondary shift register, each with a 32-bit width, for storing and processing data. The first and second data are connected to a data selector, which selects either the first or second data to be serially input into one of the shift registers based on a control signal generated by instruction decoding. The activity of the shift registers is controlled by a shift enable signal. There are two output options: serial output, where both shift registers are connected to a data selector and the serial output is selected based on the control signal; and parallel output, where the entire shift register data is output directly based on the control signal.

[0085] like Figure 2 As shown, an additional shift register for computation is added to the instruction fetch unit, pre-execution unit, and data processing unit of the proposed processor, forming a dual-channel architecture. The two registers have a master-slave relationship. When there is no conflict due to simultaneous use of current and subsequent instructions, only the master shift register participates in instruction processing. When a data conflict is about to occur between the current and subsequent instructions, the two shift registers work alternately, calculating the values ​​required by the two instructions respectively. In the instruction fetch unit, deploying a dual-channel architecture allows for the simultaneous calculation of the address to be fetched in the normal order and the address to be jumped to when processing jump-type instructions. In the pre-execution unit, deploying a dual-channel architecture allows for temporary data storage when processing shift, memory access, and compare-set instructions. In the memory and data processing unit, deploying a dual-channel architecture allows for the simultaneous temporary storage of two signals received from the data memory when processing memory access instructions, and converting them into serial signals that are then transmitted to subsequent pipeline stages.

[0086] It is understood that the content of the above method embodiments is applicable to this processor embodiment. The specific functions implemented by this processor embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0087] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A pseudo two-stage pipelined processor based on RV32I instructions, characterized in that, The processor includes a first pseudo-second-stage pipeline structure and a second pseudo-second-stage pipeline structure. The first pseudo-second-stage pipeline structure includes a first pseudo-second-stage pipeline and a second pseudo-second-stage pipeline. The second pseudo-second-stage pipeline structure includes a first pseudo-second-stage pipeline and a second pseudo-second-stage pipeline. The output of the first pseudo-second-stage pipeline is connected to the input of the second pseudo-second-stage pipeline, and the output of the first pseudo-second-stage pipeline is connected to the input of the second pseudo-second-stage pipeline. The first stage of the first pseudo-secondary pipeline is used to acquire RV32I instructions and execute the RV32I instructions; The second stage of the first pseudo-secondary pipeline is used to access and write back the data generated by executing the RV32I instructions. The first stage of the second pseudo-secondary pipeline is used to acquire RV32I instructions and pre-execute the RV32I instructions; The second pseudo-secondary pipeline is used to execute the RV32I instructions and write back the generated data. The first pseudo-second-level pipeline includes a first instruction fetch module, a first decode module, a first register file module, and a first execution module. The second pseudo-second-level pipeline includes a memory access module and a first write-back module. The first pseudo-second-level pipeline includes a second instruction fetch module, a second decode module, a second register file module, and a pre-execution module. The second pseudo-second-level pipeline includes an idle cycle module, a second execution module, and a second write-back module.

2. The processor according to claim 1, characterized in that, The output of the first instruction acquisition module is connected to the input of the first decoding module, the first output of the first decoding module is connected to the input of the first register file module, and the second output of the first decoding module is connected to the input of the first execution module, wherein: The first instruction acquisition module is used to acquire RV32I instructions, wherein the RV32I instructions include fetch signals and fetch addresses; The first decoding module is used to obtain the operation requirements of the RV32I instruction, the immediate value of the RV32I instruction, the source register address of the RV32I instruction, and the destination register address of the RV32I instruction; The first register file module is used to store the data generated by the RV32I instruction; The first execution module is used to perform data execution processing according to the operation requirements of the RV32I instruction.

3. The processor according to claim 2, characterized in that, The input terminal of the storage access module is connected to the first output terminal of the first execution module, the first input terminal of the first write-back module is connected to the second output terminal of the first execution module, and the output terminal of the storage access module is connected to the second input terminal of the first write-back module, wherein: The storage access module is used to access the stored data in the data storage device; The first write-back module is used to write back the data generated by the first execution module to the first register file module or to write back the stored data of the access data storage device to the first register file module.

4. The processor according to claim 1, characterized in that, The output of the second instruction acquisition module is connected to the input of the second decoding module, the output of the second decoding module is connected to the input of the second register file module, and the output of the second register file module is connected to the input of the pre-execution module, wherein: The second instruction acquisition module is used to acquire RV32I instructions, which include fetch signals and fetch addresses; The second decoding module is used to obtain the operation requirements of the RV32I instruction, the immediate value of the RV32I instruction, the source register address of the RV32I instruction, and the destination register address of the RV32I instruction; The second register file module is used to store the data generated by the RV32I instructions; The pre-execution module is used to perform data execution processing in advance according to the operational requirements of the RV32I instruction.

5. The processor according to claim 4, characterized in that, The input of the empty cycle module is connected to the output of the pre-execution module, the output of the empty cycle module is connected to the input of the second execution module, and the output of the second execution module is connected to the input of the second write-back module, wherein: The idle cycle module is used to perform idle processing on the processor; The second execution module is used to perform data execution processing according to the operation requirements of the RV32I instruction; The second write-back module is used to write the data generated by the second execution module back to the second register file module.

6. The processor according to claim 4, characterized in that, It also includes introducing a dual-channel structure to the first instruction fetch module, the second instruction fetch module, the pre-execution module, the first register file module, and the second register file module. The dual-channel structure includes a main shift register and a secondary shift register, wherein: The main shift register is used to shift or temporarily store the data generated by the current instruction when no data conflict occurs or when the sub-shift register still holds the data generated by the previous instruction. The secondary shift register is used to shift or temporarily store the data generated by the current instruction when the primary shift register still holds the data generated by the previous instruction.

7. A control method for a pseudo two-stage pipelined processor based on RV32I instructions as described in any one of claims 1-6, characterized in that, The control method includes: Obtain RV32I instructions and perform judgment; If the RV32I instruction is of the first instruction type, then the first pseudo-secondary pipeline structure is selected for instruction execution processing; If the RV32I instruction is of the second instruction type, then the second pseudo-secondary pipeline structure is selected for instruction execution processing.

8. The method according to claim 7, characterized in that, The first pseudo-secondary pipeline structure performs instruction execution processing, including: The RV32I instruction is acquired and decoded to obtain the first decoding result. Determine whether the first decoded result is a non-source register dependent instruction. If it is, proceed directly to the instruction execution stage. If it is not, first read the instruction from the register file and then proceed to the instruction execution stage to generate the instruction execution result. The instruction execution results are stored and written back to complete the instruction execution process of the first pseudo-secondary pipeline structure.

9. The method according to claim 7, characterized in that, The second pseudo-secondary pipeline structure performs instruction execution processing, including: The RV32I instruction is acquired and decoded to obtain the second decoding result. Based on the second decoding result, pre-execution processing of the instructions is performed to obtain the pre-execution result; Based on the pre-execution results, execution and write-back operations are performed to complete the instruction execution processing of the second pseudo-secondary pipeline structure.

10. The method according to claim 7, characterized in that, It also includes the introduction of a dual-channel structure for instruction execution processing, wherein the dual-channel structure is used to shift or temporarily store the current instruction.

Images