A single memory space cache DMA command group structure

Abstract

The present invention discloses a single storage space cache DMA command group structure, which belongs to the field of direct storage access, and includes a host, a virtual group configuration module, a DMA command group cache module and a slave; wherein the input end of the virtual group configuration module is connected to the output end of the host, and the output end is connected to the input end of the DMA command group cache module; the input end of the DMA command group cache module is simultaneously connected to the output end of the host and the output end of the virtual group configuration module, and the output end is connected to the input end of the slave. The present invention controls the read and write of the DMA command group cache module through the virtual group configuration module, and allocates the command group to a suitable virtual group, thereby improving the storage space utilization rate of the DMA command group.

Description

Technical Field

[0001] The present invention relates to the technical field of direct storage access, and in particular to a single storage space cache DMA command group structure. Background Art

[0002] In today's hierarchical storage, DMA (Direct Memory Access) is commonly used to provide high-speed data transmission between peripherals and memory or between memory and memory. Without CPU intervention, data can be quickly transferred through DMA, saving CPU resources. The role of DMA is to realize direct data transmission, eliminating the process of traditional data transmission that requires CPU participation.

[0003] With increasingly complex storage requirements, a DMA command group usually contains multiple DMA commands. In order to improve data transfer efficiency, ping-pong buffers are often used to store DMA commands, that is, when the current buffer executes a DMA command group, another buffer caches the next command group. However, while ping-pong buffers improve efficiency, they also waste storage space. Therefore, while ensuring the transfer efficiency of DMA command groups, effectively saving storage space is an important part of optimizing the cache DMA command group strategy. Summary of the invention

[0004] The object of the present invention is to provide a single storage space cache DMA command group structure to solve the problems in the background technology.

[0005] To solve the above technical problems, the present invention provides a single storage space cache DMA command group structure, including a host, a virtual Group configuration module, a DMA command group cache module and a slave; wherein,

[0006] The input end of the virtual Group configuration module is connected to the output end of the host, and the output end of the virtual Group configuration module is connected to the input end of the DMA command group cache module; the virtual Group configuration module is used to receive a host status signal, generate a read-write control signal according to the received status signal, and send the read-write control signal to the DMA command group cache module to perform DMA command group cache control;

[0007] The input end of the DMA command group cache module is connected to the output end of the host and the output end of the virtual Group configuration module at the same time, and the output end of the DMA command group cache module is connected to the input end of the slave; the DMA command group cache module is used to cache the DMA command group, and perform DMA command group cache control according to the read and write control signal sent by the virtual Group configuration module;

[0008] The DMA command group buffer module receives the DMA command group sent by the host, and completes the transfer of the DMA command according to the read-write enable signal generated by the virtual Group configuration module; the slave receives and executes the DMA command group.

[0009] In one embodiment, the virtual Group configuration module adds a command enable signal Enable after a single command in the DMA command group, and uses it as an enable signal for writing to the DMA command group cache module; the virtual Group configuration module adds a command group enable signal Launch after the DMA command group ends, and uses it as an enable signal for reading from the DMA command group cache module.

[0010] In one embodiment, the virtual Group configuration module includes two groups of virtual Groups, namely Group0 and Group1, which are executed sequentially. After the Launch signal enables the current Group, the current Group is put into a busy state until the current DMA command group is fully executed and the busy state of the current Group ends. During this period, the next command group enables another Group.

[0011] In one embodiment, there are 7 states of Group0 and Group1 in the virtual Group configuration module, namely, "Group0 idle / Group1 idle", "Group0 cache / Group1 idle", "Group0 busy / Group1 idle", "Group0 busy / Group1 cache", "Group0 idle / Group1 cache", "Group0 idle / Group1 busy", and "Group0 cache / Group1 busy";

[0012] In the "Group0 Idle / Group1 Idle" state, Group0 has a higher priority than Group1 by default;

[0013] In the "Group0 Idle / Group1 Idle" state, if Enable is enabled, the state jumps to "Group0 Cache / Group1 Idle";

[0014] In the "Group0 Cache / Group1 Idle" state, if Launch is enabled, the state jumps to "Group0 Busy / Group1 Idle";

[0015] In the "Group0 Busy / Group1 Idle" state, if there is no Enable, the state jumps to "Group0 Idle / Group1 Idle", and the execution of this DMA command group is completed; if there is Enable, the state jumps to "Group0 Busy / Group1 Cache";

[0016] In the "Group0 Busy / Group1 Cache" state, if the current DMA command group is executed and Launch is not enabled, the state jumps to "Group0 Idle / Group1 Cache"; if the current DMA command group is executed and Launch is enabled, the state jumps to "Group0 Idle / Group1 Busy";

[0017] In the "Group0 Idle / Group1 Cache" state, if Launch is enabled, the state jumps to "Group0 Idle / Group1 Busy";

[0018] In the "Group0 Idle / Group1 Busy" state, if there is no Enable, the state jumps to "Group0 Idle / Group1 Idle", and the execution of this DMA command group is completed; if there is Enable, the state jumps to "Group0 Cache / Group1 Busy";

[0019] In the "Group0 Cache / Group1 Busy" state, if the current DMA command group is executed and Launch is not enabled, the state jumps to "Group0 Cache / Group1 Idle"; if the current DMA command group is executed and Launch is enabled, the state jumps to "Group0 Busy / Group1 Idle".

[0020] The present invention provides a single storage space cache DMA command group structure, which controls the read and write of the DMA command group cache module through a virtual group configuration module, and allocates the command group to a suitable virtual group, thereby improving the storage space utilization of the DMA command group. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural block diagram of the present invention.

[0022] Figure 2 This is a state transition diagram of the virtual Group configuration module of the present invention. DETAILED DESCRIPTION

[0023] The following is a further detailed description of a single storage space cache DMA command group structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] In order to optimize the cache DMA command group strategy, the present invention provides a single storage space cache DMA command group structure, which can effectively improve the DMA storage space utilization and reduce hardware overhead.

[0025] The structural block diagram of the present invention is as follows: Figure 1 As shown, it includes a host 101, a virtual group configuration module 102, a DMA command group cache module 103, and a slave 104.

[0026] The host 101 sends a DMA command group, and the virtual group configuration module 102 is used to receive a status signal of the host 101 and send a read and write control signal of the DMA command group buffer module 103 .

[0027] The virtual Group configuration module 102 adds a command enable signal Enable after a single command in the DMA command group, and uses it as an enable signal for writing to the DMA command group cache module 103; the virtual Group configuration module 102 adds a command group enable signal Launch after the DMA command group ends (i.e., after the last Enable of this DMA command group), and uses it as an enable signal for reading from the DMA command group cache module 103.

[0028] The virtual group configuration module 102 includes two virtual groups, namely Group0 and Group1, which are executed sequentially. After the Launch signal enables the current group, the current group is in a busy state until the current DMA command group is fully executed and the current group busy state ends. During this period, the next command group enables another group.

[0029] The status jumps of Group0 and Group1 in the virtual Group configuration module 102 are as follows: Figure 2 As shown, there are 7 states, namely "Group0 Idle / Group1 Idle", "Group0 Cache / Group1 Idle", "Group0 Busy / Group1 Idle", "Group0 Busy / Group1 Cache", "Group0 Idle / Group1 Cache", "Group0 Idle / Group1 Cache", "Group0 Idle / Group1 Busy", and "Group0 Cache / Group1 Busy".

[0030] In the "Group0 Idle / Group1 Idle" state, Group0 has a higher priority than Group1 by default.

[0031] In the "Group0 Idle / Group1 Idle" state, if Enable is enabled (DMA command group is written into DMA command group cache module 103), the state jumps to "Group0 Cache / Group1 Idle".

[0032] In the "Group0 Cache / Group1 Idle" state, if Launch is enabled (the DMA command group is read from the DMA command group cache module 103 and executed), the state jumps to "Group0 Busy / Group1 Idle".

[0033] In the "Group0 busy / Group1 idle" state, if there is no Enable (DMA command group is written into the DMA command group cache module 103), the state jumps into "Group0 idle / Group1 idle", and the execution of this DMA command group is completed; if there is Enable (DMA command group is written into the DMA command group cache module 103), the state jumps into "Group0 busy / Group1 cache".

[0034] In the "Group0 Busy / Group1 Cache" state, if the current DMA command group is executed and Launch is not enabled (the DMA command group is read from the DMA command group cache module 103 and executed), the state jumps to "Group0 Idle / Group1 Cache"; if the current DMA command group is executed and Launch is enabled (the DMA command group is read from the DMA command group cache module 103 and executed), the state jumps to "Group0 Idle / Group1 Busy".

[0035] In the "Group0 Idle / Group1 Cache" state, if Launch is enabled (the DMA command group is read from the DMA command group cache module 103 and executed), the state jumps to "Group0 Idle / Group1 Busy".

[0036] In the "Group0 Idle / Group1 Busy" state, if there is no Enable (DMA command group is written into the DMA command group cache module 103), the state jumps to "Group0 Idle / Group1 Idle", and the execution of this DMA command group is completed; if there is Enable, the state jumps to "Group0 Cache / Group1 Busy".

[0037] In the "Group0 Cache / Group1 Busy" state, if the current DMA command group is executed and there is no Launch enable (the DMA command group is read from the DMA command group cache module 103 and executed), the state jumps to "Group0 Cache / Group1 Idle"; if the current DMA command group is executed and there is Launch enable (the DMA command group is read from the DMA command group cache module 103 and executed), the state jumps to "Group0 Busy / Group1 Idle".

[0038] The DMA command group buffer module 103 receives the DMA command group sent by the host 101 , and completes the transfer of the DMA command according to the read / write enable signal generated by the virtual group configuration module 102 .

[0039] The slave 104 receives and executes the DMA command group.

[0040] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A single storage space cache DMA command group device, characterized in that: It includes a host, a virtual Group configuration module, a DMA command group cache module and a slave; among which, The input end of the virtual Group configuration module is connected to the output end of the host, and the output end of the virtual Group configuration module is connected to the input end of the DMA command group cache module; the virtual Group configuration module is used to receive a host status signal, generate a read-write control signal according to the received status signal, and send the read-write control signal to the DMA command group cache module to perform DMA command group cache control; The input end of the DMA command group cache module is connected to the output end of the host and the output end of the virtual Group configuration module at the same time, and the output end of the DMA command group cache module is connected to the input end of the slave; the DMA command group cache module is used to cache the DMA command group, and perform DMA command group cache control according to the read and write control signal sent by the virtual Group configuration module; The DMA command group cache module receives the DMA command group sent by the host, and completes the transfer of the DMA command according to the read and write enable signal generated by the virtual Group configuration module; the slave receives and executes the DMA command group; The virtual Group configuration module adds a command enable signal Enable after a single command in a DMA command group, and uses it as an enable signal for writing into the DMA command group cache module; the virtual Group configuration module adds a command group enable signal Launch after the DMA command group ends, and uses it as an enable signal for reading from the DMA command group cache module; The virtual Group configuration module includes two groups of virtual Groups, namely Group0 and Group1, which are executed sequentially. After the Launch signal enables the current Group, the current Group is in a busy state until the current DMA command group is fully executed and the current Group's busy state ends. During this period, the next command group enables another Group.

2. The single storage space cache DMA command group device according to claim 1, characterized in that: There are 7 states of Group0 and Group1 in the virtual Group configuration module, namely "Group0 idle / Group1 idle", "Group0 cache / Group1 idle", "Group0 busy / Group1 idle", "Group0 busy / Group1 cache", "Group0 idle / Group1 cache", "Group0 idle / Group1 busy", "Group0 cache / Group1 busy"; In the "Group0 Idle / Group1 Idle" state, Group0 has a higher priority than Group1 by default; In the "Group0 Idle / Group1 Idle" state, if Enable is enabled, the state jumps to "Group0 Cache / Group1 Idle"; In the "Group0 Cache / Group1 Idle" state, if Launch is enabled, the state jumps to "Group0 Busy / Group1 Idle"; In the "Group0 Busy / Group1 Idle" state, if there is no Enable, the state jumps to "Group0 Idle / Group1 Idle", and the execution of this DMA command group is completed; if there is Enable, the state jumps to "Group0 Busy / Group1 Cache"; In the "Group0 Busy / Group1 Cache" state, if the current DMA command group is executed and Launch is not enabled, the state jumps to "Group0 Idle / Group1 Cache"; if the current DMA command group is executed and Launch is enabled, the state jumps to "Group0 Idle / Group1 Busy"; In the "Group0 Idle / Group1 Cache" state, if Launch is enabled, the state jumps to "Group0 Idle / Group1 Busy"; In the "Group0 Idle / Group1 Busy" state, if there is no Enable, the state jumps to "Group0 Idle / Group1 Idle", and the execution of this DMA command group is completed; if there is Enable, the state jumps to "Group0 Cache / Group1 Busy"; In the "Group0 Cache / Group1 Busy" state, if the current DMA command group is executed and Launch is not enabled, the state jumps to "Group0 Cache / Group1 Idle"; if the current DMA command group is executed and Launch is enabled, the state jumps to "Group0 Busy / Group1 Idle".

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