A serial communication method and device, a server, an electronic device and a storage medium

Abstract

The application discloses a serial port communication method and device, a server, electronic equipment and a storage medium. The method comprises the following steps: receiving a first serial port signal containing first target data from a processor, and receiving a second serial port signal containing the first target data from a baseboard management controller; comparing whether the first serial port signal and the second serial port signal are consistent; if the first serial port signal and the second serial port signal are consistent, transmitting the first serial port signal or the second serial port signal to an external device through an external serial port; if the first serial port signal and the second serial port signal are inconsistent, adding a first mark to the first serial port signal, adding a second mark to the second serial port signal, and transmitting the first serial port signal with the first mark and the second serial port signal with the second mark to the external device through the external serial port; wherein the first mark is used for marking that the first serial port signal is from the processor, and the second mark is used for marking that the second serial port signal is from the baseboard management controller. The application improves the accuracy and reliability of the server serial port communication.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a serial communication method, apparatus, server, electronic device, and storage medium. Background Technology

[0002] The server industry is currently in a phase of rapid development. During the server system startup process, the serial port can output log information of the bootloader, helping administrators monitor the system startup status and diagnose startup problems. Furthermore, when the server encounters a fault during operation, the UART (Universal Asynchronous Receiver / Transmitter) serial port can also output error information, facilitating troubleshooting and system debugging.

[0003] In related technologies, the processor sends data to the BMC (Baseboard Management Controller) via eSPI (Enhanced Serial Peripheral Interface). The BMC then converts the data into serial port information and sends it to the CPLD (Complex Programmable Logic Device). The CPLD then transmits the serial port information to the external device via an external serial port. It is evident that the server internally uses eSPI and UART format conversion, which may lead to data parsing errors. When the BMC malfunctions, the server's serial communication will be interrupted, and the processor will be unable to establish communication with external devices.

[0004] Therefore, improving the accuracy and reliability of server serial communication is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a serial communication method, device, server, electronic device, and storage medium that improves the accuracy and reliability of server serial communication.

[0006] To achieve the above objectives, this application provides a serial communication method applied to a complex programmable logic device in a server. The server includes a processor, a complex programmable logic device, a baseboard management controller, and an external serial port. The processor is connected to the complex programmable logic device through a first UART interface.

[0007] The method includes:

[0008] The processor receives a first serial port signal containing the first target data, and the baseboard management controller receives a second serial port signal containing the first target data.

[0009] Compare whether the first serial port signal and the second serial port signal are consistent;

[0010] If they match, the first serial port signal or the second serial port signal is sent to the external device through the external serial port.

[0011] If they are inconsistent, a first tag is added to the first serial port signal, a second tag is added to the second serial port signal, and the first serial port signal with the first tag and the second serial port signal with the second tag are sent to the external device through the external serial port; wherein, the first tag is used to mark that the first serial port signal originates from the processor, and the second tag is used to mark that the second serial port signal originates from the baseboard management controller.

[0012] Prior to receiving a first serial port signal containing the first target data from the processor and a second serial port signal containing the first target data from the baseboard management controller, the process further includes:

[0013] Determine the current serial port mode;

[0014] If the current serial port mode is adaptive mode, then the steps of receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller are executed.

[0015] Determining the current serial port mode includes:

[0016] The current serial port mode is determined by the jumper cap setting;

[0017] If the current serial port mode determined by the jumper cap setting is adaptive mode, then the serial port mode modification command sent by the baseboard management controller is received, and the current serial port mode is re-determined according to the serial port mode modification command.

[0018] If the current serial port mode is adaptive mode, the method further includes:

[0019] Check if the baseboard management controller is functioning properly;

[0020] If so, then the steps of receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller are executed.

[0021] If not, switch to processor mode to receive a first serial port signal containing the first target data from the processor, and send the first serial port signal to the external device through the external serial port.

[0022] The processor is connected to the baseboard management controller via a bus, the baseboard management controller is connected to the complex programmable logic device via a second UART interface, the complex programmable logic device is connected to the external serial port, and the server is connected to external devices via the external serial port.

[0023] After determining the current serial port mode, the process also includes:

[0024] If the current serial port mode is processor mode, then the first serial port signal containing the first target data is received from the processor through the first UART interface, and the first serial port signal is sent to the external device through the external serial port.

[0025] If the current serial port mode is the baseboard management controller mode, then the processor receives a second serial port signal containing the first target data from the baseboard management controller through the second UART interface, and sends the second serial port signal to the external device through the external serial port; wherein, the processor sends a first bus signal containing the first target data to the baseboard management controller through the bus, and the baseboard management controller converts the first bus signal into the second serial port signal and sends it to the complex programmable logic device;

[0026] Accordingly, if the current serial port mode is adaptive mode, then receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller includes:

[0027] The processor receives the first serial port signal from the processor via the first UART interface and receives the second serial port signal from the substrate management controller via the second UART interface; wherein, the processor sends a first bus signal containing the first target data to the substrate management controller via a bus, and the substrate management controller converts the first bus signal into the second serial port signal and sends it to the complex programmable logic device.

[0028] This also includes:

[0029] Receive a third serial port signal containing the second target data sent by the external device through the external serial port;

[0030] The third serial port signal is sent to the baseboard management controller via the second UART interface, so that the baseboard management controller converts the third serial port signal into a second bus signal and sends it to the processor;

[0031] The third serial port signal is sent to the processor through the first UART interface; wherein, the processor selects the second target data to be received from the second bus signal and the third serial port signal according to preset configuration information.

[0032] To achieve the above objectives, this application provides a serial communication device for use in a complex programmable logic device (CPL) in a server. The server includes a processor, a CPL, a baseboard management controller, and an external serial port. The processor is connected to the CPL via a first UART interface.

[0033] The device includes:

[0034] The first receiving module is configured to receive a first serial port signal containing first target data from the processor, and a second serial port signal containing the first target data from the baseboard management controller;

[0035] The comparison module is used to compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, the workflow of the first sending module is started; if they are inconsistent, the workflow of the second sending module is started.

[0036] The first transmitting module is used to transmit the first serial port signal or the second serial port signal to an external device through the external serial port;

[0037] The second transmitting module is used to add a first tag to the first serial port signal, add a second tag to the second serial port signal, and transmit the first serial port signal with the first tag and the second serial port signal with the second tag to the external device through the external serial port; wherein, the first tag is used to mark that the first serial port signal originates from the processor, and the second tag is used to mark that the second serial port signal originates from the baseboard management controller.

[0038] To achieve the above objectives, this application provides a server, including a processor, a complex programmable logic device (CPLD), a baseboard management controller (BMDC), and an external serial port. The processor is connected to the CPLD via a first UART interface, the processor is connected to the BMDC via an eSPI bus, the BMDC is connected to the CPLD via a second UART interface, the CPLD is connected to the external serial port, and the server is connected to external devices via the external serial port.

[0039] The processor is configured to send a first serial port signal containing first target data to the complex programmable logic device and a first bus signal containing the first target data to the baseboard management controller.

[0040] The substrate management controller is used to convert the first bus signal into a second serial port signal and send it to the complex programmable logic device.

[0041] The complex programmable logic device is used to compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, the first serial port signal or the second serial port signal is sent to the external device through the external serial port; if they are inconsistent, a first mark is added to the first serial port signal, a second mark is added to the second serial port signal, and the first serial port signal with the first mark and the second serial port signal with the second mark are sent to the external device through the external serial port; wherein, the first mark is used to mark that the first serial port signal originates from the processor, and the second mark is used to mark that the second serial port signal originates from the baseboard management controller.

[0042] To achieve the above objectives, this application provides an electronic device, comprising:

[0043] Memory, used to store computer programs;

[0044] A processor is used to implement the steps of the serial communication method described above when executing the computer program.

[0045] To achieve the above objectives, this application provides a non-volatile storage medium storing a computer program, which, when executed by a processor, implements the steps of the serial communication method described above.

[0046] The serial communication method provided in this application transmits both the first serial port signal directly output by the processor and the second serial port signal parsed by the baseboard management controller from the processor to a complex programmable logic device (CPL). The CPL ensures the correctness of the data transmitted to the external device through redundancy and comparison mechanisms. Therefore, in this application, the processor can directly transmit the first target data to the CPL via the first serial port signal without requiring eSPI or UART format conversion. Even when the baseboard management controller malfunctions, the processor can still transmit data to the external device, improving the accuracy and reliability of server serial communication. This application also discloses a serial communication device, an electronic device, a non-volatile storage medium, and a computer program product, which can achieve the same technical effects.

[0047] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings are used to provide a further understanding of this disclosure and constitute a part of the specification. They are used together with the following detailed description to explain this disclosure, but do not constitute a limitation of this disclosure. In the drawings:

[0049] Figure 1 This is a structural diagram of a server in related technologies;

[0050] Figure 2 This is a structural diagram of a server according to an exemplary embodiment;

[0051] Figure 3 This is a flowchart illustrating a serial communication method according to an exemplary embodiment;

[0052] Figure 4 A flowchart illustrating another serial communication method according to an exemplary embodiment;

[0053] Figure 5 A flowchart illustrating yet another serial communication method according to an exemplary embodiment;

[0054] Figure 6 This is a flowchart illustrating a CPLD receiving serial port signals according to an exemplary embodiment;

[0055] Figure 7 This is a flowchart illustrating a CPU receiving serial port signals according to an exemplary embodiment;

[0056] Figure 8 This is a structural diagram of a serial communication device according to an exemplary embodiment;

[0057] Figure 9 This is a structural diagram of an electronic device according to an exemplary embodiment. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, in the embodiments of this application, "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0059] In related technologies, server serial port design is as follows: Figure 1 As shown, the CPU (Central Processing Unit) interacts with the motherboard's out-of-band management master control chip (BMC) via the eSPI bus to transmit the system's serial port information. The BMC extracts, parses, and converts the serial port information received from the eSPI into UART bus format for communication with the CPLD. Simultaneously, it converts the serial port information received from the CPLD into eSPI format and transmits it to the CPU. The CPLD connects the BMC's UART serial port to the physical serial port interface. External devices (HOSTs) use cables to connect to the server's UART serial port to achieve UART communication with the CPU.

[0060] As can be seen, in related technologies, the server internally converts between eSPI and UART formats, which may lead to data parsing errors. When the BMC malfunctions, the server's serial communication will be interrupted, and the processor will be unable to establish communication with external devices.

[0061] Therefore, in this application, both the first serial port signal directly output by the processor and the second serial port signal parsed by the baseboard management controller from the processor are transmitted to the complex programmable logic device (CPL). The CPL ensures the correctness of the data transmitted to the external device through redundancy and comparison mechanisms. Thus, in this application, the processor can directly transmit the first target data to the CPL via the first serial port signal without requiring eSPI or UART format conversion. Even when the baseboard management controller malfunctions, the processor can still transmit data to the external device, improving the accuracy and reliability of server serial communication.

[0062] This embodiment provides a server, such as Figure 2 As shown, the system includes a processor, a complex programmable logic device (CPL), a baseboard management controller (BMD), and an external serial port. The processor is connected to the CPL via a first UART interface, and the processor is connected to the BMD via an eSPI bus. The BMD is connected to the CPL via a second UART interface, and the CPL is connected to the external serial port. The server is connected to external devices via the external serial port.

[0063] In practice, the processor connects to the complex programmable logic device (CPLD) via the first UART interface, the processor connects to the baseboard management controller via the eSPI bus, the baseboard management controller connects to the CPLD via the second UART interface, and the CPLD connects to external devices via an external serial port.

[0064] The processor is configured to send a first serial port signal containing first target data to the complex programmable logic device and a first bus signal containing the first target data to the baseboard management controller.

[0065] The substrate management controller is used to convert the first bus signal into a second serial port signal and send it to the complex programmable logic device.

[0066] The complex programmable logic device is used to compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, the first serial port signal or the second serial port signal is sent to the external device through the external serial port; if they are inconsistent, a first mark is added to the first serial port signal, a second mark is added to the second serial port signal, and the first serial port signal with the first mark and the second serial port signal with the second mark are sent to the external device through the external serial port; wherein, the first mark is used to mark that the first serial port signal originates from the processor, and the second mark is used to mark that the second serial port signal originates from the baseboard management controller.

[0067] In practical implementation, when the processor needs to transmit the first target data to an external device, the processor directly sends a first serial port signal containing the first target data to the complex programmable logic device (CPLD) via the first UART interface. Simultaneously, the processor sends a first bus signal containing the first target data to the baseboard management controller (BMC) via the eSPI bus. The BMC parses this signal and converts it into a second serial port signal containing the first target data, which is then sent to the CPLD via the second UART interface. That is, the CPLD simultaneously receives the first serial port signal containing the first target data from the processor and the second serial port signal containing the first target data from the BMC.

[0068] The complex programmable logic device (CPL) compares the first and second serial port signals for consistency. If they match, either signal is selected and sent to the external device via the external serial port. If they do not match, a corresponding log is recorded, and a source tag is added to each of the different serial port signals. Both signals are then sent to the external device simultaneously via the external serial port. Upon receiving the different serial port signals, the external device compares them to determine which communication path has a problem. Additionally, if the CPL detects that one path has no output while the other supports output, it logs the abnormality of the non-output serial port path.

[0069] Furthermore, different serial port modes can be selected, including processor mode, baseboard management controller mode, and adaptive mode. In specific implementations, a jumper cap can be set on the CPLD to initially select which serial port signal to connect to the server's external serial port, i.e., the serial port mode. Besides the jumper cap setting, the CPLD serial port mode can also be implemented by sending I2C commands through the BMC. When the jumper cap is set to adaptive mode, the CPLD can receive I2C (Inter-Integrated Circuit) commands to modify the serial port mode. In processor mode or baseboard management controller mode, it will be forcibly locked in that mode, and other I2C or serial port commands cannot change it. It also supports sending commands to the CPLD via external serial port or I2C to obtain the current serial port mode.

[0070] If the current serial port mode is processor mode, the first serial port signal sent directly from the processor to the complex programmable logic device (CPLD) is used as the serial port signal to be transmitted to the external device. If the current serial port mode is board management controller (BDC) mode, the second serial port signal sent from the BDC to the CPLD is used as the serial port signal to be transmitted to the external device. If the current serial port mode is adaptive mode, the CPLD simultaneously receives the first serial port signal containing the first target data from the processor and the second serial port signal containing the first target data from the BDC. It compares whether the first and second serial port signals are consistent. If they are consistent, either serial port signal is selected and sent to the external device through the external serial port. If they are inconsistent, the corresponding log is recorded, and a source tag is added before each serial port signal. Then, both are sent to the external device through the external serial port.

[0071] The server provided in this application transmits both the first serial port signal directly output by the processor and the second serial port signal parsed by the baseboard management controller from the processor to a complex programmable logic device (CPL). The CPL ensures the correctness of the data transmitted to the external device through redundancy and comparison mechanisms. Therefore, in this application embodiment, the processor can directly transmit the first target data to the CPL via the first serial port signal without requiring eSPI or UART format conversion. Even when the baseboard management controller malfunctions, the processor can still transmit data to the external device, improving the accuracy and reliability of the server's serial communication.

[0072] This application discloses a serial communication method that improves the accuracy and reliability of server serial communication.

[0073] See Figure 3 A flowchart illustrating a serial communication method according to an exemplary embodiment is shown below. Figure 3 As shown, it includes:

[0074] S101: Receive a first serial port signal containing the first target data from the processor, and receive a second serial port signal containing the first target data from the baseboard management controller;

[0075] The processor sends a first bus signal containing the first target data to the baseboard management controller, which converts the first bus signal into a second serial port signal and sends it to the complex programmable logic device.

[0076] The executing entity of this application is the complex programmable logic device (CPLD) in the aforementioned server. In a specific implementation, when the processor needs to transmit first target data to an external device, the processor directly sends a first serial port signal containing the first target data to the CPLD via a first UART interface. Simultaneously, the processor sends a first bus signal containing the first target data to the baseboard management controller (BMS) via the eSPI bus. The BMS parses this signal and converts it into a second serial port signal containing the first target data, which is then sent to the CPLD via a second UART interface. That is, the CPLD simultaneously receives the first serial port signal containing the first target data from the processor and the second serial port signal containing the first target data from the BMS.

[0077] S102: Compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, proceed to S103; if they are inconsistent, proceed to S104.

[0078] S103: Send the first serial port signal or the second serial port signal to an external device through the external serial port;

[0079] S104: Add a first tag to the first serial port signal, add a second tag to the second serial port signal, and send the first serial port signal with the first tag and the second serial port signal with the second tag to the external device through the external serial port; wherein, the first tag is used to mark that the first serial port signal comes from the processor, and the second tag is used to mark that the second serial port signal comes from the baseboard management controller.

[0080] In practice, the complex programmable logic device (CPL) compares the first and second serial port signals. If they match, either signal is selected and sent to the external device via the external serial port. If they don't match, a corresponding log is recorded, and a source tag is added to each signal before both. Then, both signals are sent to the external device simultaneously via the external serial port. The external device receives the different serial port signals and compares them to determine which communication path has a problem. Additionally, if the CPL detects that one path has no output while the other supports output, it logs the abnormality of the non-output serial port path.

[0081] The serial communication method provided in this application transmits both the first serial port signal directly output by the processor and the second serial port signal parsed by the baseboard management controller from the processor to a complex programmable logic device (CPLD). The CPLD ensures the correctness of the data transmitted to the external device through redundancy and comparison mechanisms. Therefore, in this application embodiment, the processor can directly transmit the first target data to the CPLD via the first serial port signal without requiring eSPI or UART format conversion. Even when the baseboard management controller malfunctions, the processor can still transmit data to the external device, improving the accuracy and reliability of server serial communication.

[0082] This application discloses a serial communication method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically:

[0083] See Figure 4 A flowchart illustrating another serial communication method according to an exemplary embodiment, such as... Figure 4 As shown, it includes:

[0084] S201: Determine the current serial port mode;

[0085] In this embodiment, different serial port modes can be selected, including processor mode, baseboard management controller mode, and adaptive mode.

[0086] As a feasible implementation method, determining the current serial port mode includes: determining the current serial port mode according to the jumper cap setting; if the current serial port mode determined according to the jumper cap setting is an adaptive mode, then receiving the serial port mode modification command sent by the baseboard management controller, and re-determining the current serial port mode according to the serial port mode modification command.

[0087] In practical implementation, a jumper cap can be set on the CPLD to initially select which serial port signal to connect to the server's external serial port, i.e., the serial port mode. Besides the jumper cap setting, the CPLD can also achieve serial port mode by sending I2C commands via the BMC. When the jumper cap is set in adaptive mode, the CPLD can receive I2C commands to modify the serial port mode. In processor mode or board management controller mode, it will be forcibly locked in that mode, and other I2C or serial port commands cannot change it. Furthermore, it supports sending commands to the CPLD via external serial port or I2C to obtain the current serial port mode.

[0088] S202: If the current serial port mode is processor mode, then receive the first serial port signal containing the first target data from the processor through the first UART interface, and send the first serial port signal to the external device through the external serial port;

[0089] In practice, if the current serial port mode is processor mode, the first serial port signal sent directly by the processor to the complex programmable logic device will be used as the serial port signal transmitted to the external device.

[0090] S203: If the current serial port mode is the baseboard management controller mode, then the second serial port signal containing the first target data is received from the baseboard management controller through the second UART interface, and the second serial port signal is sent to the external device through the external serial port.

[0091] The processor sends a first bus signal containing the first target data to the baseboard management controller via the eSPI bus. The baseboard management controller converts the first bus signal into a second serial port signal and sends it to the complex programmable logic device.

[0092] In specific implementation, if the current serial port mode is the baseboard management controller mode, the second serial port signal sent by the baseboard management controller to the complex programmable logic device is used as the serial port signal transmitted to the external device.

[0093] S204: If the current serial port mode is adaptive mode, then receive the first serial port signal from the processor through the first UART interface and receive the second serial port signal from the baseboard management controller through the second UART interface; compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, then send the first serial port signal or the second serial port signal to the external device through the external serial port; if they are inconsistent, then add a first tag to the first serial port signal, add a second tag to the second serial port signal, and send the first serial port signal with the first tag and the second serial port signal with the second tag to the external device through the external serial port.

[0094] The processor sends a first bus signal containing the first target data to the baseboard management controller via the eSPI bus. The baseboard management controller converts the first bus signal into a second serial port signal and sends it to the complex programmable logic device.

[0095] As a possible implementation, if the current serial port mode is adaptive mode, the method further includes: detecting whether the baseboard management controller is normal; if yes, then performing the steps of receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller; if no, then switching to processor mode to receive the first serial port signal containing the first target data from the processor and sending the first serial port signal to an external device through an external serial port.

[0096] In specific implementation, the CPLD determines whether the BMC is normal by detecting the WDT (Watchdog Timer) signal of the BMC. If the BMC is not normal, it switches to processor mode. If the BMC is normal, it executes the adaptive mode processing flow normally. The adaptive mode processing flow has been described in detail in the previous embodiment and will not be repeated here.

[0097] Therefore, this embodiment achieves the transmission of the first target data from the processor to the external device by selecting different serial port modes and different serial communication methods.

[0098] This application discloses a serial communication method, specifically:

[0099] See Figure 5 A flowchart illustrating another serial communication method according to an exemplary embodiment is shown below. Figure 5 As shown, it includes:

[0100] S301: Receives a third serial port signal containing the second target data sent by an external device via an external serial port;

[0101] S302: The third serial port signal is sent to the baseboard management controller through the second UART interface, so that the baseboard management controller converts the third serial port signal into a second bus signal and sends it to the processor;

[0102] S303: The third serial port signal is sent to the processor through the first UART interface; wherein, the processor selects the second target data to be received from the second bus signal and the third serial port signal according to the preset configuration information.

[0103] In practical implementation, when an external device needs to transmit second target data to the processor in the server, the external device sends a third serial port signal containing the second target data to the CPLD. The CPLD sends the third serial port signal to the processor through the first UART interface and simultaneously to the BMC through the second UART interface. The BMC parses and converts it into a second bus signal containing the second target data, and then sends it to the processor through the eSPI bus. The processor can select which signal to process based on the preset configuration information of the BIOS (Basic Input / Output System). The preset configuration information can be changed through BIOS Setup settings or BMC commands.

[0104] In a preferred implementation, the CPLD can also distinguish the current serial port mode. If the current serial port mode is processor mode, the CPLD sends the third serial port signal to the processor via the first UART interface, and the processor receives the second target data in the third serial port signal. If the current serial port mode is board management controller mode, the CPLD sends the third serial port signal to the BMC via the second UART interface. The BMC parses and converts it into a second bus signal containing the second target data, and sends it to the processor via the eSPI bus. The processor receives the second target data in the second bus signal. If the current serial port mode is adaptive mode, the CPLD sends the third serial port signal to the processor via the first UART interface and simultaneously to the BMC via the second UART interface. The BMC parses and converts it into a second bus signal containing the second target data, and sends it to the processor via the eSPI bus. The processor selects which signal to process based on preset configuration information.

[0105] The following describes an application embodiment provided by this application, such as... Figure 6 As shown, the process of a CPLD receiving serial port signals includes the following steps:

[0106] Step 1: The CPLD detects the UART mode set by the jumper cap, whether it is BMC UART, CPU UART, or UART adaptive. If it is detected as UART adaptive, it is also necessary to check whether the I2C or UART commands have switched to other modes.

[0107] Step 2: When the serial port mode is BMC UART, the CPLD ignores the output data of the CPU UART. Other implementation schemes are the same as existing technical schemes.

[0108] Step 3: When the serial port mode is CPU UART, the CPLD ignores the output data of the BMC UART, parses the output data of the CPU UART, and forwards it to the external serial port of the UART.

[0109] Step 4: When the serial port mode is UART adaptive, the CPLD supports detecting the BMC's WDT signal. When the WDT signal is abnormal, the CPLD only parses the UART data sent by the CPU. When the BMC WDT is normal, the CPLD simultaneously receives the CPU's UART information from the BMC and compares them. When the comparison results are consistent, the CPLD directly forwards the data to the external serial port interface. When the two data are inconsistent, the CPLD marks the inconsistent data separately and forwards both to the external interface output.

[0110] like Figure 7 As shown, the process of the CPU receiving serial port signals includes the following steps:

[0111] Step 1: When the HOST needs to send data to the CPU, the CPLD only needs to send the serial port data received from the external interface to the CPU UART and BMC UART respectively. The BMC receives the UART data from the CPLD, parses and packages it, and then feeds it back to the CPU via eSPI.

[0112] Step 2: The CPU selects whether to receive serial data from the CPU UART or eSPI via BIOS settings or BMC commands.

[0113] The following describes a serial communication device provided in an embodiment of this application. The serial communication device described below and the serial communication method described above can be referred to each other.

[0114] See Figure 8 A structural diagram of a serial communication device according to an exemplary embodiment is shown, as follows: Figure 8 As shown, it includes:

[0115] The first receiving module 801 is used to receive a first serial port signal containing first target data from the processor and a second serial port signal containing first target data from the baseboard management controller.

[0116] The comparison module 802 is used to compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, the first sending module's workflow is started; if they are inconsistent, the second sending module's workflow is started.

[0117] The first transmitting module 803 is used to transmit a first serial port signal or a second serial port signal to an external device through an external serial port.

[0118] The second transmitting module 804 is used to add a first tag to the first serial port signal, add a second tag to the second serial port signal, and send the first serial port signal with the first tag and the second serial port signal with the second tag to an external device through an external serial port; wherein, the first tag is used to mark that the first serial port signal originates from the processor, and the second tag is used to mark that the second serial port signal originates from the baseboard management controller.

[0119] The serial communication device provided in this application transmits both the first serial port signal directly output by the processor and the second serial port signal parsed by the baseboard management controller from the processor to a complex programmable logic device (CPLD). The CPLD ensures the correctness of the data transmitted to the external device through redundancy and comparison mechanisms. Therefore, in this application embodiment, the processor can directly transmit the first target data to the CPLD via the first serial port signal without requiring eSPI or UART format conversion. Even when the baseboard management controller malfunctions, the processor can still transmit data to the external device, improving the accuracy and reliability of server serial communication.

[0120] Based on the above embodiments, as a preferred embodiment, it further includes:

[0121] The determination module is used to determine the current serial port mode; if the current serial port mode is an adaptive mode, the workflow of the first receiving module 801 is started.

[0122] Based on the above embodiments, as a preferred implementation, the determining module is specifically used to: determine the current serial port mode according to the jumper cap setting; if the current serial port mode determined according to the jumper cap setting is an adaptive mode, then receive the serial port mode modification command sent by the baseboard management controller, and re-determine the current serial port mode according to the serial port mode modification command.

[0123] Based on the above embodiments, as a preferred implementation, if the current serial port mode is an adaptive mode, then it further includes:

[0124] The detection module is used to detect whether the baseboard management controller is normal; if so, the working process of the first receiving module 801 is started; if not, it switches to processor mode to receive a first serial port signal containing the first target data from the processor and sends the first serial port signal to the external device through the external serial port.

[0125] Based on the above embodiments, as a preferred implementation, if the current serial port mode is processor mode, then it further includes:

[0126] The second receiving module is configured to receive a first serial port signal containing the first target data from the processor through the first UART interface, and send the first serial port signal to the external device through the external serial port.

[0127] Based on the above embodiments, as a preferred embodiment, the processor is connected to the baseboard management controller via an eSPI bus, the baseboard management controller is connected to the complex programmable logic device via a second UART interface, the complex programmable logic device is connected to the external serial port, and the server is connected to external devices via the external serial port;

[0128] If the current serial port mode is the baseboard management controller mode, then it also includes:

[0129] The third receiving module is used to receive a second serial port signal containing the first target data from the baseboard management controller through the second UART interface, and send the second serial port signal to the external device through the external serial port; wherein, the processor sends a first bus signal containing the first target data to the baseboard management controller through the eSPI bus, and the baseboard management controller converts the first bus signal into the second serial port signal and sends it to the complex programmable logic device.

[0130] Based on the above embodiments, as a preferred implementation, the first receiving module 801 is specifically used to: receive the first serial port signal from the processor through the first UART interface, and receive the second serial port signal from the baseboard management controller through the second UART interface; wherein, the processor sends a first bus signal containing the first target data to the baseboard management controller through the eSPI bus, and the baseboard management controller converts the first bus signal into the second serial port signal and sends it to the complex programmable logic device.

[0131] Based on the above embodiments, as a preferred embodiment, it further includes:

[0132] The fourth receiving module is used to receive a third serial port signal containing the second target data sent by the external device through the external serial port;

[0133] The third transmitting module is used to transmit the third serial port signal to the baseboard management controller through the second UART interface, so that the baseboard management controller converts the third serial port signal into a second bus signal and sends it to the processor;

[0134] The fourth transmitting module is used to transmit the third serial port signal to the processor through the first UART interface; wherein the processor selects the second target data to be received from the second bus signal and the third serial port signal according to preset configuration information.

[0135] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0136] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiments of this application, the embodiments of this application also provide an electronic device. Figure 9 This is a structural diagram of an electronic device according to an exemplary embodiment, such as... Figure 9 As shown, the electronic device includes:

[0137] Communication interface 1 enables information exchange with other devices, such as network devices;

[0138] Processor 2 is connected to communication interface 1 to enable information exchange with other devices. When running a computer program, it executes the serial communication method provided by one or more of the above-mentioned technical solutions. The computer program is stored in memory 3.

[0139] Of course, in practical applications, the various components in an electronic device are coupled together through bus system 4. It can be understood that bus system 4 is used to achieve communication and connection between these components. In addition to the data bus, bus system 4 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 9 The general will label all buses as Bus System 4.

[0140] The memory 3 in this embodiment is used to store various types of data to support the operation of the electronic device. Examples of such data include any computer program used to operate on the electronic device.

[0141] It is understood that memory 3 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 3 described in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0142] The methods disclosed in the embodiments of this application can be applied to processor 2, or implemented by processor 2. Processor 2 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 2 or by instructions in the form of software. The processor 2 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 2 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 3. Processor 2 reads the program in memory 3 and completes the steps of the aforementioned method in combination with its hardware.

[0143] When processor 2 executes the program, it implements the corresponding processes in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0144] In an exemplary embodiment, this application also provides a non-volatile storage medium storing a computer program that can be executed by a processor 2 to perform the steps described in the aforementioned method.

[0145] In an exemplary embodiment, this application also provides a computer program product, including a computer program executed by a processor 2 to perform the steps described in the aforementioned method.

[0146] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to computer program instructions. The aforementioned computer program can be stored in a non-volatile storage medium, and when executed, it performs the steps of the above method embodiments. Alternatively, if the integrated units of this application are implemented as software functional modules and sold or used as independent products, they can also be stored in a non-volatile storage medium. Based on this understanding, the technical solutions of the embodiments of this application, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a non-volatile storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, network device, etc.) to execute all or part of the methods described in the various embodiments of this application.

[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A serial communication method, characterized in that, A complex programmable logic device for use in a server, the server including a processor, a complex programmable logic device, a baseboard management controller and an external serial port, the processor being connected to the complex programmable logic device via a first UART interface; The method includes: The processor receives a first serial port signal containing the first target data, and the baseboard management controller receives a second serial port signal containing the first target data. Compare whether the first serial port signal and the second serial port signal are consistent; If they match, the first serial port signal or the second serial port signal is sent to the external device through the external serial port. If they are inconsistent, a first tag is added to the first serial port signal, a second tag is added to the second serial port signal, and the first serial port signal with the first tag and the second serial port signal with the second tag are sent to the external device through the external serial port; wherein, the first tag is used to mark that the first serial port signal originates from the processor, and the second tag is used to mark that the second serial port signal originates from the baseboard management controller.

2. The serial communication method according to claim 1, characterized in that, Before receiving a first serial port signal containing the first target data from the processor and a second serial port signal containing the first target data from the baseboard management controller, the method further includes: Determine the current serial port mode; If the current serial port mode is adaptive mode, then the steps of receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller are executed.

3. The serial communication method according to claim 2, characterized in that, Determine the current serial port mode, including: The current serial port mode is determined by the jumper cap setting; If the current serial port mode determined by the jumper cap setting is adaptive mode, then the serial port mode modification command sent by the baseboard management controller is received, and the current serial port mode is re-determined according to the serial port mode modification command.

4. The serial communication method according to claim 2, characterized in that, If the current serial port mode is adaptive mode, the method further includes: Check if the baseboard management controller is functioning properly; If so, then the steps of receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller are executed. If not, switch to processor mode to receive a first serial port signal containing the first target data from the processor, and send the first serial port signal to the external device through the external serial port.

5. The serial communication method according to claim 2, characterized in that, The processor is connected to the baseboard management controller via a bus. The baseboard management controller is connected to the complex programmable logic device via a second UART interface. The complex programmable logic device is connected to the external serial port. The server is connected to external devices via the external serial port. After determining the current serial port mode, the process also includes: If the current serial port mode is processor mode, then the first serial port signal containing the first target data is received from the processor through the first UART interface, and the first serial port signal is sent to the external device through the external serial port. If the current serial port mode is the baseboard management controller mode, then the processor receives a second serial port signal containing the first target data from the baseboard management controller through the second UART interface, and sends the second serial port signal to the external device through the external serial port; wherein, the processor sends a first bus signal containing the first target data to the baseboard management controller through the bus, and the baseboard management controller converts the first bus signal into the second serial port signal and sends it to the complex programmable logic device; Accordingly, if the current serial port mode is adaptive mode, then receiving a first serial port signal containing the first target data from the processor and receiving a second serial port signal containing the first target data from the baseboard management controller includes: The processor receives the first serial port signal from the processor via the first UART interface and receives the second serial port signal from the substrate management controller via the second UART interface; wherein, the processor sends a first bus signal containing the first target data to the substrate management controller via a bus, and the substrate management controller converts the first bus signal into the second serial port signal and sends it to the complex programmable logic device.

6. The serial communication method according to claim 1, characterized in that, Also includes: Receive a third serial port signal containing the second target data sent by the external device through the external serial port; The third serial port signal is sent to the baseboard management controller via the second UART interface, so that the baseboard management controller converts the third serial port signal into a second bus signal and sends it to the processor; The third serial port signal is sent to the processor through the first UART interface; wherein, the processor selects the second target data to be received from the second bus signal and the third serial port signal according to preset configuration information.

7. A serial communication device, characterized in that, A complex programmable logic device for use in a server, the server including a processor, a complex programmable logic device, a baseboard management controller and an external serial port, the processor being connected to the complex programmable logic device via a first UART interface; The device includes: The first receiving module is configured to receive a first serial port signal containing first target data from the processor, and a second serial port signal containing the first target data from the baseboard management controller; The comparison module is used to compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, the workflow of the first sending module is started; if they are inconsistent, the workflow of the second sending module is started. The first transmitting module is used to transmit the first serial port signal or the second serial port signal to an external device through the external serial port; The second transmitting module is used to add a first tag to the first serial port signal, add a second tag to the second serial port signal, and transmit the first serial port signal with the first tag and the second serial port signal with the second tag to the external device through the external serial port; wherein, the first tag is used to mark that the first serial port signal originates from the processor, and the second tag is used to mark that the second serial port signal originates from the baseboard management controller.

8. A server, characterized in that, The system includes a processor, a complex programmable logic device (CPL), a baseboard management controller (BMD), and an external serial port. The processor is connected to the CPL via a first UART interface, and the processor is connected to the BMD via an eSPI bus. The BMD is connected to the CPL via a second UART interface, and the CPL is connected to the external serial port. The server is connected to external devices via the external serial port. The processor is configured to send a first serial port signal containing first target data to the complex programmable logic device and a first bus signal containing the first target data to the baseboard management controller. The substrate management controller is used to convert the first bus signal into a second serial port signal and send it to the complex programmable logic device. The complex programmable logic device is used to compare whether the first serial port signal and the second serial port signal are consistent; if they are consistent, the first serial port signal or the second serial port signal is sent to the external device through the external serial port; if they are inconsistent, a first mark is added to the first serial port signal, a second mark is added to the second serial port signal, and the first serial port signal with the first mark and the second serial port signal with the second mark are sent to the external device through the external serial port; wherein, the first mark is used to mark that the first serial port signal originates from the processor, and the second mark is used to mark that the second serial port signal originates from the baseboard management controller.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the serial communication method as described in any one of claims 1 to 6 when executing the computer program.

10. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores a computer program, which, when executed, implements the steps of the serial communication method as described in any one of claims 1 to 6.

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