A digital circuit, chip and method for convolution operation

Abstract

The present application discloses a digital circuit, method and chip for convolution operation, which relates to the field of data processing technology, a selector, the number of which is the same as the length of a data sequence, the first input ends of all selectors receive the data of the data sequence in sequence, and the second input ends of the corresponding selectors receive the bit values ​​of the first parameter sequence, and the first parameter sequence is formed by transposing the original parameter sequence; if the bit value of the corresponding bit of the first parameter sequence is 0, the selector outputs 0, and if the bit value of the corresponding bit of the first parameter sequence is 1, the selector outputs the corresponding data of the data sequence; the selector outputs several groups of output data with the same length as the first parameter sequence respectively; each group of output data output by the selector is added to obtain several first sum values; all the first sum values ​​are added to output the second sum value. The present application converts the part of the original convolution operation that needs to be implemented by a multiplier into an adder implementation, effectively reducing the cost required for circuit implementation.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a digital circuit, chip and method for convolution operation. Background Art

[0002] Convolution is an important signal processing method, which is widely used in image processing, speech recognition, natural language processing and other fields. It can play different roles according to different application scenarios, such as feature extraction, dimensionality reduction, denoising, image enhancement, etc. As a basic signal processing method, convolution has many different variants and applications. In digital signal processing, discrete convolution is usually used, such as feature extraction and image enhancement in digital image processing. In digital circuit design, convolution is also widely used, such as filtering data and processing images through convolution.

[0003] The following formula 1 is the basic formula for discrete convolution:

[0004] Formula 1

[0005] From the formula, this calculation process involves a large number of multiplication and addition operations. However, in digital circuit design, multipliers have greater delay, power consumption, and area than adders, so the cost of implementing convolution is relatively high. In the current digital circuit implementation, the calculation structure of the convolution sum is as follows: Figure 1 As shown, a large number of multipliers are used in its implementation process, which will consume a lot of resources. Summary of the invention

[0006] In view of the shortcomings of the prior art, the present application proposes a digital circuit implementation method and circuit for convolution operation, which optimizes the original multiplier structure to reduce the cost required for circuit implementation.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] A digital circuit implementation method for convolution operation, comprising:

[0009] An original parameter sequence is received, and an original parameter sequence G(0) to G(n) of the convolution operation is transposed to generate a first parameter sequence, where the length of the first parameter sequence is the bit width of each parameter of the original parameter sequence;

[0010] receiving a data sequence, and inputting data f(0) to f(n) of the data sequence into first input terminals of a plurality of selectors respectively;

[0011] Input the bit values ​​from the 0th bit to the nth bit of the first parameter sequence into the second input terminal of the corresponding selector;

[0012] The selector determines the bit value of the corresponding bit of the first parameter sequence. If the bit value of the corresponding bit is 0, the selector outputs 0. If the bit value of the corresponding bit is 1, the selector outputs the corresponding data of the data sequence. All the selectors output a plurality of groups of output data having the same length as the first parameter sequence according to the length of the first parameter sequence.

[0013] Each group of output data of the selector is added by a first adding circuit to obtain a plurality of first sum values;

[0014] All the first sum values ​​are added together by a second adding circuit to obtain a second sum value.

[0015] The present application further proposes a digital circuit for convolution operation, comprising:

[0016] The number of selectors is the same as the length of the data sequence. The first input ends of all the selectors receive the data f(0) to f(n) of the data sequence in sequence, and the second input ends of the corresponding selectors receive the bit values ​​of the 0th to nth bits of the first parameter sequence, where the first parameter sequence is formed by transposing the original parameter sequence G(0) to G(n). If the bit value of the corresponding bit of the first parameter sequence is 0, the selector outputs 0. If the bit value of the corresponding bit of the first parameter sequence is 1, the selector outputs the corresponding data of the data sequence. The length of the first parameter sequence is the bit width of each parameter of the original parameter sequence. All the selectors output a number of groups of output data having the same length as the first parameter sequence according to the length of the first parameter sequence.

[0017] A first adding circuit adds each group of output data output by the selector to obtain a plurality of first sum values;

[0018] The second adding circuit adds all the first sum values ​​and outputs a second sum value.

[0019] The present application further proposes a chip, which includes the digital circuit for the above-mentioned convolution operation.

[0020] The digital circuit implementation method and circuit of convolution and operation proposed in the present application reorganize the parameter sequence of convolution and appropriately rewrite the formula for implementing the convolution operation according to the principle of the reorganized parameter sequence, optimize the original multiplication operation to an addition operation to implement it, and then propose a digital circuit structure to optimize the original multiplier to an adder to reduce the cost of circuit implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0022] Figure 1 It is a discrete convolution circuit of the prior art;

[0023] Figure 2 It is a flow chart of the digital circuit implementation method of convolution operation;

[0024] Figure 3 It is a circuit diagram of a digital circuit for calculating a first sum value of a convolution operation in an embodiment disclosed in the present application;

[0025] Figure 4 It is a circuit diagram of calculating the second sum value of a digital circuit for convolution operation according to an embodiment disclosed in the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings.

[0027] The terms "first", "second", etc. in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or positional relationship. It should be understood that the terms used in this way are interchangeable under appropriate circumstances. This is merely a way of distinguishing objects with the same properties in the embodiments of this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, so that a process, method, circuit, product or device that includes a series of units is not necessarily limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, circuits, products or devices.

[0028] The present application discloses a digital circuit implementation method for convolution operation, which reduces the cost required for circuit implementation by optimizing the structure.

[0029] A method for implementing convolution operations, refer to Figure 2 , including the following methods:

[0030] (I) Receive the original parameter sequence G(x) and the data sequence f(x), transpose the original parameter sequence G(x) of the convolution operation to generate the first parameter sequence g(X), the length of the first parameter sequence is the bit width of each parameter of G(x); the first parameter sequence g(X) includes data g(0)~g(N), and the variable X=0,1,2,3...N. The variable x of the original parameter sequence G(x) is 0,1,2,3...n, and the original parameter sequence G(x) contains n+1 data points from G(0) to G(n).

[0031] The method of transposing the original parameter sequence G(x) of the convolution operation to generate the first parameter sequence includes: generating the first parameter sequence by recombining the bit values ​​of the same binary bits of each parameter of the original parameter sequence G(x) of the convolution operation.

[0032] Here the recombination of the sequence g(X) is performed as follows:

[0033] g(X) = {G(0)[X],G(1)[X],...,G(n)[X]}.

[0034] Specifically, each parameter is composed of the first parameter sequence from the lowest bit to the highest bit, and the number of binary digits of the parameters of the combined original parameter sequence is the length of the first parameter sequence g(X), and the length of the original parameter sequence is the binary bit width of the parameters of the first parameter sequence g(X). For example, G(0)~G(5) is a set of sequences with a bit width of 4 and a length of 6. The lowest bit constitutes g(0), and the highest bit constitutes g(4). The bit width of g(0) and g(4) is 6.

[0035] In the circuit implementation process, Formula 2 is derived from Formula 1, and after reorganization, Formula 3 is obtained.

[0036] Formula 2

[0037] When performing sequence reorganization, the data with the same bits in each original sequence, that is, G(nx)[X] in the formula, are reorganized to obtain a new parameter sequence g(N), so the formula here can be re-expressed as Formula 3:

[0038] Formula 3

[0039] It should be noted that f(x) in Formula 2 and f(m) in Formula 1 have similar meanings. Since x in Formula 2 is 0-n, a transformation description is made.

[0040] As for how to implement the application of formula 3, please refer to the following (II) digital circuit implementation method. Figure 2-Figure 4 .

[0041] (ii) receiving a data sequence, and inputting data f(0) to f(n) of the data sequence into first input terminals of a plurality of selectors respectively;

[0042] The bit value of the [x]th bit of the first parameter sequence g(X) is input into the second input end of the corresponding selector, that is, the input is f(0) to f(n), and the corresponding input is g(X)[0] to g(X)[x].

[0043] The selector determines the bit value of the [x]th bit of g(X). If the bit value of the [x]th bit is 0, the selector outputs 0. If the bit value of the [x]th bit is 1, the selector outputs f(x). All selectors output a number of groups of output data with the same length as the first parameter sequence g(X) according to the length of the first parameter sequence g(X). That is, the first parameter sequence g(X) includes g(0) to g(N). The data f(0) to f(n) are respectively calculated by g(0) to g(N) to obtain a number of first sum values. The number of the first sum values ​​is the same as the length of the first parameter sequence.

[0044] Each group of output data of the selector is added by a first adding circuit to obtain a plurality of first sum values;

[0045] All the first sum values ​​are added together by a second adding circuit to obtain a second sum value.

[0046] The method of inputting the bit values ​​of the 0th to nth bits of the first parameter sequence into the second input end of the corresponding selector includes: inputting different bit values ​​of the first parameter sequence into the second input end of the corresponding selector through bit shift operation.

[0047] In formula 3, g(X)[x] represents the bit value of the 0th to nth bit of the binary of each parameter in the first parameter sequence, that is, the variable x takes 0-n, and its value is only 0 and 1. Therefore, the calculation formula f(x)*g(X)[x] only has two cases in actual calculation: f(x) and 0. Therefore, the multiplication operation in this formula can be ignored, thus turning this step into an accumulation operation. At the same time, the 2 in formula 1 N It is also a special multiplier. If used in digital circuits, the operation of multiplying by an integer power of 2 can be completed through shift operations.

[0048] According to the above disclosed principle description, Formula 1 can be converted into a digital circuit implementation of a convolution operation. As for the implementation of the reorganization method, the input sequence, i.e., the original parameter sequence, is transposed and output, and then input into the digital circuit of the convolution operation.

[0049] According to the above method, the present application also discloses a digital circuit for convolution operation, referring to Figure 3 and Figure 4 , the circuit includes:

[0050] The number of selectors is the same as the length of the data sequence, the first input ends of all the selectors receive the data f(0) to f(n) of the data sequence in sequence, and the second input ends of the corresponding selectors receive the bit value of the [x]th bit of the first parameter sequence, where the first parameter sequence is formed by transposing the original parameter sequence; if the bit value of the [x]th bit of the first parameter sequence is 0, the selector outputs 0, and if the bit value of the [x]th bit of the first parameter sequence is 1, the selector outputs f(n); wherein the length of the first parameter sequence is the bit width of each parameter of the original parameter sequence; all the selectors output a number of groups of output data having the same length as the first parameter sequence according to the length of the first parameter sequence;

[0051] A first adding circuit adds each group of output data output by the selector to obtain a plurality of first sum values;

[0052] The second adding circuit adds all the first sum values ​​and outputs a second sum value.

[0053] Furthermore, the digital circuit also includes a shift unit, which is used to shift the data of the first parameter sequence one bit to the left based on the current bit, and input the shifted bit value into the next selector.

[0054] Furthermore, the digital circuit also includes an input unit and a transposition unit, the input unit receives the original parameter sequence G(x), and the transposition unit is used to perform a transposition operation on the original parameter sequence G(x) and output it; wherein the transposition unit is connected to the selector.

[0055] but Figure 3 The circuit structure shown in is a digital circuit implementation of Formula 4.

[0056] Formula 4

[0057] The specific description of the reorganization and convolution operations is further illustrated by Examples 1 to 3.

[0058] Example 1: Assume that there is binary data of a parameter sequence, and the length of the parameter sequence is 6 as follows. The same bits of the original parameter sequence are extracted. For example, the highest bits (bits) of the parameters of the original parameter sequence are: 1, 0, 1, 1, 1, 1. These binary data are recombined to obtain g(5)=101111 in the new sequence. The results of other new sequences are calculated in the same way, as shown in Table 1.

[0059] After obtaining the first parameter sequence g(X), proceed to the next step and use formula 3 for convolution calculation. Assume that the data sequence is f(0)~f(n), n=5, and the length is 6. The data are f(0)~f(5) respectively. Perform operations on them and g(0). According to the values ​​of each bit in g(0), the calculation result should be Sum_5=f(5)+f(4)+f(3)+f(2)+0+f(1). The other data are calculated in the same way. Finally, the first sum sequence is Sum_0~Sum_5. In the shift operation, taking Sum_5 as an example, according to the process in the previous step, the parameter sequence corresponding to Sum_5 is g(0), and each bit in g(0) corresponds to bit6 in the original parameter sequence G(x), that is, multiplied by 2. 5 , which is exactly an integer power of 2. In binary operations, when a data is multiplied by an integer power of 2, the result is exactly the binary number of the data shifted left by the same number of bits as the power.

[0060] Table 1:

[0061]

[0062] Furthermore, the process of converting the original parameter sequence into the first parameter sequence can be more specifically seen from the following Table 2:

[0063] Table 2:

[0064]

[0065] Embodiment 2:

[0066] Assuming that the number of the original parameter sequence G(x) is G(0) to G(3), and the bit width is 5, then after conversion, the process of obtaining the first parameter sequence g(0) to g(4) is as shown in Table 3.

[0067] Table 3:

[0068]

[0069] Through the above method, the matrix of the original parameter sequence is transposed into the first parameter sequence. Assuming that the input sequence is f(0)~f(n), and the variable x of the function f(x) varies from 0 to n, then the product of f(0)~f(n) and G(0)~G(N) is transformed into the following, where Sum_0, Sum_1, Sum_2, Sum_3, and Sum_4 are the first sum values.

[0070] Sum_0 = [f(0)*g(4)[0]+f(1)*g(4)[1]+f(2)*g(4)[2]+f(3)*g[4](3)]*2 4 ;

[0071] Sum_1 = [f(0)*g(3)[0]+f(1)*g(3)[1]+f(2)*g(3)[2]+f(3)*g[3](3)]*2 3 ;

[0072] Sum_2 = [f(0)*g(2)[0]+f(1)*g(2)[1]+f(2)*g(2)[2]+f(3)*g[2](3)]*2 2 ;

[0073] Sum_3 = [f(0)*g(1)[0]+f(1)*g(1)[1]+f(2)*g(1)[2]+f(3)*g[1](3)]*2 1 ;

[0074] Sum_4 = [f(0)*g(0)[0]+f(1)*g(0)[1]+f(2)*g(0)[2]+f(3)*g[0](3)]*2 0 ;

[0075] The final calculation result is the second sum value Sum_out=Sum_0+Sum_1+Sum_2+Sum_3+Sum_4.

[0076] Example 3: Assuming that the number of convolution parameters G(x) is 4 and the bit width is 8, the process of obtaining the new parameter g(X) after conversion is as shown in Table 4:

[0077] Table 4

[0078]

[0079] Through the above method, the matrix of the original parameter sequence is transposed into the first parameter sequence. Assuming that the input sequence is f(0)~f(n), the product of f(0)~f(n) and G(0)~G(N) is converted as follows, where Sum_0~Sum_7 is the first sum.

[0080] Sum_0 = [f(0)*g(7)[0]+f(1)*g(7)[1]+f(2)*g(7)[2]+f(3)*g[7](3)]*2 7 ;

[0081] Sum_1 = [f(0)*g(6)[0]+f(1)*g(6)[1]+f(2)*g(6)[2]+f(3)*g[6](3)]*2 6 ;

[0082] Sum_2 = [f(0)*g(5)[0]+f(1)*g(5)[1]+f(2)*g(5)[2]+f(3)*g[5](3)]*2 5 ;

[0083] Sum_3 = [f(0)*g(4)[0]+f(1)*g(4)[1]+f(2)*g(4)[2]+f(3)*g[4](3)]*2 4 ;

[0084] Sum_4 = [f(0)*g(3)[0]+f(1)*g(3)[1]+f(2)*g(3)[2]+f(3)*g[3](3)]*2 3 ;

[0085] Sum_5 = [f(0)*g(2)[0]+f(1)*g(2)[1]+f(2)*g(2)[2]+f(3)*g[2](3)]*2 2 ;

[0086] Sum_6 = [f(0)*g(1)[0]+f(1)*g(1)[1]+f(2)*g(1)[2]+f(3)*g[1](3)]*2 1 ;

[0087] Sum_7 = [f(0)*g(0)[0]+f(1)*g(0)[1]+f(2)*g(0)[2]+f(3)*g[0](3)]*2 0 ;

[0088] The final calculation result is Sum_out=Sum_0+Sum_1+Sum_2+Sum_3+Sum_4+Sum_5+Sum_6+Sum_7.

[0089] The above is the circuit structure and implementation method proposed in this application. Obviously, the embodiments described herein are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

Claims

1. A digital circuit for convolution operation, characterized in that: include: The number of selectors is the same as the length of the data sequence. The first input ends of all the selectors receive the data f(0) to f(n) of the data sequence in sequence, and the second input ends of the corresponding selectors receive the bit values ​​of the 0th to nth bits of the first parameter sequence, where the first parameter sequence is formed by transposing the original parameter sequence G(0) to G(n). If the bit value of the corresponding bit of the first parameter sequence is 0, the selector outputs 0. If the bit value of the corresponding bit of the first parameter sequence is 1, the selector outputs the corresponding data of the data sequence. The length of the first parameter sequence is the bit width of each parameter of the original parameter sequence. All the selectors output a number of groups of output data having the same length as the first parameter sequence according to the length of the first parameter sequence. A first adding circuit adds each group of output data output by the selector to obtain a plurality of first sum values; The second adding circuit adds all the first sum values ​​and outputs a second sum value.

2. The digital circuit for convolution operation as claimed in claim 1, characterized in that: It also includes a shift unit, which is used to shift the data of the first parameter sequence to the left by one bit based on the current bit, and input the bit value after the shift into the next selector.

3. The digital circuit for convolution operation as claimed in claim 1, characterized in that: It also includes an input unit and a transposition unit, the input unit receives the original parameter sequence, and the transposition unit is used to perform a transposition operation on the original parameter sequence to obtain a first parameter sequence and output it; wherein the transposition unit is connected to the selector.

4. A chip, characterized in that: The chip comprises a digital circuit for convolution operation as described in any one of claims 1-3.

5. A digital circuit implementation method for convolution operation, characterized in that: The following methods are included: An original parameter sequence is received, and an original parameter sequence G(0) to G(n) of the convolution operation is transposed to generate a first parameter sequence, where the length of the first parameter sequence is the bit width of each parameter of the original parameter sequence; receiving a data sequence, and inputting data f(0) to f(n) of the data sequence into first input terminals of a plurality of selectors respectively; Input the bit values ​​from the 0th bit to the nth bit of the first parameter sequence into the second input terminal of the corresponding selector; The selector determines the bit value of the corresponding bit of the first parameter sequence. If the bit value of the corresponding bit is 0, the selector outputs 0. If the bit value of the corresponding bit is 1, the selector outputs the corresponding data of the data sequence. All the selectors output a plurality of groups of output data having the same length as the first parameter sequence according to the length of the first parameter sequence. Each group of output data of the selector is added by a first adding circuit to obtain a plurality of first sum values; All the first sum values ​​are added together by a second adding circuit to obtain a second sum value.

6. The digital circuit implementation method of convolution operation as claimed in claim 5, characterized in that: The method of transposing an original parameter sequence of a convolution operation to generate a first parameter sequence includes: generating the first parameter sequence by recombining bit values ​​of the same binary positions of each parameter of the original parameter sequence of the convolution operation.

7. The digital circuit implementation method of convolution operation as claimed in claim 5, characterized in that: The method of inputting the bit values ​​of the 0th to the nth bit of the first parameter sequence into the second input terminal of the corresponding selector comprises: Different bit values ​​of the first parameter sequence are input into the second input terminal of the corresponding selector through bit shift operation.

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