On-chip redistribution layer signal integrity analysis method and system based on semi-supervised learning

Abstract

The present invention discloses an on-chip redistribution layer signal integrity analysis method and system based on semi-supervised learning. The method includes: S1, 3D modeling of on-chip redistribution layer channels, and extracting channel scattering parameters through finite element electromagnetic simulation; S2, eye diagram simulation setting; S3, abstracting complex signal integrity problems existing in three-dimensional integrated microsystems, performing fast transient time domain simulation under different conditions, and obtaining a changing eye diagram data set, which includes a labeled data set and an unlabeled data set, and the number of the unlabeled data sets is greater than the number of the labeled data sets; S4, using the labeled changing eye diagram data set obtained in step S3, and performing fully supervised back propagation preliminary training on the main convolutional neural network according to a fully supervised cross entropy loss function to obtain a model that has been preliminarily trained; S5, using the unlabeled changing eye diagram data set obtained in step S3, and training the model that has been preliminarily trained in step S4 according to a semi-supervised cross entropy loss function.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal integrity analysis of chip packaging in three-dimensional integrated microsystems, and in particular relates to an eye diagram data analysis method and system for redistribution layer (RDL) channels in a silicon interposer (Siinterposer) based on semi-supervised learning. Background Art

[0002] With the development of artificial intelligence and big data, the feature sizes of integrated circuits are approaching the physical limits of materials. In the semiconductor and microelectronics fields, three-dimensional integrated microsystems based on advanced packaging have become a viable solution to meet chip performance and size requirements such as higher bandwidth, higher functionality, higher density, and a smaller footprint. In three-dimensional integrated microsystems, the redistribution layer (RDL) within the silicon interposer is used to enable communication between functional units within the integrated microsystem. A good RDL design ensures that the signal maintains its correct time and frequency domain characteristics after transmission, i.e., the prerequisite for signal integrity. Due to the numerous non-ideal factors in actual integrated microsystems, such as impedance mismatch, crosstalk, ground bounce, and power supply noise, accurate and efficient signal integrity analysis of the RDL and tracing the root causes of signal integrity issues are crucial steps in high-speed link design.

[0003] An eye diagram is a graphical tool used to visualize the signal integrity performance of high-speed links by overlaying all possible binary bit streams received by the receiver over a single observation period. The chip design industry generates eye diagram data through post-simulation signal integrity testing. Test engineers analyze distorted eye diagrams to diagnose signal integrity issues in high-speed links. This process often requires engineers with extensive signal integrity testing experience and consumes significant labor costs. Unavoidable human error also complicates and time-consuming design processes. However, currently, there is no accurate and efficient automated signal integrity analysis method for on-chip redistribution layers.

[0004] Image recognition is a fundamental task in computer vision and machine learning. Using semi-supervised learning methods to analyze eye diagrams can accurately and efficiently identify signal integrity issues without human intervention, thereby guiding high-speed link design. Existing technologies have conducted preliminary research on optical communications and board-level channels. These technologies are based on fully supervised learning frameworks, and their model performance is also limited by the size of fully annotated datasets. Furthermore, during the signal integrity testing phase, repeated signal integrity testing of thousands of channels generates a large amount of unlabeled eye diagram data, which is underutilized. Summary of the Invention

[0005] To address the aforementioned issues with existing technologies, the present invention provides a semi-supervised learning-based on-chip redistribution layer (ORDL) signal integrity analysis method and system. This semi-supervised learning framework utilizes a convolutional neural network (CNN) and pseudo-labeling techniques to ensure model accuracy and performance even with small-scale labeled eye diagram datasets and large-scale unlabeled datasets. After the machine learning model is trained, it can automatically perform signal integrity analysis on the ORDL, guiding the design of high-speed links to ensure voltage and timing margins.

[0006] The present invention adopts the following technical solutions:

[0007] A method for analyzing signal integrity of an on-chip redistribution layer based on semi-supervised learning, comprising the following steps:

[0008] S1. 3D modeling of the on-chip redistribution layer channel and extraction of channel scattering parameters through high-precision finite element electromagnetic simulation;

[0009] S2. Eye diagram simulation settings; the targeted on-chip redistribution layer is used for second-generation high-bandwidth memory (HBM2) and GPU signal communication, and the corresponding data transmission rate, parasitic capacitance and other parameters are set.

[0010] S3. Abstract the complex signal integrity issues existing in three-dimensional integrated microsystems, perform fast transient time domain simulations under different conditions, and obtain a changing eye diagram dataset, which includes a small number of labeled datasets and a large number of unlabeled datasets.

[0011] S4. Using the labeled change eye diagram dataset obtained in step S3, perform fully supervised back propagation preliminary training on the main convolutional neural network according to the fully supervised cross entropy loss function to obtain a model that has completed preliminary training;

[0012] S5. Using the unlabeled changing eye diagram dataset obtained in step S3, further train the model preliminarily trained in step S4 using a semi-supervised cross-entropy loss function. After the model is fully trained, verify the accuracy and effectiveness of the model.

[0013] S6. Use the model trained in step S5 for signal integrity analysis to implement signal integrity analysis of the on-chip redistribution layer.

[0014] Preferably, in step 3, abstracting the complex signal integrity issues existing in the three-dimensional integrated microsystem specifically includes:

[0015] First, the signal transmission channel in the on-chip redistribution layer has inherent conductor and dielectric losses, and energy is inevitably attenuated to a certain extent during transmission. If the channel insertion loss exceeds the maximum value specified in the relevant technical specifications, the channel needs to be optimized or compensated.

[0016] Second, because the on-chip redistribution layer transmission channels are not resistor-terminated at the receiving end, signal reflections occur there. Impedance mismatch is also a significant factor affecting channel signal integrity. By adding series resistors at the end of the channel, channel signal mismatch can be reduced. This approach allows us to understand the impact of impedance mismatch on signal integrity.

[0017] Third, due to advancements in chip manufacturing processes, the spacing between transmission channels in the on-chip redistribution layer continues to shrink, making any channel susceptible to crosstalk from adjacent attack channels. Crosstalk is further divided into near-end crosstalk (NEXT) and far-end crosstalk (FEXT):

[0018]

[0019] Both are caused by capacitive and inductive coupling within the channel. Crosstalk can cause overshoot and ringing in the victim channel. For on-chip redistribution layer channels, considering adjacent dual-aggressor channels is sufficient to characterize the crosstalk impact.

[0020] Fourth, 3D integrated microsystems use power distribution networks (PDNs) to power their functional units. However, an imperfectly designed PDN can cause power supply noise (PSN) and power supply jitter (PSIJ) in the channels in the redistribution layer, affecting the channel signal integrity.

[0021] In summary, channel loss can be mitigated by shortening interconnects and reducing the dielectric loss tangent. Impedance matching can be achieved by short-circuiting a resistor equal to the interconnect's characteristic impedance at the receiving end. Channel crosstalk can be reduced by separating adjacent attack channels (i.e., increasing the spacing between channels). To mitigate the effects of jitter, appropriately positioned and numbered decoupling capacitors can be added to the power distribution network.

[0022] The factors affecting signal integrity in the above four three-dimensional integrated microsystems are comprehensively considered, and a changing eye diagram dataset is constructed.

[0023] Preferably, in step 4, the specific method for performing full-supervision preliminary training on the model using the labeled dataset constructed in step 3 is as follows:

[0024] S4.1: Build the main convolutional neural network model based on the VGG network architecture for on-chip redistribution layer signal integrity analysis. Initialize the model weights using the Xavier method.

[0025] S4.2, construct a fully supervised training loss function. Since the method is to perform image recognition on eye patterns, the loss function used in the initial training model is the cross-entropy loss function:

[0026]

[0027] Among them, N is the single training batch size, C is the total number of classification categories, and y ij is the label value of the jth category of the i-th sample, p ij is the predicted probability that the i-th sample belongs to the j-th category.

[0028] S4.3, construct the optimizer Adam; use the optimizer to adjust the model parameters according to the gradient descent method to minimize the loss function.

[0029] S4.4, iteratively train the model using the training set in the mini-batch labeled dataset until the model's performance in the validation set in the mini-batch labeled dataset no longer improves.

[0030] Preferably, in step 5, the specific method of using the unlabeled dataset constructed in step 3 to perform further semi-supervised training on the model that has completed the preliminary training in step 4 is as follows:

[0031] S5.1. Use the preliminarily trained model to pseudo-label the unlabeled dataset. The specific process of pseudo-labeling the dataset is as follows:

[0032]

[0033] Among them, f i (x) is the predicted probability of the completed preliminary model for unlabeled data, through the predicted probability f i (x) Screen high-confidence samples (i.e., greater than the set confidence level) and annotate them with pseudo labels.

[0034] S5.2, construct the loss function for semi-supervised learning training:

[0035]

[0036] Among them, L(·) represents the cross entropy loss function, and α(t) is the coefficient used to balance the two losses.

[0037] S5.3, semi-supervised iterative training of the model is performed using the training set and pseudo-labeled dataset from the mini-batch labeled dataset. During the iterative training of the network, the proportion of pseudo-label loss is gradually increased, which is achieved by changing α(t):

[0038]

[0039] The value of parameter T1 depends on the number of initial training iterations, and the value of T2 depends on the maximum number of iterations. When the model's performance on the validation set of the mini-batch annotated dataset no longer improves, training is terminated and the optimal model parameters are extracted. The accuracy and effectiveness of the model are verified using the test set of the mini-batch annotated dataset.

[0040] The present invention also discloses an on-chip redistribution layer signal integrity analysis system based on semi-supervised learning, which includes the following modules based on the above method:

[0041] Channel scattering parameter extraction module: performs 3D modeling of the on-chip redistribution layer channel and extracts the channel scattering parameters through finite element electromagnetic simulation;

[0042] Setting module: set the eye diagram simulation;

[0043] Eye diagram dataset construction module: This module abstracts the complex signal integrity issues present in three-dimensional integrated microsystems and performs fast transient time-domain simulations under different conditions to obtain varying eye diagram datasets, including both labeled and unlabeled datasets. The number of unlabeled datasets is greater than the number of labeled datasets.

[0044] Fully supervised module: Using the obtained labeled change eye diagram dataset, the main convolutional neural network is preliminarily trained with fully supervised backpropagation according to the fully supervised cross-entropy loss function to obtain a preliminarily trained model;

[0045] Semi-supervised module: Use the obtained unlabeled change eye diagram dataset and the semi-supervised cross entropy loss function to train the preliminarily trained model;

[0046] Signal integrity analysis module: Use the trained model for signal integrity analysis to implement signal integrity analysis of the on-chip redistribution layer.

[0047] Compared with existing signal integrity analysis technologies, the present invention has the following significant advantages:

[0048] The present invention adopts a machine learning model image recognition method. After completing the model training, it can automatically perform accurate and efficient signal integrity analysis of the on-chip redistribution layer without any experience or domain knowledge, and provide guidance for the design of high-speed links to ensure voltage and time margins.

[0049] Compared with previous research conducted in the field of optical communications and at the board level, the present invention has the following significant advantages:

[0050] (1) An advanced convolutional neural network model is used to meet the requirements for higher signal integrity analysis accuracy. (2) Pseudo-labeling technology is used to annotate a large number of unlabeled data sets, making full use of the large amount of eye diagram data generated during signal integrity testing, further improving the accuracy of signal integrity analysis. This invention has wider applicability and higher accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a schematic diagram of the channel model for the redistribution layer of the three-dimensional integrated microsystem targeted by the present invention for high-bandwidth memory (HBM) and GPU signal transmission (Interposer Channel: interposer channel, Si interposer: silicon interposer, Logic die: logic chip, DRAM Die: memory chip; PHY: physical layer chip, TSV: through silicon via, bump: metal bump);

[0052] Figure 2 This is a schematic diagram of the transient time domain simulation circuit of the redistribution layer channel (Memory Controller Tx: memory control transmitter, Memory Controller Tx: memory control receiver, ESD Cparastic: electrostatic discharge parasitic capacitance, C gate : Gate capacitance, C Diffusion : diffusion capacitance);

[0053] Figure 3 Schematic diagram of the main factors affecting signal integrity in the redistribution layer channel of a three-dimensional integrated microsystem, where (a) is a schematic diagram of the inherent transmission loss of the channel, (b) is a schematic diagram of the channel affected by crosstalk, (c) is a schematic diagram of the channel impedance mismatch, and (d) is a schematic diagram of the channel affected by jitter (High frequency attenuation: high frequency attenuation, Crosstalk: crosstalk, Aggressor channel: attack channel, Victim channel: victim channel, Jitter: jitter, R: resistance, L: capacitance, VRM: voltage regulator module, Chip: chip, Interposer: intermediate layer, PCB / PKG: board level / package level, VDD: DC power supply, ESL: equivalent series inductance, ESR: equivalent series resistance, C Decap : Decoupling capacitors, Logic Circuits: logic circuits);

[0054] Figure 4 Schematic diagram of 12 different scenarios corresponding to the constructed distorted eye diagram dataset (H: high-frequency attenuation, C1: single-attack channel crosstalk, C2: double-attack channel crosstalk, I: impedance mismatch, J: jitter);

[0055] Figure 5 This is a schematic diagram of the main neural network model structure used in the present invention (Conv: convolutional layer, Pool: pooling layer, Fc: fully connected layer, Output: output);

[0056] Figure 6 This is a comparison chart of the results of the main neural network used in the present invention and two classic convolutional neural networks (LeNet and AlexNet) (Testing Performance).

[0057] Figure 7 This is a flow chart of the semi-supervised training model;

[0058] Figure 8 This is a graph showing the performance improvement of the model after adding semi-supervised training (Testing Performance: test performance, Performance Improvement: performance improvement, Dataset Type: dataset type);

[0059] Figure 9 This is a flow chart of an automatic analysis method for on-chip redistribution layer signal integrity based on semi-supervised learning in a preferred embodiment of the present invention;

[0060] Figure 10 This is a block diagram of an on-chip redistribution layer signal integrity automatic analysis system based on semi-supervised learning in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0061] The following describes the embodiments of the present invention in conjunction with the accompanying drawings through specific specific implementation cases. Those skilled in the art can intuitively understand other advantages of the present invention from the content described in this specification. The present invention can also be implemented or applied through other different specific implementation methods. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0062] like Figure 9 As shown, this embodiment provides an automatic analysis method for on-chip redistribution layer signal integrity based on semi-supervised learning, and the specific steps are as follows:

[0063] S1, such as Figure 1As shown, 3D modeling of the on-chip redistribution layer channels was performed, and channel scattering parameters were extracted through high-precision finite element electromagnetic simulation. The on-chip redistribution layer for HBM and GPU communication consists of four metal layers (M1-M4). The metal layer interconnect material is set to copper (Copper) and the substrate material is set to silicon dioxide (SiO2). Based on the typical copper-Damascene interposer process, the relative dielectric constant of silicon dioxide at 9GHz is set to 4.1. The interconnect geometry parameters are set according to process limits and the actual routing area.

[0064] S2, eye diagram simulation settings; the on-chip redistribution layer is used for the second-generation high-bandwidth memory (HBM2) and GPU signal communication, and the corresponding data transmission rate, parasitic capacitance and other parameters are set. Figure 2 As shown in FIG, for HBM2, the single-channel signal transmission rate is set to 2 Gbps, and the parasitic capacitance of the transmitter and receiver sections are both set to 0.4 pF.

[0065] S3. We abstracted the complex signal integrity issues present in three-dimensional integrated microsystems and conducted fast transient time-domain simulations under various conditions. This yielded a dataset of distorted eye diagrams (indicates that the eye diagram deviates from its ideal form due to adverse external signal integrity factors). This dataset includes a small number of labeled datasets and a large number of unlabeled datasets. The datasets all contain RGB distorted eye diagram images with an aspect ratio of 300×200.

[0066] Reference Figure 3 ,The specific steps for abstracting the complex signal integrity issues in three-dimensional integrated microsystems are as follows:

[0067] First, the signal transmission channel in the on-chip redistribution layer has inherent conductor and dielectric losses, and energy is inevitably attenuated to a certain extent during transmission. If the channel insertion loss exceeds the maximum value specified in the relevant technical specifications, the channel needs to be optimized or compensated. The insertion loss in the scattering parameter indicates the degree of signal attenuation in the channel. Channels with different insertion loss values ​​can be obtained by varying the interconnect length and the dielectric material loss tangent.

[0068] Second, due to advancements in chip manufacturing processes, the spacing between transmission channels in the on-chip redistribution layer continues to shrink, making any channel susceptible to crosstalk from adjacent attack channels. Crosstalk is divided into near-end crosstalk (NEXT) and far-end crosstalk (FEXT):

[0069]

[0070] Both are caused by capacitive and inductive coupling within the channel. Crosstalk can cause overshoot and ringing in the victim channel. For on-chip redistribution layer channels, considering adjacent dual-aggressor channels is sufficient to characterize the crosstalk impact. Changing channel spacing can enhance or mitigate the crosstalk effect.

[0071] Third, because the on-chip redistribution layer transmission channels are not resistor-terminated at the receiving end, signal reflections can occur there. Impedance mismatch is also a significant factor affecting channel signal integrity. By adding series resistors at the end of the channel, channel signal mismatch can be reduced. This approach allows us to understand the impact of impedance mismatch on signal integrity.

[0072] Fourth, 3D integrated microsystems use a power distribution network (PDN) to power their functional units. However, an imperfectly designed PDN can introduce power supply noise (PSN) and power supply jitter (PSIJ) into the channels within the redistribution layer, impacting channel signal integrity. Jitter can cause delays or advances in the timing of the binary bit stream, leading to timing errors at the receiver. Properly placing and arranging decoupling capacitors on the PDN can mitigate the effects of jitter.

[0073] The factors affecting signal integrity in the above four three-dimensional integrated microsystems are comprehensively considered to construct a distorted eye diagram dataset. The 12 scenarios considered in the dataset are as follows: Figure 4 As shown in the figure, H represents high-frequency channel attenuation, C1 represents crosstalk from a single-attack channel, C2 represents crosstalk from a double-attack channel, I represents channel impedance mismatch, and J represents the presence of jitter in the channel. The constructed dataset not only accounts for the impact of single factors but also considers the impact of multiple factors on channel signal integrity.

[0074] S4, using the labeled distorted eye diagram dataset obtained in step S3, perform a fully supervised back propagation preliminary training on the main convolutional neural network according to the fully supervised cross entropy loss function to obtain a model that has been preliminarily trained. The main convolutional neural network structure is as follows: Figure 5 As shown in the figure, it contains 8 convolutional layers and five pooling layers. After the convolutional pooling layer, there are three fully connected layers. The comparison results of the main convolutional neural network and two classic convolutional neural network models are shown in Figure 6 As shown in the figure, it can be seen that the main convolutional neural network used in the present invention has better performance (Accuracy, Precision, Recall, and F1Score are indicators for evaluating the classification performance of neural networks, and the higher the scores, the better the model performance).

[0075] More specifically, in step 4, the specific method for performing fully supervised preliminary training of the model using the labeled dataset constructed in step 3 is as follows:

[0076] S4.1: Build the main convolutional neural network model based on the VGG network architecture for on-chip redistribution layer signal integrity analysis. Initialize the model weights using the Xavier method.

[0077] S4.2, construct a fully supervised training loss function. Since the method is to perform image recognition on eye patterns, the loss function used in the initial training model is the cross-entropy loss function:

[0078]

[0079] Among them, N is the single training batch size, C is the total number of classification categories, and y ij is the label value of the jth category of the i-th sample, p ij is the predicted probability that the i-th sample belongs to the j-th category.

[0080] S4.3, construct the optimizer Adam; use the optimizer to adjust the model parameters according to the gradient descent method to minimize the loss function.

[0081] S4.4: Iteratively train the model using the training set from the mini-batch annotated dataset until the model's performance on the validation set from the mini-batch annotated dataset no longer improves. Training is terminated using the "early stopping" method. If the model fails to improve performance on the test set after 10 consecutive iterations, training is terminated.

[0082] S5, the unlabeled distorted eye diagram dataset obtained using S3, refer to Figure 7 , the model that has completed the initial training of S4 is further trained according to the semi-supervised cross entropy loss function. After the model completes all the training, the accuracy and effectiveness of the model are verified. The performance improvement of the model after training with the unlabeled dataset is as follows Figure 8 As shown in the figure, it can be found that the model performance is effectively improved by adding unlabeled datasets to training.

[0083] More specifically, in step 5, the specific method for further semi-supervised training of the model preliminarily trained in step 4 using the unlabeled dataset constructed in step 3 is as follows:

[0084] S5.1. Use the preliminarily trained model to pseudo-label the unlabeled dataset. The specific process of pseudo-labeling the dataset is as follows:

[0085]

[0086] Among them, f i (x) is the predicted probability of the completed preliminary model for unlabeled data, through the predicted probability f i(x) Screen high-confidence samples and annotate them with pseudo labels.

[0087] S5.2, construct the loss function for semi-supervised learning training:

[0088]

[0089] Among them, L(·) represents the cross entropy loss function, and α(t) is the coefficient used to balance the two losses.

[0090] S5.3, semi-supervised iterative training of the model is performed using the training set and pseudo-labeled dataset from the mini-batch labeled dataset. During the iterative training of the network, the proportion of pseudo-label loss is gradually increased, which is achieved by changing α(t):

[0091]

[0092] The value of parameter T1 depends on the number of initial training iterations, and the value of T2 depends on the maximum number of iterations. When the model's performance on the validation set of the mini-batch annotated dataset no longer improves, training is terminated and the optimal model parameters are extracted. The accuracy and effectiveness of the model are verified using the test set of the mini-batch annotated dataset.

[0093] S6. Use the model trained in step S5 for signal integrity analysis to implement signal integrity analysis of the on-chip redistribution layer.

[0094] like Figure 10 As shown, this embodiment discloses an automatic analysis system for on-chip redistribution layer signal integrity based on semi-supervised learning, which includes the following modules based on the above method embodiment:

[0095] Channel scattering parameter extraction module: performs 3D modeling of the on-chip redistribution layer channel and extracts the channel scattering parameters through finite element electromagnetic simulation;

[0096] Setting module: set the eye diagram simulation;

[0097] Eye diagram dataset construction module: This module abstracts the complex signal integrity issues in three-dimensional integrated microsystems and performs fast transient time-domain simulations under different conditions to obtain distorted eye diagram datasets, including annotated and unannotated datasets. The number of unannotated datasets is greater than the number of annotated datasets.

[0098] Fully supervised module: Using the obtained labeled distorted eye diagram dataset, the main convolutional neural network is preliminarily trained with fully supervised backpropagation according to the fully supervised cross-entropy loss function to obtain a preliminarily trained model;

[0099] Semi-supervised module: Use the obtained unlabeled distorted eye diagram dataset and train the preliminarily trained model according to the semi-supervised cross-entropy loss function;

[0100] Signal integrity analysis module: Use the trained model for signal integrity analysis to implement signal integrity analysis of the on-chip redistribution layer.

[0101] For other contents of this embodiment, please refer to the above method embodiment.

[0102] The above are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. An on-chip redistribution layer signal integrity analysis method based on semi-supervised learning, characterized in that: The steps include: S1. 3D modeling of the on-chip redistribution layer channel and extraction of channel scattering parameters through finite element electromagnetic simulation; S2, eye diagram simulation settings; S3. Abstract the complex signal integrity issues existing in three-dimensional integrated microsystems and perform fast transient time-domain simulations under different conditions to obtain varying eye diagram datasets, including annotated and unannotated datasets. The number of unannotated datasets is greater than the number of annotated datasets. S4. Using the labeled change eye diagram dataset obtained in step S3, perform fully supervised back propagation preliminary training on the main convolutional neural network according to the fully supervised cross entropy loss function to obtain a model that has completed preliminary training; S5. Using the unlabeled changing eye diagram dataset obtained in step S3, the model preliminarily trained in step S4 is trained according to the semi-supervised cross entropy loss function; S6. Use the model trained in step S5 for signal integrity analysis to implement signal integrity analysis of the on-chip redistribution layer; Step S4 specifically includes: S4.1, referring to the VGG network structure, build the main convolutional neural network model for on-chip redistribution layer signal integrity analysis; use the Xavier method to initialize the weights of the model; S4.2, construct the cross entropy loss function for fully supervised training; the loss function used in the preliminary training model adopts the cross entropy loss function as follows: in, N is the single training batch size, C is the total number of categories for classification, It is i The first sample j The label value of each category, It is i The samples belong to j The probability prediction value of each category; S4.3, construct the optimizer Adam; use the optimizer to adjust the model parameters according to the gradient descent method to minimize the loss function; S4.4, iteratively train the model using the training set in the labeled dataset until the model's performance on the validation set in the labeled dataset no longer improves; Step S5 specifically includes: S5.

1. Use the preliminarily trained model to pseudo-label the unlabeled dataset. The specific process of pseudo-labeling the dataset is as follows: in, It is to complete the prediction probability of the preliminary model for unlabeled data, through the prediction probability Screen high-confidence samples and annotate them with pseudo labels; S5.2, construct the loss function for semi-supervised learning training as follows: Where n and n' represent the training batch sizes with labels and pseudo labels, respectively. represents the label value of the sample, represents the probability prediction value, L(·) represents the cross entropy loss function, is the coefficient used to balance the two losses; S5.3, use the training set and pseudo-labeled dataset in the labeled dataset to perform semi-supervised iterative training on the model; during the iterative training process, the proportion of pseudo-label loss gradually increases, specifically by changing To implement: Among them, t represents the number of iterations of the model during training, and the parameter The value of depends on the number of initial training iterations, The value of depends on the maximum number of iterations; when the model performance in the validation set of the labeled dataset no longer improves, training is terminated and the optimal model parameters are extracted.

2. The on-chip redistribution layer signal integrity analysis method according to claim 1, characterized in that: In step S3, a specific abstract method is implemented for the complex signal integrity problem existing in the three-dimensional integrated microsystem, specifically including: Channel loss is mitigated by shortening interconnect lengths and reducing dielectric loss tangent. Impedance matching is achieved by shorting a resistor equal to the interconnect characteristic impedance at the receiving end. Channel crosstalk is reduced by distancing adjacent attack channels. Decoupling capacitors are added to the power distribution network to eliminate jitter effects. The factors affecting signal integrity in three-dimensional integrated microsystems, namely channel loss, impedance mismatch, channel crosstalk, power supply noise and power supply jitter, are comprehensively considered to construct a changing eye diagram dataset.

3. An on-chip redistribution layer signal integrity analysis system based on semi-supervised learning, based on the method according to any one of claims 1-2, characterized in that: Includes the following modules: Channel scattering parameter extraction module: performs 3D modeling of the on-chip redistribution layer channel and extracts the channel scattering parameters through finite element electromagnetic simulation; Setting module: set the eye diagram simulation; Eye diagram dataset construction module: This module abstracts the complex signal integrity issues present in three-dimensional integrated microsystems and performs fast transient time-domain simulations under different conditions to obtain varying eye diagram datasets, including both labeled and unlabeled datasets. The number of unlabeled datasets is greater than the number of labeled datasets. Fully supervised module: Using the obtained labeled change eye diagram dataset, the main convolutional neural network is preliminarily trained with fully supervised backpropagation according to the fully supervised cross-entropy loss function to obtain a preliminarily trained model; Semi-supervised module: Use the obtained unlabeled change eye diagram dataset and the semi-supervised cross entropy loss function to train the preliminarily trained model; Signal integrity analysis module: Use the trained model for signal integrity analysis to implement signal integrity analysis of the on-chip redistribution layer.

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