A fast dynamic electromigration prediction method based on hierarchical behavior model modeling

Abstract

The application discloses a fast dynamic electromigration prediction method based on hierarchical behavior modeling, comprising the following steps: hierarchical parasitic parameter extraction; risk metal segment identification; behavior modeling and conversion; electromigration violation check. The method models the input and output characteristics of a circuit and internal current response, and expresses the same in a Verilog-A form with low complexity. Compared with a traditional method of directly applying a flat parasitic parameter netlist to circuit simulation, the application replaces original circuit modules with generated Verilog-A models, significantly reduces the complexity of a post-layout netlist, accelerates the circuit simulation speed for obtaining current distribution, and realizes fast dynamic electromigration analysis.

Description

Technical Field

[0001] The present invention belongs to the technical field of dynamic electromigration prediction, and in particular relates to a fast dynamic electromigration prediction method based on hierarchical behavioral modeling. Background Art

[0002] Electromigration, a key mechanism of interconnect failure in very large-scale integrated circuits (VLSIs), is the atomic migration process caused by momentum exchange between conductive electrons and diffusing metal atoms at high current densities. As chip technology advances into the sub-10nm FinFET device era, interconnect failures caused by electromigration are expected to become more severe due to the shrinking interconnect geometry and the high temperature environment surrounding the FinFET transistor fins, significantly shortening chip lifespan.

[0003] Electromigration prediction is highly dependent on current density, which is often obtained through dynamic simulation after parasitic parameter extraction. However, since parasitic parameter extraction significantly increases the complexity of the circuit layout netlist, dynamic simulation of large-scale circuits is very time-consuming. The cost of obtaining these current densities is extremely high, making dynamic electromigration analysis of large-scale circuits under multiple input stimuli difficult to implement. Furthermore, current conventional electromigration analysis methods do not yet have an efficient process for obtaining circuit current density. If dynamic electromigration prediction can be achieved quickly with only partial dynamic simulation or without dynamic simulation, the time required for circuit power integrity analysis can be significantly accelerated and product cycle time can be reduced. Summary of the Invention

[0004] To address the shortcomings of the existing technology, the present invention aims to provide a fast dynamic electromigration prediction method based on hierarchical behavioral modeling. This method reduces the complexity of the post-layout netlist through behavioral modeling, accelerates the circuit simulation process, and minimizes the current density estimation error, ultimately achieving a fast electromigration simulation process under different input stimuli. To achieve this goal, the specific technical solutions of this application are as follows:

[0005] The method for rapid dynamic electromigration prediction based on hierarchical behavioral modeling comprises the following steps:

[0006] S1. Hierarchical parasitic parameter extraction: Divide the circuit from top to bottom into a combination of different functional units, perform hierarchical parasitic parameter extraction, and generate a hierarchical post-layout netlist;

[0007] S2. Risky Metal Segment Identification: Based on worst-case electromigration analysis of the entire circuit, all metal segments prone to electromigration violations are screened from the layout of different functional units.

[0008] S3. Behavioral Modeling and Conversion: Using a neural network, we build a behavioral model that reflects the output of each functional unit and the current density flowing through the screened internal metal segments. This model is then converted into a Verilog-A model suitable for circuit simulation.

[0009] S4. Electromigration violation check: Replace the functional units in the hierarchical post-layout netlist with the generated Verilog-A models to reduce the complexity of the original post-layout netlist and enable fast dynamic transistor-level electromigration analysis under different input stimuli.

[0010] Furthermore, in step S1, each functional unit has different input and output characteristics, which are expressed as different Verilog-A models through behavioral modeling; and Cadence's parasitic parameter extraction tool Quantus is used to perform hierarchical parasitic parameter extraction. By writing a text file with modular settings, the parasitic parameter extraction tool can automatically identify these functional unit structures and modularize them to achieve hierarchical parasitic parameter extraction; in the hierarchical parasitic parameter extraction, each circuit unit of the top-level circuit is modeled as a separate unit, and parasitic parameter extraction is performed separately to form a hierarchical post-layout netlist; expressed in a detailed standard parasitic parameter format.

[0011] Furthermore, in step S2, the worst operating state corresponds to the situation where the circuit operates at the maximum power. At the same time, during the screening process, all metal segment lines with an electromigration violation rate exceeding 80% are selected. Cadence Spectre is used to perform a single circuit simulation and Cadence Voltus-Fi is applied to perform electromigration checking. By using a Python program to parse the text file generated by Cadence Voltus-Fi, a file for saving circuit simulation settings can be generated after the operation.

[0012] Furthermore, in step S3, a neural network model is used to perform behavioral modeling on the input and output behavior and internal current response of the circuit. The behavioral modeling specifically includes three models: a two-stage FNN for modeling the input and output relationship of the oscillator, an LSTM model for modeling the input and output relationship of the device, and a parallel combination LSTM model for modeling the internal current response information in the circuit;

[0013] All three models use root mean square error to quantify the loss function and use gradient descent method to optimize model parameters;

[0014] The behavioral model adopts the forward Euler method and uses the differential function ddt() and integral function idt() in the Verilog-A language to transform the forward propagation process of the proposed model structure into an ordinary differential equation and express it in the Verilog-A language. This process is implemented by a Python program.

[0015] Furthermore, regarding the input and output behavior of the model: the input of the LSTM model is the input voltage value at different time steps, and its dimension is (n, x), where n represents the number of input time steps and x represents the dimension of the input, that is, the number of input ports of the circuit; the output dimension of the model is (n, y), where y represents the number of output ports of the circuit.

[0016] For the internal current response of the model: the internal current response of the model is divided into multiple groups. The internal current response of each group is learned by an LSTM model of the same specifications. Specifically, if m internal current responses are divided into t groups, there will be t LSTM models, whose input dimension is still (n, x), and the corresponding output dimension is (n, ) or (n, );

[0017] To generate oscillating output for a constant input signal: a two-stage feedforward neural network model is introduced to realize its behavioral modeling process:

[0018]

[0019] Where ω(t) represents the output frequency of the oscillator, V tume (t) represents the modulation voltage signal input to the oscillator, φ(t) represents the output phase of the oscillator, V osc (t) represents the output voltage of the oscillator. The relationship between the input modulation signal and the output frequency of the oscillator is obtained through periodic steady-state simulation, and the relationship between the input modulation signal and the output oscillation voltage of the oscillator can be obtained through transient simulation.

[0020] Furthermore, in step S4, the Verilog-A models of the different functional units generated in step S3 replace the modules in the hierarchical parasitic parameter netlist generated in step S1, and a simplified DSPF post-layout netlist is formed; circuit simulation under different input stimuli is performed, and the current density of each metal segment in the simulation is saved as a text file through the fstrobe function in Verilog-A. Using the Python program, these current densities are read and compared with the current threshold in the technical file, and finally the corresponding electromigration violation degree is generated.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] 1) The method of the present invention models the circuit's input and output characteristics and internal current response, expressing them in a less complex Verilog-A format. Compared to traditional circuit simulation methods that directly use a flat parasitic netlist, by replacing the original circuit modules with the generated Verilog-A model, the complexity of the post-layout netlist is significantly reduced, the circuit simulation speed used to obtain current distribution is accelerated, and fast dynamic electromigration analysis is achieved.

[0023] 2) This method innovatively incorporates internal current responses into the behavioral model and, based on a top-down design philosophy, utilizes hierarchical parasitic parameter extraction to generate a hierarchical post-layout DSPF netlist. By modeling each functional unit's behavioral model and converting it into a Verilog-A model, the present invention significantly shortens circuit simulation time and enables dynamic electromigration analysis under different input stimuli.

[0024] 3) To address the convergence difficulties and increased training costs often encountered by models with high-dimensional outputs, this method decomposes the response current of the metal segments within the circuit and transforms the corresponding LSTM model with multiple output ports into multiple LSTM models with fewer output ports. This combined model is used to accurately learn the internal current response of the circuit. These combined models share the same input and can be easily combined into a single Verilog-A model. This method reduces the need for training data, enhances the model's convergence, and provides a solid foundation for accurately predicting the internal current response of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a framework diagram of the method of the present invention;

[0026] Figure 2 Flow chart of the method of the present invention;

[0027] Figure 3 This is a structural diagram of the behavioral model of the present invention;

[0028] Figure 4 A structural diagram of a multi-mode voltage-controlled oscillator according to an embodiment of the present invention;

[0029] Figure 5 Schematic diagram of single-modal and multi-modal input stimulus scenarios used in the embodiments of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, a fast dynamic electromigration prediction method based on hierarchical behavioral modeling of the present invention is further described below with reference to the accompanying drawings.

[0031] like Figure 1 and Figure 2 As shown, a fast dynamic electromigration prediction method based on hierarchical behavioral model modeling includes: hierarchical parasitic parameter extraction, risk metal segment identification, behavioral model modeling and transformation, and electromigration violation checking.

[0032] (1) Hierarchical parasitic parameter extraction

[0033] Hierarchical parasitic extraction is based on prior information from top-down designs. In top-down design, a top-level circuit can be divided into multiple functional units, each with different input and output characteristics, which can be expressed as different Verilog-A models through behavioral modeling. This strategy is based on the fact that memory requirements for circuit simulation typically have a superlinear relationship with the number of circuit components. Hierarchical parasitic extraction can transform the simulation of the top level of the circuit into a separate simulation of each functional unit, thereby reducing the time required to obtain training data.

[0034] The method of hierarchical parasitic parameter extraction is supported by a variety of electronic design automation tools. The present invention uses Cadence's parasitic parameter extraction tool Quantus to implement this strategy. By writing a text file with modular settings, the parasitic parameter extraction tool can automatically identify these functional unit structures and modularize them to achieve hierarchical parasitic parameter extraction. Unlike the flat post-layout netlist formed by the usual method, in the hierarchical parasitic parameter extraction, each circuit unit of the top-level circuit is modeled as a separate unit, and parasitic parameter extraction is performed separately to form a hierarchical post-layout netlist. Ultimately, this post-layout netlist is expressed in a detailed standard parasitic parameter format (DSPF).

[0035] (2) Identification of risky metal segments

[0036] Risky metal segment identification is based on hierarchical parasitic parameter extraction. During this stage, circuit simulation and electromigration analysis are performed under the circuit's worst-case operating conditions to identify all metal segments within each functional unit that are susceptible to electromigration violations. This worst-case operating condition corresponds to the circuit's maximum operating power. During the screening process, all metal segments with electromigration violation rates exceeding 80% are selected and converted into current-saving commands for the circuit simulation using a Python program.

[0037] The risky metal segment identification method can quickly screen the number of metal segments that need to be considered in the DSPF netlist, thereby significantly reducing the number of current responses learned in behavioral modeling, reducing the difficulty of model training and improving modeling accuracy. The present invention uses Cadence Spectre for a single circuit simulation and Cadence Voltus-Fi for electromigration checking. By using a Python program to parse the text file generated by Cadence Voltus-Fi, a file can be generated after the operation to save the circuit simulation settings.

[0038] (3) Behavioral model building and transformation

[0039] Recurrent neural network (RNN) is a classic neural network model that introduces a hidden layer state into the feedforward structure of the model, which can be expressed by formula (5):

[0040] x n =σ(W h x n-1 +W u u n +b u ) (5) Where n represents the number of time steps, u n is the input vector, x n-1 、x n are the hidden layer states of the model at the previous time step and the current time step, σ is the activation function, usually represented by the sigmoid function, and W h 、W u 、b u where represents the weight matrix and bias in the model, respectively. Because recurrent neural networks simultaneously reference the hidden layer state at the previous time step and the input at the current time step, their output at the current time step can take into account the input conditions at all previous time steps. Therefore, this model can effectively capture the memory effects and nonlinear behavior of output waveforms from different circuits.

[0041] The Long Short-Term Memory (LSTM) network is a variant of the RNN. It adds multiple operation gates to the feedforward structure of the model to solve the gradient vanishing and gradient exploding problems in the RNN. Its structure can be expressed by formula (6):

[0042]

[0043] Among them, i n 、f n , and o n Represents the input gate, forget gate and output gate respectively, c n-1 and c nIt represents the state of the model memory unit at the previous time step and the current time step, and W and b represent the weight matrix and bias of the model.

[0044] In behavioral model modeling and transformation, this application uses neural network models such as LSTM to model the input and output behavior and internal current response of the circuit.

[0045] Regarding the model's input and output behavior: The LSTM model's input is the input voltage value at different time steps, with a dimension of (n, x). Here, n represents the number of input time steps, and x represents the input dimension, i.e., the number of input ports in the circuit. The model's output dimension is (n, y), where y represents the number of output ports in the circuit.

[0046] Regarding the internal current response of the model: Due to the large number of internal current responses, a parallel combination model strategy is adopted, that is, the internal current response of the model is divided into multiple groups, and the internal current response of each group is learned by an LSTM model of the same specifications. Specifically, if m internal current responses are divided into t groups, there will be t LSTM models, whose input dimension is still (n, x), and the corresponding output dimension is (n, ) or (n, ). This strategy can avoid the training data requirements and model accuracy issues caused by the model's high output dimension.

[0047] In addition, for some special circuit structures such as oscillators, they produce oscillating outputs for constant input signals. Due to the stability limitations of the model, this cannot be learned by models such as LSTM, which often regard the oscillating output as causing and outputting a local optimal value. Therefore, when learning the input and output behavior of such circuit structures, the present invention introduces a two-stage feedforward neural network (FNN) model to implement its behavioral modeling process:

[0048]

[0049] Where ω(t) represents the output frequency of the oscillator, V tune (t) represents the modulation voltage signal input to the oscillator, φ(t) represents the output phase of the oscillator, V osc (t) represents the output voltage of the oscillator. The relationship between the input modulation signal and the output frequency of the oscillator can be obtained through periodic steady-state (PSS) simulation, and the relationship between the input modulation signal and the output oscillation voltage of the oscillator can be obtained through transient simulation.

[0050] In short, if Figure 3As shown, the behavioral modeling of this application includes three models: a two-stage FNN for modeling the input-output relationship of the oscillator, an LSTM model for modeling the input-output relationship of other devices, and a parallel combination LSTM model for modeling the internal current response information in these circuits. These models all use the root mean square error (RMSE) to quantify the loss function and use gradient descent to optimize the model parameters.

[0051] After training the behavioral model, it accurately reflects the desired functional behavior of the circuit. Furthermore, the present invention employs the forward Euler method, utilizing the differential function ddt() and the integral function idt() in the Verilog-A language, to transform the forward propagation process of the proposed model structure into an ordinary differential equation, which is then expressed in Verilog-A. This process is implemented using a Python program.

[0052] Specifically, the embodiment of the present invention is at t=t n-1 +αh continuous time point, where α is a hyperparameter and h is the time step used in model training. At this continuous time point, the original discrete input, memory cell state and hidden state of LSTM can be expressed as:

[0053]

[0054] The differential operation is implemented by the ddt() function in the Verilog-A function; the value of the hyperparameter α determines the stability of the approximate ordinary differential equation model. When α is close to 1, the numerical stability of the model deteriorates. In the embodiment of the present invention, α is set to 0.05.

[0055] Therefore, after substituting formula (8) into formula (6), the continuous forward propagation process of the LSTM model can be expressed as:

[0056]

[0057] In the Verilog-A model, the first two equations of Equation (9) can be enforced by expressing the right-hand side as the value of the open-loop branch current. Using these equations, the resulting Verilog-A model can determine the values ​​of c and x at each successive time step and be used for circuit simulation.

[0058] (4) Electromigration violation inspection

[0059] In the electromigration violation check, we use the Verilog-A models of different functional units generated in the third step (i.e., the behavioral model modeling and conversion step) to replace the modules in the hierarchical parasitic netlist generated in the first step (i.e., the hierarchical parasitic parameter extraction step), and form a simplified DSPF post-layout netlist. Due to the low complexity, the circuit simulation time of these Verilog-A models is significantly faster than the simulation time of the corresponding transistor-level circuit. At the same time, these Verilog-A models can also reflect the internal current response information of the corresponding circuit. Finally, in the present invention, circuit simulation under different input stimuli is performed, and the current density of each metal segment in the simulation is saved as a text file through the fstrobe function in Verilog-A; using the python program, these current densities are read and compared with the current threshold in the technical file, and finally the corresponding electromigration violation degree is generated.

[0060] Example 1

[0061] This embodiment is implemented in a multi-mode voltage-controlled oscillator (VCO) based on a 40 nm CMOS process.

[0062] like Figure 4 The structure of the multi-mode voltage-controlled oscillator (MVCO) is shown. The top-level VCO circuit can be broken down into the multi-mode VCO core and output buffer. Parasitic parameter extraction using Cadence Quantus generated a hierarchical DSPF parasitic netlist containing approximately 155,000 parasitic resistors and capacitors. Electromigration analysis at maximum power identified 123 and 72 metal segments in the MVO core and output buffer that were susceptible to electromigration violations, respectively. Finally, a text file was generated for circuit simulation.

[0063] To acquire training data, this embodiment uses the Cadence Spectre X circuit simulator to obtain the data required for modeling the two functional units through transient circuit simulation and periodic steady-state simulation. Specifically, for the multi-mode voltage-controlled oscillator core, the training data includes the core output frequency under different input modulation signals, the output oscillation waveform under different input modulation signals, and the internal current response waveform under different input modulations; for the buffer, the training data includes the output waveform under different input signals and the internal current response waveform under different input signals. Furthermore, to enhance the applicability of the behavioral model, the simulated training data covers the range of parameter variations expected for the circuit.

[0064] and Figure 3As shown, this embodiment uses three models: a two-stage FNN to model the input and output characteristics of the multi-mode voltage-controlled oscillator core, an LSTM model with LSTM layers and fully connected layers to model the input and output characteristics of the buffer, and a parallel combined LSTM model to learn the internal current responses of the two devices. The internal current responses of the multi-mode voltage-controlled oscillator and the buffer are both split into six parts.

[0065] In the benchmark setting, this embodiment uses the peak, average, and root mean square current density on each metal segment and the number of electromigration violations as evaluation indicators of the method.

[0066] In the baseline setting, this embodiment selected the most advanced circuit simulator Cadence Spectre X as the reference baseline. It contains five preset simulation modes, among which the CX mode represents the simulator with the highest simulation accuracy, the VX mode represents the simulator with the highest simulation performance, and the MX mode represents the simulator with a balanced accuracy and performance schedule. In addition, this embodiment also uses Spectre X's iterated simulation method as another baseline. In this mode, the circuit simulator first uses a simplified RC network to calculate the voltage and current waveforms of each device port, and then evaluates the electromigration violations of each RC network based on the above waveforms. In summary, in this embodiment, there are three simulation modes: CX, MX, and VX, as well as two methods: direct and iterated, as baseline standards.

[0067] like Figure 5 As shown, in the experimental setup, this embodiment uses two different input excitation conditions: multi-mode and single-mode. In multi-mode, the operating mode and input voltage of the multi-mode voltage-controlled oscillator change simultaneously, making the corresponding circuit simulation more difficult. In single-mode, the operating mode of the multi-mode voltage-controlled oscillator does not change, making the corresponding circuit simulation less difficult.

[0068] Table 1 shows the comparison results of current density estimation and running time between the embodiment of the present invention and the baseline. It can be seen that the method proposed in the present invention can achieve accurate current density estimation based on a simulation time acceleration ratio of 6.17 times to 38.02 times.

[0069] Table 1 Comparison of peak, average and RMS current density errors and operating time in different modes:

[0070]

[0071] Table 2 compares the electromigration violations reported by the embodiment of the present invention with those reported by the baseline. The accuracy is defined as the ratio of correctly predicted electromigration violations to the number of reported violations. The number in parentheses within the reported violations indicates the amount of overlap between the reported electromigration violations and those in the baseline. The results show that the violating metal segments reported by the embodiment highly overlap with the baseline. Furthermore, the difference between the current density and the threshold for both ignored and misjudged metal segments is within 10% of the threshold, demonstrating the accuracy of the present method in current density estimation.

[0072] Table 2 Electromigration violations reported under different methods and cases:

[0073]

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fast dynamic electromigration prediction method based on hierarchical behavioral modeling, characterized in that: The following steps are involved: S1. Hierarchical parasitic parameter extraction: Divide the circuit from top to bottom into a combination of different functional units, perform hierarchical parasitic parameter extraction, and generate a hierarchical post-layout netlist; S2. Risky Metal Segment Identification: Based on worst-case electromigration analysis of the entire circuit, all metal segments prone to electromigration violations are screened from the layout of different functional units. S3. Behavioral Modeling and Conversion: Using a neural network, we build a behavioral model that reflects the output of each functional unit and the current density flowing through the screened internal metal segments. This model is then converted into a Verilog-A model suitable for circuit simulation. S4. Electromigration violation check: Replace the functional units in the hierarchical post-layout netlist with the generated Verilog-A models to reduce the complexity of the original post-layout netlist and enable fast dynamic transistor-level electromigration analysis under different input stimuli.

2. The fast dynamic electromigration prediction method based on hierarchical behavioral modeling according to claim 1, characterized in that: In step S1, each functional unit has different input and output characteristics, which are expressed as different Verilog-A models through behavioral modeling; and hierarchical parasitic parameter extraction is performed using Cadence's parasitic parameter extraction tool Quantus. By writing a text file with modular settings, the parasitic parameter extraction tool can automatically identify these functional unit structures and modularize them to achieve hierarchical parasitic parameter extraction; in hierarchical parasitic parameter extraction, each circuit unit of the top-level circuit is modeled as a separate unit, and parasitic parameter extraction is performed separately to form a hierarchical post-layout netlist; expressed in a detailed standard parasitic parameter format.

3. The fast dynamic electromigration prediction method based on hierarchical behavioral modeling according to claim 1, characterized in that: In step S2, the worst operating state corresponds to the situation where the circuit operates at the maximum power. At the same time, during the screening process, all metal segment lines with electromigration violation rates exceeding 80% are selected. Cadence Spectre is used to perform a single circuit simulation and Cadence Voltus-Fi is applied to perform electromigration checking. The text file generated by Cadence Voltus-Fi is parsed by using a Python program, and a file for saving circuit simulation settings can be generated after the operation.

4. The fast dynamic electromigration prediction method based on hierarchical behavioral modeling according to claim 1, characterized in that: In step S3, a neural network model is used to perform behavioral modeling on the input and output behavior and internal current response of the circuit. The behavioral modeling specifically includes three models: a two-stage FNN for modeling the input and output relationship of the oscillator, an LSTM model for modeling the input and output relationship of the device, and a parallel combination LSTM model for modeling the internal current response information in the circuit; All three models use root mean square error to quantify the loss function and use gradient descent method to optimize model parameters; The behavioral model adopts the forward Euler method and uses the differential function ddt() and integral function idt() in the Verilog-A language to transform the forward propagation process of the proposed model structure into an ordinary differential equation and express it in the Verilog-A language. This process is implemented by a Python program.

5. The fast dynamic electromigration prediction method based on hierarchical behavioral modeling according to claim 4, characterized in that: Regarding the input and output behavior of the model: The input of the LSTM model is the input voltage value at different time steps, and its dimension is (n, x), where n represents the number of input time steps and x represents the input dimension, that is, the number of input ports of the circuit; the output dimension of the model is (n, y), where y represents the number of output ports of the circuit; For the internal current response of the model: the internal current response of the model is divided into multiple groups. The internal current response of each group is learned by an LSTM model of the same specifications. Specifically, if m internal current responses are divided into t groups, there will be t LSTM models, whose input dimension is still (n, x), and the corresponding output dimension is or To generate oscillating output for a constant input signal: a two-stage feedforward neural network model is introduced to realize its behavioral modeling process: Where ω(t) represents the output frequency of the oscillator, V tune (t) represents the modulation voltage signal input to the oscillator, Ф(t) represents the output phase of the oscillator, V osc (t) represents the output voltage of the oscillator. The relationship between the input modulation signal and the output frequency of the oscillator is obtained through periodic steady-state simulation, and the relationship between the input modulation signal and the output oscillation voltage of the oscillator can be obtained through transient simulation.

6. The fast dynamic electromigration prediction method based on hierarchical behavioral modeling according to claim 1, characterized in that: In step S4, the Verilog-A models of the different functional units generated in step S3 replace the modules in the hierarchical parasitic parameter netlist generated in step S1, and a simplified DSPF post-layout netlist is formed; circuit simulation under different input stimuli is performed, and the current density of each metal segment in the simulation is saved as a text file through the fstrobe function in Verilog-A. Using a python program, these current densities are read and compared with the current thresholds in the technical file, and finally the corresponding electromigration violation degree is generated.

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