A storage array device, a data storage device and a data storage method

Abstract

The present invention relates to the field of data storage technology, and in particular to a storage array device, a data storage device and a data storage method, wherein the storage array device comprises a plurality of control sub-lines, a plurality of storage cells, a plurality of data transmission bit lines and a data reading module; wherein the plurality of storage cells are distributed along a first direction, and the first port of each storage cell is independently connected to a control sub-line, the plurality of data transmission bit lines extend along a second direction perpendicular to the distribution direction of the storage cells, and any one of the data transmission bit lines is connected to at least the second port or the third port of a storage cell, and forms the main structure of the storage array with the storage cells, and the data reading module comprises a plurality of groups of data reading structures, and each group of data reading structures is evenly connected to a plurality of data transmission bit lines. The present invention effectively improves the layout density and storage capacity of the storage cells, optimizes the data storage and reading efficiency, and reduces power consumption and cost.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a storage array device, a data storage equipment and a data storage method. Background Art

[0002] With the rapid development of information technology, read-only memory (ROM), as a core component of non-volatile memory, plays a vital role in various electronic devices. Traditional ROM array design usually arranges storage cells in a two-dimensional grid, determines the location of each storage point by the intersection of rows and columns, and stores the corresponding binary data (0 or 1). Although this design is simple and intuitive, its large area occupation and high cost gradually become prominent when faced with high-capacity and high-density storage requirements.

[0003] Especially driven by modern integrated circuit manufacturing processes and system-on-chip (SoC) technology, semiconductor memory is no longer limited to independent memory chip forms, but is increasingly embedded in complex systems, becoming a key factor in system performance, cost and reliability. In order to reduce the overall system cost, improve performance and enhance reliability, designers urgently need a ROM storage array device that can efficiently utilize chip area.

[0004] However, traditional ROM arrays have many limitations in improving storage density. On the one hand, the fixed layout and connection method of the storage cells limit the compactness of the storage array; on the other hand, the complexity and efficiency of the data reading mechanism also restrict the overall performance of the storage array. Therefore, how to design a new ROM storage array device that can both improve storage density and optimize reading efficiency has become a hot topic and difficulty in current research. Summary of the invention

[0005] In view of the problems existing in the above background technology, the present invention proposes an innovative storage array device, data storage device and data storage method thereof, aiming to improve the density and performance of the ROM storage array by optimizing the layout and connection mode of the storage unit and introducing an efficient data reading mechanism. The storage array device includes the following modules:

[0006] Multiple control sub-lines;

[0007] A plurality of storage units, wherein the plurality of storage units are distributed along a first direction, and a first port of each storage unit is independently connected to a control sub-line;

[0008] A plurality of data transmission bit lines, wherein the plurality of data transmission bit lines extend along a second direction perpendicular to the distribution direction of the memory cells, and any one of the data transmission bit lines is connected to at least the second port or the third port of a memory cell, and forms a main structure of a memory array with the memory cell;

[0009] And a data reading module, the data reading module includes a plurality of groups of data reading structures, each group of data reading structures is evenly connected to a plurality of data transmission bit lines.

[0010] In one embodiment of the present invention, the storage unit is a MOS transistor, the gate of any MOS transistor is independently connected to a control sub-line, and the source and drain thereof are respectively connected to one of the data transmission bit lines.

[0011] In one embodiment of the present invention, the number of storage units is set as follows: the number of bits of binary data to be stored is defined as n, and n is an integer between 2 and 4. .

[0012] In one embodiment of the present invention, the number of data transmission bit lines is set as follows:

[0013] The number of bits required to store data encoded into binary data is defined as n, and n is an integer between 2 and 4;

[0014] When the number of bits required to store data encoded into binary data is n=2, the number of data transmission bit lines is ;

[0015] When the number of bits n required to store data encoded into binary data is ≥ 3, the number of data transmission bit lines .

[0016] In one embodiment of the present invention, the condition for setting the number of the data reading structures includes: the number of the data reading structures is equal to the number of bits required to store data encoded into binary data.

[0017] In one embodiment of the present invention, each data reading structure includes at least one signal amplifier and conductive lines matching the number of data transmission bit lines, wherein the conductive lines are grounded or precharged to a high level, and the conductive lines precharged to a high level are connected to the signal amplifier.

[0018] In one embodiment of the present invention, the setting conditions for the conductive line to be grounded or precharged to a high level include:

[0019] The number of bits required to store data encoded into binary data is defined as n, and n is an integer between 2 and 4;

[0020] When the number of bits n of binary data to be stored is ≥3, the data reading structure also includes a logic processing module. For the data transmission bit lines distributed in the second direction, the conductive line connected to the first data transmission bit line is grounded, the conductive line connected to the last data transmission bit line is precharged to a high level, and the multiple conductive lines connected to the middle data transmission bit line are precharged to a high level in turn, and the remaining conductive lines are grounded, and two conductive lines precharged to a high level are connected to the logic processing module each time.

[0021] In one embodiment of the present invention, the logic processing module is an AND gate circuit module.

[0022] In one embodiment of the present invention, the setting conditions for the conductive line to be grounded or pre-charged to a high level also include: when the data to be stored is encoded into the number of bits of binary data n=2, for the data transmission bit lines distributed in the second direction, the conductive line connected to the first data transmission bit line is grounded, and the remaining conductive lines are pre-charged to a high level in sequence.

[0023] Based on the same inventive concept, the present invention also provides a data storage device, including a processor and the above-mentioned storage array device.

[0024] The present invention also provides a data storage method, which is used for the above-mentioned data storage device to store data and read data, and the method comprises the following steps:

[0025] S1: converting the data to be stored into binary coded data, and storing the binary coded data in the storage unit;

[0026] S2: When data needs to be read, any storage unit is activated, and all data transmission bit lines are pre-charged to a high level or grounded according to the binary coded data, and a connection relationship between the activated storage unit and the corresponding data transmission bit line is obtained;

[0027] S3: Based on the connection relationship, determine whether the precharged high level of the designated data transmission bit line leaks through the data transmission bit line connected to the current storage unit:

[0028] If yes, it means that the second port or the third port of the current storage unit is connected to the data transmission bit line of different voltage state, and the read data is "0" at this time;

[0029] Otherwise, it means that the second port or the third port of the current storage unit is connected to the data transmission bit line of the same voltage state or is not connected to the data transmission bit line of the pre-charged high level, and the read data is "1";

[0030] S4: Determine whether the data of all storage units have been read:

[0031] If not, return to step S3 to read all storage cells in the storage array one by one;

[0032] If so, get the data of all storage units.

[0033] The above technical solution of the present invention has the following advantages compared with the prior art:

[0034] Improve storage density: By distributing storage cells vertically and data transmission bit lines horizontally, a compact storage array device is formed, which effectively improves the layout density of storage cells, thereby achieving higher storage capacity within the same chip area.

[0035] Optimize reading efficiency: introduce multiple sets of data reading structures, each of which includes a signal amplifier and conductive wires that match the number of data transmission bit lines. Through the strategy of precharging high level or grounding, combined with logic processing modules (such as AND gate circuit modules), the state of the storage unit can be quickly judged, thereby improving the data reading efficiency.

[0036] Improve data encoding and storage methods: According to the number of bits of binary data encoded into the required storage data, flexibly adjust the number of storage units and data transmission bit lines, as well as the configuration of the data reading structure. This flexible encoding and storage method not only meets the data storage needs in different application scenarios, but also improves the accuracy and reliability of data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0038] Figure 1 is a structural schematic diagram of a storage array device provided in Embodiment 1 of the present invention;

[0039] Figure 2 is a schematic diagram of a portion of the structure of a storage array device when the number of bits n of binary data to be stored is 2;

[0040] Figure 3 is with Figure 2 Two sets of data reading structures corresponding to the storage array device in the embodiment, wherein (a) represents a data reading structure for reading a first bit, and (b) represents a data reading structure for reading a second bit;

[0041] Figure 4 is a schematic diagram of a portion of the structure of a storage array device when the number of bits n of binary data to be encoded into the storage data is 3;

[0042] Figure 5 is with Figure 4Three sets of data reading structures corresponding to the storage array device in the embodiment, wherein (a) represents a data reading structure for reading a first bit, (b) represents a data reading structure for reading a second bit, and (c) represents a data reading structure for reading a third bit;

[0043] Figure 6 is a schematic diagram of a portion of the structure of a storage array device when the number of bits n of binary data to be stored is 4;

[0044] Figure 7 is with Figure 6 Four groups of data reading structures corresponding to the storage array device in , wherein (a) represents a data reading structure for reading a first bit, (b) represents a data reading structure for reading a second bit, (c) represents a data reading structure for reading a third bit, and (d) represents a data reading structure for reading a fourth bit;

[0045] Figure 8 This is a flow chart of a data storage method provided in Embodiment 2 of the present invention;

[0046] Explanation of the reference numerals in the specification: 1. control sub-line; 2. storage unit; 3. data transmission bit line; 4. data reading module; 41. data reading structure. DETAILED DESCRIPTION

[0047] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention. Embodiment 1

[0048] Reference Figure 1 As shown, the present invention provides a storage array device, which effectively solves the problems of traditional ROM array in improving storage density and optimizing reading efficiency through innovative storage array devices and data storage methods, and provides new ideas and methods for semiconductor memory design. The storage array device includes the following modules:

[0049] A plurality of control sub-lines 1, used for storing data in the storage unit 2, and activating the storage unit 2 designated to be read when reading data;

[0050] A plurality of storage units 2, wherein the plurality of storage units 2 are distributed along a first direction (ie, a vertical direction), and a first port of each storage unit 2 is independently connected to a control sub-line 1;

[0051] A plurality of data transmission bit lines 3, wherein the plurality of data transmission bit lines 3 extend along a second direction (i.e., a horizontal direction) perpendicular to the distribution direction of the storage cells 2, and any one of the data transmission bit lines 3 is connected to at least the second port or the third port of one storage cell 2, and together with the storage cells 2 forms a main structure of an efficient, stable, and compact storage array;

[0052] and a data reading module 4, wherein the data reading module 4 comprises a plurality of groups of data reading structures 41, each group of data reading structures 41 being evenly connected to a plurality of data transmission bit lines 3;

[0053] The storage unit 2 is a MOS transistor, the gate of any MOS transistor is independently connected to a control sub-line, and the source and drain thereof are respectively connected to one of the data transmission bit lines 3 .

[0054] It can be seen from the above technical solutions that the present invention realizes precise control of the storage unit 2 through the carefully arranged multiple control sub-lines 1. These control sub-lines are like the veins of the nervous system, which accurately transmit instructions to each storage unit 2, ensuring the timeliness and accuracy of data operations. At the same time, the storage unit 2 adopts a longitudinal distribution method, which not only optimizes the space utilization, but also facilitates efficient data access operations. The first port of each storage unit 2 is independently connected to a control sub-line 1. This design ensures the independence and reliability of the control signal and avoids mutual interference between signals.

[0055] In order to further improve the data transmission efficiency, the present invention is also equipped with a plurality of horizontally distributed data transmission bit lines 3. These bit lines cleverly connect the second port or the third port of each storage unit 2 to form a high-density storage array. Through this layout, multiple data channels can be processed simultaneously, greatly improving the bandwidth and speed of data transmission.

[0056] Furthermore, when the number of bits of binary data to be stored is n, and n is an integer between 2 and 4, the number of storage units 2 is , the number of the data reading structure 41 .

[0057] In this embodiment, each data reading structure 41 includes at least one signal amplifier and conductive wires matching the number of the data transmission bit lines 3. During the data reading process, according to the encoding method (such as binary encoding) and the bit number requirement of the stored data, the conductive wires are grounded or precharged to a high level, and the conductive wires precharged to a high level are connected to the signal amplifier, and the precharge state of the conductive wires is intelligently adjusted to achieve accurate detection of the state of the storage unit 2.

[0058] Furthermore, when the number of bits of binary data to be stored is n=2, the number of the data transmission bit lines 3 is , corresponding to the data transmission bit lines 3 distributed in the second direction, the conductive line connected to the first data transmission bit line 3 is grounded, and the remaining conductive lines are precharged to a high level in sequence.

[0059] See also Figure 2 and Figure 3 , when the data to be stored is encoded in binary form and the number of bits is set to 2, the number of data transmission bit lines 3 in the technical solution is optimized to 3, and at the same time, the data reading structure 41 is precisely configured into 2 groups according to the number of data bits to be read. Each group of data reading structures 41 includes 3 conductive lines (marked as A, B, C), and the source and drain of each MOS transistor are connected to one (or the same) of the three conductive lines. In particular, adjacent transistors present the characteristics of source-drain interconnection, that is, the drain of one transistor is directly connected to the source of the next transistor, and all transistors are active devices of the same type.

[0060] In the data reading mechanism, if both ends of the MOS transistor are connected to the same conductive line (such as AA, BB or CC configuration), the pre-charge voltage on conductive line B will be maintained and will not be leaked. At this time, the reading circuit outputs a logic value of "1" through the built-in signal amplifier M. On the contrary, if the two ends of the transistor are respectively connected to conductive lines with different voltage states (such as AB, BC configuration), the pre-charge voltage on conductive line B will leak through the transistor to other conductive lines (A or C), and the signal amplifier M will output a logic value of "0". If the two ends of the transistor are connected to different conductive lines but the voltages of the two are the same (such as AC configuration), the pre-charge voltage of conductive line B will also be maintained, and the signal amplifier M outputs a logic value of "1".

[0061] Taking MOS transistor T0 as an example, by placing it in Figure 3 In the first data reading structure shown in (a) and the second data reading structure shown in (b), the stored data can be read sequentially. In this configuration, the conductive lines A, B, and C are respectively connected to the data transmission bit lines BL. A BL B BL C Correspondingly. In the first set of read structures, conductive lines A and C are grounded, and conductive line B is precharged to a high level. Since both ends of T0 are connected to the data transmission bit line BL A, so the high level of conductive line B is maintained, and the first bit of data is read as "1". In the second set of reading structures, conductive line A is grounded, conductive line B is also grounded, and conductive line C is precharged to a high level. Since the other end of T0 is not connected to conductive line C or is connected to it but has the same voltage state, the high level of conductive line C is also maintained, and the second bit of data is read as "1". Therefore, the final data reading result of T0 is "11".

[0062] Similarly, the data reading results of MOS transistors T1, T2 and T3 are "01", "00" and "10" respectively. This result shows that the storage array device provided by the present invention can fully cover all possible combinations of two-bit binary data, providing richer and more flexible options for data storage and encoding.

[0063] It is worth mentioning that when the number of bits of binary data to be stored is greater than or equal to 3, the number of data transmission bit lines 3 is In addition, the data reading structure 41 further includes a logic processing module for performing logic operations on the data of the storage unit 2 according to the precharge state and connection relationship of the data transmission bit line 3, thereby further improving the accuracy and efficiency of data reading.

[0064] Specifically corresponding to the data transmission bit lines 3 distributed in the horizontal direction, the conductive line connected to the first data transmission bit line 3 is grounded, the conductive line connected to the last data transmission bit line 3 is precharged to a high level, and multiple conductive lines connected to the middle data transmission bit line 3 are precharged to a high level in turn, and the remaining conductive lines are grounded, and two conductive lines precharged to a high level are connected to the logic processing module each time.

[0065] Preferably, the logic processing module is an AND gate circuit module. On the one hand, when two conductive wires precharged to a high level are read by the signal amplifier M, the AND gate circuit module will output an accurate logic value only when both signals meet the high level condition. This strict logical judgment ensures the accuracy of data reading and avoids errors caused by signal interference or misreading. On the other hand, even when other conductive wires are interfered with or changed, the AND gate circuit module can still ensure that the two conductive wires remain in a high level state, thereby ensuring the continuity and stability of data reading.

[0066] See also Figure 4 and Figure 5When the data to be stored is encoded in binary form and the number of bits is set to 3, the number of data transmission bit lines in the technical solution is optimized to 5, and at the same time, the data reading structure 41 is precisely configured into 3 groups according to the number of data bits to be read. Each group of data reading structures includes 5 conductive lines (marked as A, B, C, D, E), and these conductive lines are connected to the source and drain of MOS transistors T0~T7, ensuring accurate data reading.

[0067] Taking MOS transistor T0 as an example, by placing it in Figure 5 In the first data reading structure shown in (a), the second data reading structure shown in (b), and the third data reading structure shown in (c), the stored data can be read in sequence. In this configuration, the conductive lines A, B, C, D, and E are respectively connected to the data transmission bit lines BL. A BL B BL C BL D BL E Corresponding connection.

[0068] In the first set of read structures, conductive lines A, C, and D are grounded, while conductive lines B and E are precharged to a high level, and conductive lines B and E are connected through an AND gate circuit module. A , so the high level of conductive lines B and E is maintained, and the first bit of data is read as "1". In the second set of reading structures, conductive lines A, B, and D are grounded, while conductive lines C and E are precharged to a high level, and conductive lines C and E are connected through an AND gate circuit module. Since both ends of T0 are connected to the data transmission bit line BL A , so the high level of conductive lines C and E is also maintained, and the second bit of data is read as "1". In the third group of reading structures, conductive lines A, B, and C are grounded, while conductive lines D and E are precharged to a high level, and conductive lines D and E are connected through an AND gate circuit module. Since both ends of T0 are connected to the data transmission bit line BL A , so the high level of the conductive lines D and E is also maintained, and the third bit of data is read as "1". Therefore, the final data reading result of T0 is "111".

[0069] Similarly, the data reading results of MOS transistors T1, T2, T3, T4, T5, T6 and T7 are "011", "001", "100", "010", "101", "110" and "000" respectively. This result shows that the storage array device provided by the present invention can fully cover all possible combinations of three-bit binary data, providing a more diverse and flexible solution for data storage and encoding.

[0070] See also Figure 6 and Figure 7 When the data to be stored is encoded in binary form and the number of bits is set to 4, the number of data transmission bit lines in the technical solution is optimized to 6, and at the same time, the data reading structure 41 is precisely configured into 4 groups according to the number of data bits to be read. Each group of data reading structures 41 includes 6 conductive lines (marked as A, B, C, D, E, F), and the source and drain of each MOS transistor are connected to one (or the same) of the 6 conductive lines.

[0071] Taking MOS transistor T0 as an example, by placing it in Figure 7 In the first data reading structure shown in (a), the second data reading structure shown in (b), the third data reading structure shown in (c), and the fourth data reading structure shown in (d), the stored data can be read in sequence. In this configuration, the conductive lines A, B, C, D, E, and F are respectively connected to the data transmission bit lines BL. A BL B BL C BL D BL E BL F Corresponding.

[0072] In the first set of read structures, conductive lines A, C, D, and E are grounded, while conductive lines B and F are precharged to a high level, and conductive lines B and F are connected through an AND gate circuit module. Since both ends of T0 are connected to the data transmission bit line BL A , so the high level of conductive lines B and F is maintained, and the first bit of data is read as "1". In the second set of reading structures, conductive lines A, B, D, and E are grounded, while conductive lines C and F are precharged to a high level, and conductive lines C and F are connected through an AND gate circuit module. Since both ends of T0 are connected to the data transmission bit line BL A , so the high level of conductive lines C and F is also maintained, and the second bit of data is read as "1". In the third group of reading structures, conductive lines A, B, C, and E are grounded, while conductive lines D and F are precharged to a high level, and conductive lines D and F are connected through an AND gate circuit module. Since both ends of T0 are connected to the data transmission bit line BL A , so the high level of conductive lines D and F is also maintained, and the third bit of data is read as "1". In the fourth group of reading structures, conductive lines A, B, C, and D are grounded, while conductive lines E and F are precharged to a high level, and conductive lines E and F are connected through an AND gate circuit module. Since both ends of T0 are connected to the data transmission bit line BL A , so the high level of the conductive lines E and F is also maintained, and the fourth bit of data is read as "1". Therefore, the final data reading result of T0 is "1111".

[0073] Similarly, the data reading results of MOS transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14 and T15 are respectively "0111", "0011", "1001", "1100", "0001", "1011", "1101", "1110", "0000", "0101", "0110", "1000", "1010", "0100", "0010". This result shows that the storage array device provided by the present invention can fully cover all possible combinations of four-bit binary data, providing richer and more flexible options for data storage and encoding.

[0074] In summary, the core of the present invention is to construct a storage array device consisting of multiple control sub-lines 1, multiple longitudinally distributed storage cells 2, multiple transversely distributed data transmission bit lines 3, and a data reading module 4. Among them, the storage cell 2 is implemented by a MOS transistor, the gate of which is independently connected to a control sub-line 1, and the source and drain are respectively connected to different data transmission bit lines 3. This layout not only realizes the compact arrangement of the storage cell 2, but also facilitates independent access and operation of the storage cell 2 through the control sub-line 1.

[0075] In addition, the present invention also flexibly adjusts the number of storage cells 2 and data transmission bit lines 3 according to the number of binary bits of the stored data. When the number of stored data bits is an integer between 2 and 4, accurate storage and efficient reading of data can be ensured through specific bit line configuration and reading strategy. In particular, when reading data, a method based on precharging and leakage detection is adopted to determine the state (0 or 1) of the storage cell 2 by judging whether the precharged high level on the data transmission bit line 3 leaks through the storage cell 2. This method not only simplifies the reading process, but also significantly improves the reading speed and accuracy.

[0076] The storage array design of the present invention is not only suitable for specific application scenarios such as HUD devices on automobiles, but can also be widely used in other fields that require efficient and accurate storage and reading of data. Embodiment 2

[0077] The present invention also provides a data storage device, comprising a processor and the storage array device described in Embodiment 1, for storing, processing and accessing data. The storage array device is a core component of the data storage device and is responsible for data storage and reading operations. Embodiment 3

[0078] The present invention also provides a data storage method, which is used for the data storage device described in the second embodiment to store and read data. Figure 8 As shown, the method comprises the following steps:

[0079] S1: When the data storage device receives data to be stored, the processor converts the data into binary coded data and stores the binary coded data in the storage unit via control subline 1;

[0080] S2: When data needs to be read, the processor activates the storage unit 2 corresponding to any control sub-line 1, and pre-charges all data transmission bit lines 3 to a high level or grounds them through the data reading structure 41 according to the binary coded data, and obtains the connection relationship between the activated storage unit 2 and the data transmission bit line 3 corresponding to it;

[0081] S3: Based on the connection relationship, determine whether the precharged high level of the designated data transmission bit line 3 leaks through the data transmission bit line 3 connected to the current storage unit 2:

[0082] If yes, it means that the second port or the third port of the current storage unit 2 is connected to the data transmission bit line 3 of a different voltage state, and the read data is "0" at this time;

[0083] Otherwise, it means that the second port or the third port of the current storage unit 2 is connected to the data transmission bit line 3 of the same voltage state or is not connected to the data transmission bit line 3 of the pre-charged high level, and the read data is "1";

[0084] S4: Determine whether all the data in storage unit 2 have been read:

[0085] If not, return to step S3 to read all storage cells 2 in the storage array one by one;

[0086] If yes, get the data of all storage units 2.

[0087] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0088] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0089] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0090] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0091] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A storage array device, characterized in that: include: Multiple control sub-lines; A plurality of storage units, wherein the plurality of storage units are distributed along a first direction, and a first port of each storage unit is independently connected to a control sub-line; A plurality of data transmission bit lines, wherein the plurality of data transmission bit lines extend along a second direction perpendicular to the distribution direction of the memory cells, and any one of the data transmission bit lines is connected to at least the second port or the third port of a memory cell, and forms a main structure of a memory array with the memory cell; and a data reading module, the data reading module comprising a plurality of groups of data reading structures, each group of data reading structures being evenly connected to a plurality of data transmission bit lines; Each data reading structure includes at least one signal amplifier and conductive lines matching the number of the data transmission bit lines, and during the data reading process, the conductive lines are grounded or precharged to a high level; The setting conditions for the conductive line to be grounded or precharged to a high level include: The number of bits required to store data encoded into binary data is defined as n, and n is an integer between 2 and 4; When the number of bits n of binary data to be encoded into the data to be stored is ≥3, the data reading structure further includes a logic processing module, and for the data transmission bit lines distributed in the second direction, the conductive line connected to the first data transmission bit line is grounded, the conductive line connected to the last data transmission bit line is precharged to a high level, and the multiple conductive lines connected to the middle data transmission bit line are precharged to a high level in sequence, and the remaining conductive lines are grounded, and each time two conductive lines precharged to a high level are connected to the logic processing module; When the number of bits n of binary data to be stored is 2, for the data transmission bit lines distributed in the second direction, the conductive line connected to the first data transmission bit line is grounded, and the remaining conductive lines are precharged to a high level in sequence.

2. The storage array device according to claim 1, wherein: The storage unit is a MOS transistor, the gate of any MOS transistor is independently connected to a control sub-line, and the source and drain thereof are respectively connected to one of the data transmission bit lines.

3. The storage array device according to claim 1, wherein: The number of storage units is set as follows: the number of bits of binary data to be encoded into the required storage data is defined as n, and n is an integer between 2 and 4. .

4. The storage array device according to claim 1, wherein: The number setting conditions of the data transmission bit lines include: The number of bits required to store data encoded into binary data is defined as n, and n is an integer between 2 and 4; When the number of bits required to store data encoded into binary data is n=2, the number of data transmission bit lines is ; When the number of bits n required to store data encoded into binary data is ≥ 3, the number of data transmission bit lines .

5. The storage array device according to claim 1, wherein: The condition for setting the number of data reading structures includes: the number of data reading structures is equal to the number of bits required to store data encoded into binary data.

6. The storage array device according to claim 1, characterized in that: The conductive line precharged to a high level is connected to the signal amplifier.

7. The storage array device according to claim 1, wherein: The logic processing module is an AND gate circuit module.

8. A data storage device, characterized in that: The invention comprises a processor and a storage array device as claimed in any one of claims 1 to 7.

9. A data storage method, characterized in that: Using the data storage device as claimed in claim 8 to store and read data, the method comprises the following steps: S1: converting the data to be stored into binary coded data, and storing the binary coded data in the storage unit; S2: When data needs to be read, any storage unit is activated, and all data transmission bit lines are pre-charged to a high level or grounded according to the binary coded data, and a connection relationship between the activated storage unit and the corresponding data transmission bit line is obtained; S3: Based on the connection relationship, determine whether the precharged high level of the designated data transmission bit line leaks through the data transmission bit line connected to the current storage unit: If yes, it means that the second port or the third port of the current storage unit is connected to a data transmission bit line of a different voltage state, and the read data is "0" at this time; Otherwise, it means that the second port or the third port of the current storage unit is connected to the data transmission bit line of the same voltage state or is not connected to the data transmission bit line of the pre-charged high level, and the read data is "1"; S4: Determine whether the data of all storage units have been read: If not, return to step S3 to read all storage cells in the storage array one by one; If so, get the data of all storage units.

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