Manufacturing method of U-shaped groove

Abstract

The present invention discloses a method for manufacturing a U-shaped groove, comprising: providing a semiconductor substrate on which field oxide is formed, wherein in a first region, the field oxide is used to isolate parallel-arranged first active regions. Forming a hard mask layer in the first region. Performing a first patterned etching on the hard mask layer to form a first groove and a first hard mask layer strip. The first groove is located directly above the first active region and exposes the top surface of the first active region. Applying an organic bottom layer. Performing a second patterned etching on the organic bottom layer to form an organic bottom layer pattern having a second groove, wherein the length directions of the first and second grooves are perpendicular, the second groove has a first overlapping region that overlaps with the first groove, and the top surface of the first active region in the first overlapping region is exposed. Performing a third etching on the semiconductor substrate using the organic bottom layer pattern as a mask to form a U-shaped groove in the first overlapping region. The present invention can increase the process window, improve the morphology of the U-shaped groove, and simplify the process steps.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a U-trench. Background Art

[0002] Capacitance is a bottleneck in the development of traditional DRAM. Semi-floating-gate transistors offer a promising capacitor-free DRAM, compatible with standard logic processes and easier to scale. U-trench isolates the semi-floating-gate Nwell, forming a U-shaped channel at its base. Compared to traditional profile channels, this facilitates device miniaturization. Furthermore, the polysilicon gate in the U-trench is used to store charge, leveraging the tunneling effect to accelerate charge writing.

[0003] In existing methods, U-trench development in a semi-floating gate process compatible with memory arrays and logic circuits requires first using array photolithography (PH) to open the array area. Then, dry etching is used to remove the pad SiN and pad oxide (OX) layers. OX / SIN / OX are then sequentially deposited as a hard mask. U-trench Y etches OX with high selectivity and stops on SIN, forming a Y-direction HM pattern. U-trench X then opens the active area (AA) for X-direction etching. Photoresist (PR) protects the shallow trench isolation (STI) area. Under PR protection, the HM OX / SIN / OX pattern is etched. Finally, under dual HM and PR protection, the Si substrate in the active area is etched to form the U-trench. Wherein, U-trench Y represents the Y direction of the U-trench, U-trench X represents the X direction of the U-trench, U-trench Y is perpendicular to the length direction of the active area, and U-trench X is parallel to the length direction of the active area.

[0004] Therefore, the existing method is to first U-trench Y (U-trench Y first) and then U-trench X (U-trenchX last). The existing method has the following process risks:

[0005] During the U-trench X-etch process, the X-direction HM opening undergoes multiple plasma bombardments, causing the profile to become rounded, resulting in a bell-shaped U-trench profile. This can lead to poor U-trench morphology. A trade-off exists between polymer reduction, carbon coating (SOC) residue, and HM profile, which results in a narrow process window. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for manufacturing a U-shaped groove, which can increase the process window, improve the morphology of the U-shaped groove, and simplify the process steps.

[0007] To solve the above technical problems, the present invention provides a method for manufacturing a U-shaped groove, comprising the following steps:

[0008] A semiconductor substrate with field oxide formed thereon is provided. In a first region, first active regions are isolated by the field oxide, and the first active regions are arranged in parallel.

[0009] The first region is opened, and a hard mask layer is formed in the first region.

[0010] The hard mask layer is subjected to a first patterning etching to form a first trench and a first hard mask layer strip. The first trench is located directly above the first active area and the first trench exposes the top surface of the first active area; the first hard mask layer strip covers the top surface of the field oxide.

[0011] An organic bottom layer is coated, wherein the organic bottom layer completely fills the first trench and extends to above the top surface of the first hard mask layer strip outside the first trench, and the top surface of the organic bottom layer is flat.

[0012] The organic bottom layer is subjected to a second patterning etching to form an organic bottom layer pattern having a second groove, wherein the length direction of the second groove is perpendicular to the length direction of the first groove, the second groove has a first overlapping region overlapping with the first groove and a second overlapping region overlapping with the first hard mask layer strip, and the top surface of the first active area in the first overlapping region is exposed.

[0013] The semiconductor substrate is etched for a third time using the organic bottom layer pattern as a mask, and the third etching forms a U-shaped groove in the first overlapping area; after the third etching is completed, the hard mask layer in the second overlapping area is ensured to have a residual thickness.

[0014] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0015] A further improvement is that the field oxide is formed by a shallow trench isolation process.

[0016] A further improvement is that the hard mask layer includes a first oxide layer and a second nitride layer stacked in sequence.

[0017] A further improvement is that the material of the organic bottom layer includes a carbon film coating (SOC).

[0018] A further improvement is that after the third etching, a step of removing the organic bottom layer is also included.

[0019] A further improvement is that the U-shaped trench is a semi-floating gate trench of a semi-floating gate transistor.

[0020] A further improvement is that the first region is a formation region of each of the half-floating gate transistors, and in the first region, each of the half-floating gate transistors is arranged in rows and columns to form a memory array.

[0021] A further improvement is that a first conductive type well is formed in the first active region, and the first conductive type well is formed in a surface region of the second conductive type well.

[0022] The U-shaped trench passes through the first conductive type well and a bottom surface of the U-shaped trench enters the second conductive type well.

[0023] A further improvement is that the semi-floating gate transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semi-floating gate transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0024] Compared with the prior art in which etching of a pattern perpendicular to the length direction of the active area is first performed and then etching of a pattern parallel to the length direction of the active area is performed, the present invention first etches a pattern parallel to the length direction of the active area, i.e., the first active area in the first region, to form a first groove. The first groove exposes the top surface of the bottom first active area. Thereafter, an organic bottom layer is coated and patterned to form a second groove perpendicular to the length direction of the first groove. In this way, a first overlapping area where the first groove and the second groove overlap is a formation area of ​​the U-shaped groove. Etching the semiconductor substrate using the organic bottom layer pattern as a mask, i.e., a third etching, can form a U-shaped groove in the first overlapping area. Since the side of the second groove is vertical, after the third etching, the vertical side of the second groove can be transferred downward into the U-shaped groove, thereby avoiding the trumpet-mouth morphology of the U-shaped groove and improving the morphology of the U-shaped groove.

[0025] At the same time, in the present invention, after the organic bottom layer pattern is formed, the third etching is directly performed on the semiconductor substrate at the first active area exposed in the first overlapping area, and there is no process of first etching the hard mask layer to form the hard mask layer opening and then etching the semiconductor substrate at the bottom of the hard mask layer. This avoids the contradiction between the need to maintain a certain residual amount of the thickness of the organic bottom layer covering the top of the field oxygen and the need to remove the polymer residue of the organic bottom layer on the side of the opening of the hard mask layer, which limits the process window. Therefore, the present invention can also increase the process window.

[0026] In the present invention, since the hard mask layer in the top area of ​​the first active area has been removed during the formation of the first trench, there is no need to remove the remaining hard mask layer on the surface of the first active area after the U-shaped trench is formed. Therefore, the present invention can also simplify the process steps.

[0027] In addition, the hard mask layer of the present invention can usually be realized by using two layers, namely a stacked layer of an oxide layer and a nitride layer. Compared with the existing method in which the hard mask layer needs to use three layers, namely a stacked layer of an oxide layer, a nitride layer and an oxidation pool, the number and thickness of the film layers of the hard mask layer of the present invention can be reduced, thereby further simplifying the process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0029] Figure 1A-1E It is a three-dimensional structural diagram of the device in each step of the existing method for manufacturing a semi-floating gate U-shaped trench;

[0030] Figure 2A-2E It is a Y-direction cross-sectional structural diagram of the device in each step of the existing semi-floating gate U-shaped trench manufacturing method;

[0031] Figures 3A-3D It is a cross-sectional structural diagram of the device in the X direction in each step of the existing method for manufacturing a semi-floating gate U-shaped trench;

[0032] Figure 4 is a flow chart of a method for manufacturing a U-shaped groove according to an embodiment of the present invention;

[0033] Figures 5A-5C 1 is a cross-sectional structural diagram of a device in the Y direction in each step of the method for manufacturing a U-shaped groove according to an embodiment of the present invention;

[0034] Figures 6A-6C 1 is a cross-sectional structural diagram of a device in the X direction in each step of the method for manufacturing a U-shaped trench according to an embodiment of the present invention;

[0035] Figures 7A-7D It is a three-dimensional structural diagram of the device in each step of the method for manufacturing a U-shaped groove according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present invention are formed based on the analysis of the technical problems of the existing methods. Before describing the embodiments of the present invention in detail, the existing methods are briefly introduced:

[0037] like Figures 1A to 1E As shown, it is a three-dimensional structure diagram of the device in each step of the existing method for manufacturing a semi-floating gate U-shaped trench; Figures 2A to 2E As shown, it is a Y-direction cross-sectional structure diagram of the device in each step of the existing semi-floating gate U-shaped trench manufacturing method; Figures 3A to 3D FIG. 1 is a cross-sectional structural diagram of a device in the X direction in each step of a conventional method for manufacturing a semi-floating gate U-shaped trench. The conventional method for manufacturing a semi-floating gate U-shaped trench includes the following steps:

[0038] like Figure 1A As shown, a semiconductor substrate 102 with a field oxide 103 formed thereon is provided. In a first region 101, the field oxide 103 isolates first active regions, that is, the semiconductor substrate 102 located between the field oxides 103 constitutes each of the first active regions, and the first active regions are arranged in parallel.

[0039] Figure 1A It shows that the X direction is parallel to the length direction of the first active region, and the Y direction is perpendicular to the X direction. Please refer to the cross-sectional structure of the field oxide 103. Figure 2A shown.

[0040] Typically, the semiconductor substrate 102 is a silicon substrate, and the field oxide 103 is formed by a shallow trench isolation process.

[0041] like Figure 1A As shown, the first area 101 is opened.

[0042] Figure 1A , the first area 101 is located on the right side of the dotted line AA.

[0043] Typically, the area to the left of the dotted line AA is also covered by a pad layer, such as a SiN pad layer and a silicon oxide pad layer. The pad layer in the first area 101 is removed, thereby opening the first area 101.

[0044] like Figure 1B As shown, a hard mask layer 104 is formed in the first region 101 .

[0045] Typically, the hard mask layer 104 includes a first oxide layer 104a, a second nitride layer 104b, and a third oxide layer 104c stacked in sequence. Figure 2AShown and Figure 3A shown.

[0046] The processes for forming the first oxide layer 104a, the second nitride layer 104b and the third oxide layer 104c are respectively:

[0047] U-trench OX1 dep; U-trench SiNdep; U-trench OX2 dep.

[0048] The thicknesses of the first oxide layer 104a, the second nitride layer 104b and the third oxide layer 104c can be set to:

[0049] The thickness of the first oxide layer 104a is The thickness of the second nitride layer 104b is The thickness of the third oxide layer 104c is

[0050] like Figure 1C As shown, U-trench Y etching (ET) is performed to form the trench 105. Photolithography definition is required before etching. The structure of the trench 105 can also be referred to Figure 2B and Figure 3A shown. Figure 2B In FIG, the groove 105 is indicated by a dotted box.

[0051] U-trench Y ET uses high selectivity to etch OX and stop on SIN. Figure 2B As described above, the third oxide layer 104 c is etched and stops on the top surface of the second nitride layer 104 b .

[0052] like Figure 2C As shown, U-trench X ET is performed, including:

[0053] like Figure 2C As shown, an organic bottom layer 108 is coated. The organic bottom layer 108 completely fills the trench 105 and extends to above the top surface of the hard mask layer 104 outside the trench 105. The top surface of the organic bottom layer 108 is flat.

[0054] Typically, the material of the organic bottom layer 108 includes SOC.

[0055] like Figure 1D As shown, after that, a photoresist is formed and a pattern in the X direction is defined by photolithography.

[0056] After that, U-trench X ET1 is performed, i.e., the first X-direction pattern etching. U-trench X ET1 uses a low selectivity and a time-controlled endpoint (BT) etching process to etch SiN and OX. Figure 2C As shown, in the bottom area of ​​the trench 105, i.e., the overlapping area of ​​the trenches 105 and 106, the trench 106 formed by the U-trench X ET1 passes through the second nitride layer 104b and stops in the first oxide layer 104a; outside the trench 105, the bottom of the trench 106 stops in the second silicon nitride layer 104b. For the cross section corresponding to the X direction, please refer to Figure 3B shown.

[0057] After that, U-trench X ET2, i.e., the second X-direction pattern etching, is performed. U-trench X ET2 uses a low selectivity BT etching process to etch and expose the silicon surface of the active area in the overlapping area of ​​trenches 105 and 106. Figure 2D As shown, in the bottom area of ​​the trench 105, the first oxide layer 104a at the bottom of the trench 106 is removed, and the Si surface is exposed. Outside the trench 105, the bottom of the trench 106 is still located in the second silicon nitride layer 104b. For the cross section corresponding to the X direction, please refer to Figure 3C As shown, however, from Figure 3C As shown, the top of the opening at the overlapping region of the trenches 105 and 106 has a rounded shape, and the opening gradually becomes rounded under the action of plasma during the etching process.

[0058] like Figure 2D As shown, in the existing process, a certain thickness of the organic bottom layer 108 needs to be retained on the top of the field oxide 103 to protect the field oxide 103. However, in the etching process for forming the corresponding opening, a polymer will be formed on the side of the hard mask layer 104, and the process of removing the polymer, such as the SOC flush process, will damage the organic bottom layer 108. Therefore, there is a contradiction between removing the polymer and protecting the organic bottom layer 108. The two are difficult to balance, thereby reducing the process window.

[0059] Afterwards, if Figure 2E As shown, U-trench X ET3 is the third X-direction pattern etching. U-trench X ET3 is Si etching and a U-trench, i.e., a U-shaped trench 107, is etched in the overlapping area of ​​trenches 105 and 106. For the cross section corresponding to the X direction, please refer to Figure 3D As shown, however, from Figure 3C As shown, the rounded shape of the opening at the overlapping region of trenches 105 and 106 is transferred downward into U-shaped trench 107, making U-shaped trench 107 have a bell-mouth shape. At the same time, at the bottom of trench 106 outside trench 105, the hard mask layer is thinned and a portion of the first oxide layer 104a remains.

[0060] During each U-trench XET etch, the SOC is consumed, and polymer produced during the etching process is deposited on the sides of the hard mask layer 104, i.e., the sides corresponding to the trenches 105 or 106. To maintain a good trench morphology, an SOC flushing process is required to remove the polymer. However, this SOC flushing process affects the thickness of the SOC. If the SOC thickness is too thin, it will weaken the protection of the bottom field oxide 103. Therefore, there is a contradiction between removing the polymer on the sides of the hard mask layer 104 and ensuring the remaining thickness of the SOC, which will reduce the process window.

[0061] exist Figure 1D After the U-trench X ET3 is completed to form the U-shaped trench 107, the hard mask layer still remains on the surface of the active area, for example, the first oxide layer 104a remaining at the bottom of the trench 106 outside the trench 105. Figure 1E As shown, the hard mask layer is etched away (HM RM), typically the oxide layer 104 a is removed (OX RM).

[0062] From the above, it can be seen that the process of the existing method for forming the U-shaped groove 107 can be simplified as follows:

[0063] U-trench OX1 dep, U-trench SiNdep, U-trench OX2 dep, U-trench Y PH / ET, U-trench X PH / ET and OX RM.

[0064] Among them, U-trench X ET includes U-trench X ET1, U-trench X ET2 and U-trench XET3.

[0065] In the existing method, during the U-trench X ET process:

[0066] In OX partial ET (U-trench X ET1 and U-trench X ET2), SOC polymer accumulation on the HM sidewalls needs to be reduced. Otherwise, there is a risk of Si sidewalls remaining during Si ET. However, SOC remains to protect the STI HM from loss, and the SOC flush window is small.

[0067] Si partial etching, i.e., U-trench X ET3, requires a balance between the HM OX remain and the U-trench opening profile.

[0068] After U-trench X etching, additional OX RM is needed to remove the HM OX on AA.

[0069] like Figure 4 FIG. 1 is a flow chart of a method for manufacturing a U-shaped groove 207 according to an embodiment of the present invention; Figures 5A to 5C As shown, it is a Y-direction cross-sectional structure diagram of the device in each step of the manufacturing method of the U-shaped groove 207 according to an embodiment of the present invention; Figures 6A to 6C As shown, it is a cross-sectional structural diagram of the device in the X direction in each step of the manufacturing method of the U-shaped groove 207 according to an embodiment of the present invention; 7A to 7D , which is a three-dimensional structural diagram of the device in each step of the method for manufacturing the U-shaped groove 207 according to an embodiment of the present invention; the method for manufacturing the U-shaped groove 207 according to an embodiment of the present invention includes the following steps:

[0070] Step S101: Figure 7A As shown, a semiconductor substrate 201 with a field oxide 202 is provided. In a first region 301, the field oxide 202 is used to isolate first active regions. That is, the semiconductor substrate 201 located between the field oxides 202 constitutes each of the first active regions, and the first active regions are arranged in parallel.

[0071] Figure 7A It shows why the X direction is parallel to the length direction of the first active region, and the Y direction is perpendicular to the X direction. Please refer to the cross-sectional structure of the field oxide 202. Figure 5A shown.

[0072] In the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate.

[0073] The field oxide 202 is formed by a shallow trench isolation process.

[0074] Step S102: Figure 7A As shown, the first area 301 is opened.

[0075] Figure 7A , the first area 301 is located on the right side of the dotted line BB.

[0076] In some embodiments, the area to the left of the dotted line BB is also covered by a pad layer, such as a SiN pad layer and a silicon oxide pad layer. The pad layer in the first area 301 is removed, thereby opening the first area 301.

[0077] like Figure 7B As shown, a hard mask layer 203 is formed in the first region 301 .

[0078] In the embodiment of the present invention, the hard mask layer 203 includes a first oxide layer 203a and a second nitride layer 203b stacked in sequence. Figure 5A shown.

[0079] The processes for forming the first oxide layer 203a and the second nitride layer 203b are respectively:

[0080] U-trench OX dep, U-trench SiN dep.

[0081] In some embodiments, the thickness of the first oxide layer 203a and the second nitride layer 203b can be set to:

[0082] The thickness of the first oxide layer 203a is The thickness of the second nitride layer 203b is

[0083] Step S103: Figure 7C As shown, the hard mask layer 203 is patterned and etched for the first time to form first trenches 204 and first hard mask layer strips. The first hard mask layer strips are strip structures composed of the hard mask layer 203 located between the first trenches 204.

[0084] The first trench 204 is located directly above the first active region and exposes the top surface of the first active region; the first hard mask layer is strip-shaped and covers the top surface of the field oxide 202. Please refer to the cross-sectional structure after the first trench 204 is formed. Figure 5B shown. Figure 6A The first groove 204 is also shown in a dotted box.

[0085] According to the X and Y directions, the first patterning etching is U-trench XET. U-trench XET uses a high selectivity ratio HM SIN / OX and stops on Si (stop on Si). Si represents silicon when the semiconductor substrate 201 is a silicon substrate.

[0086] At the same time, if Figure 5B As shown, in the embodiment of the present invention, the second nitride layer 203b in the hard mask layer 203 is used on the field oxygen 202 to ensure that the oxide layer of the field oxygen 202 is not consumed. Therefore, the embodiment of the present invention is more flexible in processing the subsequent organic bottom layer 205 such as SOC, eliminating the contradictions caused by the existing method in the processing of SOC and the technical problem of the small process window caused by it.

[0087] Step S104: Figure 5C As shown, an organic bottom layer 205 is coated, which completely fills the first trench 204 and extends to the top surface of the first hard mask layer strip outside the first trench 204. The top surface of the organic bottom layer 205 is flat. Figure 6B FIG also shows a cross-sectional structure after coating the organic bottom layer 205 along the X direction.

[0088] In the embodiment of the present invention, the material of the organic bottom layer 205 includes SOC.

[0089] Step S105: Figure 5C As shown, the organic bottom layer 205 is subjected to a second patterning etching to form an organic bottom layer 205 pattern having a second groove 206, wherein the length direction of the second groove 206 is perpendicular to the length direction of the first groove 204, and the second groove 206 has a first overlapping region overlapping with the first groove 204 and a second overlapping region overlapping with the first hard mask layer strip, and the top surface of the first active area in the first overlapping region is exposed. Figure 5C In FIG, the first groove 204 shown is the first overlapping area where the first groove 204 and the second groove 206 overlap. Figure 6B In FIG, the second groove 206 shown is also the first overlapping area.

[0090] Step S106: Figure 5C As shown, the semiconductor substrate 201 is etched for the third time using the organic bottom layer 205 pattern as a mask, and the third etching forms a U-shaped groove 207 in the first overlapping area; after the third etching is completed, the hard mask layer 203 in the second overlapping area is ensured to have a residual thickness. Figure 5C As shown, during the third etching process, the hard mask layer 203 in the second overlapping region will also be lost to a certain extent. In the embodiment of the present invention, it is necessary to ensure that the hard mask layer 203 has a residual thickness after the third etching is completed. Figure 6B The structure of the hard mask layer 203 is not shown because it is located above the first active region.

[0091] According to the X direction and the Y direction, the second patterning etching and the third etching are U-trenchYET.

[0092] In the embodiment of the present invention, when the U-trench X completely etches the HM, i.e., the hard mask layer 203, on the AA and exposes the AA, the vertical profile formed by the SOC etching, i.e., the second patterned etching, is directly etched into the semiconductor substrate 201, such as silicon, to form a Si trench, i.e., a U-shaped trench 207. Since there is no additional etching process, the vertical profile of the SOC can be transferred to the Si trench, forming a vertical U-shaped trench.

[0093] In the embodiment of the present invention, Figure 6C As shown, after the third etching, the step of removing the organic bottom layer 205 is also included.

[0094] In addition, compared with the existing process, in the embodiment of the present invention, the U-trench X etching process has completely etched the HM. After removing the organic bottom layer 205, such as stripping the SOC, the final U-trench is directly obtained, which is a simple process.

[0095] In the embodiment of the present invention, the U-shaped trench 207 is a semi-floating gate trench of a semi-floating gate transistor.

[0096] The first region 301 is a formation region of the half-floating gate transistors. In the first region 301 , the half-floating gate transistors are arranged in rows and columns to form a memory array.

[0097] The first active region is formed with a first conductive type well, which is formed in a surface region of the second conductive type well.

[0098] The U-shaped trench 207 passes through the first conductive type well and the bottom surface of the U-shaped trench 207 enters the second conductive type well.

[0099] In an embodiment of the present invention, the semi-floating gate transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the semi-floating gate transistor may be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0100] After forming the U-shaped trench 207, the semi-floating gate transistor can be formed by the same method as in the prior art. For example:

[0101] A floating gate dielectric layer is formed, where the floating gate dielectric layer covers the inner surface of the U-shaped trench 207 and extends to the surface of the first conductive type well outside the U-shaped trench 207 .

[0102] A floating gate dielectric window penetrating the floating gate dielectric layer is formed in the top region of the first conductive type well on the drain region side outside the U-shaped trench 207 .

[0103] A polysilicon floating gate is formed, which completely fills the U-shaped groove 207 and extends to the outside of the U-shaped groove 207. The polysilicon floating gate also completely fills the floating gate dielectric window and contacts the first conductive type well to form a PN junction. In this way, the polysilicon floating gate has a semi-floating gate structure.

[0104] Then, a control gate is formed, which is located on top of the polysilicon floating gate with an inter-gate dielectric layer between them. The control gate is also located on the surface of the first conductive type well outside the floating gate dielectric window and is separated from the first conductive type well by a corresponding gate dielectric layer.

[0105] A source region and a drain region heavily doped with the first conductivity type are self-alignedly formed on both sides of a gate structure formed by superposition of a polysilicon floating gate and a control gate.

[0106] Compared with the prior art that first etches a pattern perpendicular to the length direction of the active region and then etches a pattern parallel to the length direction of the active region, the embodiment of the present invention first etches a pattern parallel to the length direction of the active region, i.e., the first active region in the first region 301, to form a first trench 204. The first trench 204 exposes the top surface of the first active region at the bottom. Then, an organic bottom layer 205 is coated and patterned to form a second trench 206 perpendicular to the length direction of the first trench 204. In this way, the first overlapping area where the first groove 204 and the second groove 206 overlap is the formation area of ​​the U-shaped groove 207. The semiconductor substrate 201 is etched using the organic bottom layer 205 pattern as a mask, that is, the third etching can form the U-shaped groove 207 in the first overlapping area. Since the side of the second groove 206 is vertical, after the third etching, the vertical side of the second groove 206 can be transferred downward into the U-shaped groove 207, thereby avoiding the trumpet-mouth morphology of the U-shaped groove 207, and thus improving the morphology of the U-shaped groove 207.

[0107] At the same time, in the embodiment of the present invention, after the organic bottom layer 205 pattern is formed, the third etching is directly performed on the semiconductor substrate 201 at the first active area exposed in the first overlapping area. There is no process of first etching the hard mask layer 203 to form an opening in the hard mask layer 203 and then etching the semiconductor substrate 201 at the bottom of the hard mask layer 203. This avoids the contradiction between the need to maintain a certain residual amount of the thickness of the organic bottom layer 205 covering the top of the field oxide 202 and the need to remove the polymer residue of the organic bottom layer 205 on the side of the opening of the hard mask layer 203, which limits the process window. Therefore, the embodiment of the present invention can also increase the process window.

[0108] In the embodiment of the present invention, since the hard mask layer 203 in the top area of ​​the first active area has been removed during the formation of the first trench 204, there is no need to remove the remaining hard mask layer 203 on the surface of the first active area after the U-shaped trench 207 is formed. Therefore, the embodiment of the present invention can also simplify the process steps.

[0109] In addition, the hard mask layer 203 of the embodiment of the present invention is usually realized by using two layers, namely a stacked layer of an oxide layer and a nitride layer. Compared with the existing method in which the hard mask layer 203 needs to use three layers, namely a stacked layer of an oxide layer, a nitride layer and an oxidation pool, the number and thickness of the film layers of the hard mask layer of the embodiment of the present invention can be reduced, thereby further simplifying the process steps.

[0110] In the method of the present embodiment, the process can be simplified to: U-trench OX dep, U-trench SiN dep, U-trench X PH / ET, and U-trench Y PH / ET. Compared to the corresponding processes of the prior art methods, namely U-trench OX1 dep, U-trench SiN dep, U-trench OX2 dep, U-trench Y PH / ET, U-trench X PH / ET, and OXRM, the method of the present embodiment reduces the number of process layers for HM dep and eliminates the final OXRM, thus simplifying the process. Most importantly, the present embodiment performs U-trench X PH / ET first, followed by U-trench Y PH / ET, and the specific process conditions are modified. This results in a better morphology for the U-shaped trench 207 of the present embodiment, eliminating the appearance of a bell-mouth morphology. Furthermore, the narrow process window caused by the residual SOC thickness and polymer residue on the HM side surfaces, which occurs during the multi-layer etching of the HM in the prior art, is avoided.

[0111] In the method of the embodiment of the present invention, the U-trench X etching process, or U-trench X ET, is simple and controllable, with a wide process window. U-trench Y etching forms a vertical U-trench profile in a single step, simplifying the process and eliminating the need for additional AA area removal.

[0112] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A method for manufacturing a U-shaped groove, characterized in that: The steps include: Providing a semiconductor substrate with field oxide formed thereon, wherein in a first region, first active regions are isolated by the field oxide, and the first active regions are arranged in parallel; opening the first region and forming a hard mask layer in the first region; Performing a first patterned etching on the hard mask layer to form a first trench and a first hard mask layer strip; the first trench is located directly above the first active area and the first trench exposes the top surface of the first active area; the first hard mask layer strip covers the top surface of the field oxide; Applying an organic bottom layer, wherein the organic bottom layer completely fills the first trench and extends to above the top surface of the first hard mask layer strip outside the first trench, and the top surface of the organic bottom layer is flat; Performing a second patterning etching on the organic bottom layer to form an organic bottom layer pattern having a second trench, wherein the length direction of the second trench is perpendicular to the length direction of the first trench, the second trench having a first overlapping region overlapping with the first trench and a second overlapping region overlapping with the first hard mask layer strip, wherein the top surface of the first active area is exposed in the first overlapping region; performing a third etching on the semiconductor substrate using the organic bottom layer pattern as a mask, wherein the third etching forms a U-shaped groove in the first overlapping region; After the third etching is completed, it is ensured that the hard mask layer in the second overlapping region has a residual thickness.

2. The method for manufacturing a U-shaped groove according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.

3. The method for manufacturing a U-shaped groove according to claim 1, wherein: The field oxide is formed by a shallow trench isolation process.

4. The method for manufacturing a U-shaped groove according to claim 1, wherein: The hard mask layer includes a first oxide layer and a second nitride layer stacked in sequence.

5. The method for manufacturing a U-shaped groove according to claim 1, wherein: The material of the organic bottom layer includes SOC.

6. The method for manufacturing a U-shaped groove according to claim 1, wherein: After the third etching, the method further includes a step of removing the organic bottom layer.

7. The method for manufacturing a U-shaped groove according to claim 1, wherein: The U-shaped trench is a semi-floating gate trench of a semi-floating gate transistor.

8. The method for manufacturing a U-shaped groove according to claim 7, wherein: The first region is a formation region of the half-floating gate transistors. In the first region, the half-floating gate transistors are arranged in rows and columns to form a memory array.

9. The method for manufacturing a U-shaped groove according to claim 7, wherein: The first active region is formed with a first conductive type well, and the first conductive type well is formed in a surface area of ​​the second conductive type well; The U-shaped trench passes through the first conductive type well and a bottom surface of the U-shaped trench enters the second conductive type well.

10. The method for manufacturing a U-shaped groove according to claim 9, wherein: The semi-floating gate transistor is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the semi-floating gate transistor is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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