A novel VDMOS and a preparation method thereof

Abstract

A novel VDMOS and its fabrication method are disclosed. This relates to the field of semiconductor technology. The method includes the following steps: Step S100, fabricating a plurality of spaced P-body regions within an epitaxial wafer; Step S200, fabricating a plurality of spaced N+ source regions and N+ low-resistivity regions within the P-body regions; Step S300, fabricating a gate dielectric on the epitaxial wafer, and fabricating polysilicon on the gate dielectric above the P-body regions sandwiched between the N+ source regions and the N+ low-resistivity regions; Step S400, depositing an isolation layer on the epitaxial wafer, and fabricating source (S) and gate (G) electrodes by opening windows between adjacent N+ source regions and above the P-body regions sandwiched between the N+ source regions and the N+ low-resistivity regions; Step S500, fabricating a drain (D) electrode at the bottom of the epitaxial wafer, completing the fabrication of the entire device. In this invention, the N+ low-resistivity regions and N+ source regions are fabricated in the same step. Compared with currently commercial products, this method does not add additional process steps, offering high cost-effectiveness and facilitating commercialization.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a novel VDMOS and its fabrication method. Background Technology

[0002] In the field of power electronic device technology, MOSFETs, as a commonly used power semiconductor, have replaced transistors as one of the most commonly used switching devices in the power semiconductor field. Throughout decades of iteration, improving power density has consistently been one of the main directions of MOSFET development. Reducing the on-resistance per unit area is the most effective method to increase device power density and is also one of the most significant research and development directions for MOSFETs.

[0003] VDMOS, a type of MOSFET, is typically used in high-voltage devices. Currently, the industry's main measures to reduce the on-resistance of VDMOS are reducing the cell pitch and adopting a superjunction structure. With the improvement of process precision, the cell pitch of conventional VDMOS structures has been reduced to its theoretical limit in recent years. This is mainly because as the cell pitch continues to decrease, the width of the N-voltage region sandwiched by the P-body region becomes lower and lower, and the resistance of this region, i.e., the JFET resistance, will increase. As the cell pitch approaches its limit, the reduction in on-resistance caused by reducing the cell pitch and the increase in on-resistance caused by the increase in JFET resistance reach a balance. Further reducing the cell pitch will actually increase the overall resistance of the device. Therefore, new technologies and structures must be adopted to further reduce its on-resistance. Summary of the Invention

[0004] This invention addresses the research and development direction of reducing the on-resistance per unit area of ​​MOSFETs by providing a novel VDMOS and its fabrication method.

[0005] The technical solution of this invention is:

[0006] A novel VDMOS fabrication method includes the following steps:

[0007] Step S100: Prepare several spaced P-body regions within the epitaxial wafer;

[0008] Step S200: Prepare several N+ source regions and N+ low-resistivity regions spaced apart within the P-body region;

[0009] Step S300: A gate dielectric is prepared on the epitaxial wafer, and polysilicon is prepared on the gate dielectric above the P-body region sandwiched between the N+ source region and the N+ low-resistivity region.

[0010] In step S400, an isolation layer is deposited on the epitaxial wafer, and windows are opened between adjacent N+ source regions and above the P-body region sandwiched between the N+ source region and the N+ low-resistivity region to prepare the S-electrode and G-electrode.

[0011] In step S500, a D electrode is fabricated on the bottom of the epitaxial wafer, and the entire device fabrication is completed.

[0012] Specifically, step S100 includes:

[0013] Step S110: Using photolithography, a mask is used to protect the outer region of the P-body region; through diffusion or ion implantation, several spaced P-body regions are formed.

[0014] Specifically, the thickness of the P-body region is 1-20 μm, and the spacing is 1-10 μm.

[0015] Specifically, step S200 includes:

[0016] In step S210, using photolithography, a mask is used to protect the outer regions of the N+ source region and the N+ low-resistivity region; through diffusion or ion implantation, several N+ source regions and N+ low-resistivity regions are formed at intervals.

[0017] Specifically, the thicknesses of the N+ source region and the N+ low-resistivity region are 0.5-10 μm, respectively.

[0018] Specifically, step S300 includes:

[0019] Step S310: The gate dielectric is fabricated on the epitaxial wafer using a thermal oxidation technique;

[0020] In step S320, a photolithography process is used to protect the external region of the P-body region sandwiched between the N+ source region and the N+ low-resistivity region using a mask. Polycrystalline silicon is then fabricated on the gate dielectric above the P-body region sandwiched between the N+ source region and the N+ low-resistivity region using chemical vapor deposition.

[0021] Specifically, step S400 includes:

[0022] Step S410: Prepare an isolation layer using chemical vapor deposition. Using photolithography, use a mask to protect the external region of the P-body region sandwiched between adjacent N+ source regions and between the N+ source region and the N+ low-resistivity region. Use etching to open windows in the P-body region sandwiched between adjacent N+ source regions and between the N+ source region and the N+ low-resistivity region.

[0023] In step S420, the corresponding S electrode and G electrode are prepared at the window opening of the P body region between adjacent N+ source regions and between the N+ source region and the N+ low-resistivity region by means of a stripping process or an etching process.

[0024] A novel VDMOS comprises, from bottom to top, a drain electrode, an epitaxial wafer, a gate dielectric, polysilicon, and an isolation layer;

[0025] The top of the epitaxial wafer is provided with:

[0026] The P-body region is provided with several spaced apart from each other, each extending downward from the top surface of the epitaxial sheet;

[0027] The N+ source region is provided in several forms, each extending downward from the top of the P body region;

[0028] The N+ low-resistivity region is provided in several forms, each extending downward from the top surface of the P-body region; the N+ source regions are located between adjacent N+ low-resistivity regions.

[0029] The polysilicon is provided with several gate dielectrics spaced apart from each other, which are respectively located on the top surface of the P-body region sandwiched by the N+ source region and the N+ low-resistivity region.

[0030] The isolation layer is located on the top surface of the gate dielectric and the top surface of the polysilicon; the isolation layer is provided with:

[0031] The S electrode extends downward from the top surface of the isolation layer into the P-body region and connects with the P-body region and the adjacent N+ source region to form an ohmic contact.

[0032] The G electrode extends downward from the top surface of the isolation layer into the polycrystalline silicon and forms an ohmic contact with the polycrystalline silicon.

[0033] Specifically, the epitaxial wafer includes an N+ substrate layer and an N- withstand voltage layer connected sequentially from bottom to top;

[0034] The D electrode is connected to the N+ substrate layer to form an ohmic contact.

[0035] The N+ source region and the N+ low-resistivity region extend downward from the top surface of the epitaxial wafer, and their bottom surfaces are higher than the bottom surface of the P-body region.

[0036] Beneficial effects of this invention:

[0037] Compared to traditional VDMOSFET structures, this invention introduces a highly doped N+ low-resistivity region inside the P-body region of the device. One side of this N+ low-resistivity region is connected to the gate channel, effectively reducing the JFET resistance. Furthermore, the N+ low-resistivity region is shielded by the P-body region in the vertical direction, which can effectively reduce the high voltage surge from the bottom drain when the device is off, thus not affecting the device's breakdown voltage. Moreover, the N+ low-resistivity region and the N+ source region of this invention are prepared in the same step. Compared with currently commercial products, no additional process steps are added, resulting in high cost-effectiveness and facilitating commercialization. Attached Figure Description

[0038] Figure 1This is a process flow diagram of the present invention;

[0039] Figure 2 This is a schematic diagram of the cross-sectional structure of the device in step S100;

[0040] Figure 3 This is a schematic diagram of the cross-sectional structure of the device in step S200;

[0041] Figure 4 This is a schematic diagram of the gate dielectric structure fabricated in step S300;

[0042] Figure 5 This is a schematic diagram of the preparation of the polycrystalline silicon structure in step S300;

[0043] Figure 6 This is a schematic diagram of the structure of the deposited isolation layer in step S500;

[0044] Figure 7 This is a schematic diagram of the windowing structure at the P-body region sandwiched by the N+ source region, N+ source region, N+ low-resistivity region in step S500.

[0045] Figure 8 This is a schematic diagram of the S-electrode and G-electrode structures prepared in step S500;

[0046] Figure 9 This is a schematic diagram of the structure after preparation;

[0047] Figure 10 This is a schematic diagram of a conventional MOSFET structure;

[0048] In the figure, 1 is the epitaxial wafer, 2 is the P-body region, 3 is the N+ source region, 4 is the N+ low-resistivity region, 5 is the gate dielectric, 6 is polysilicon, 7 is the isolation layer, 8 is the S electrode, 9 is the G electrode, 10 is the D electrode, 11 is the N+ substrate layer, and 12 is the N- withstand voltage layer. Detailed Implementation

[0049] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0050] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0051] The following is for reference. Figure 1-9 Describe the present invention;

[0052] A novel VDMOS fabrication method includes the following steps:

[0053] Step S100: Prepare several spaced P-body regions 2 within the epitaxial wafer 1; such as Figure 2 As shown;

[0054] Step S110: Using photolithography, a mask is used to protect the outer region of the P-body region 2; through diffusion or ion implantation, several spaced P-body regions 2 are formed.

[0055] Accordingly, epitaxial wafer 1 is an N-type epitaxial wafer, comprising an N+ substrate layer 11 and an N- withstand voltage layer 12 from bottom to top. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the N+ substrate layer 11 is 90-1500 μm, the thickness of the N- withstand voltage layer 12 is 10-500 μm, the thickness of the P-body region 2 is 1-20 μm, and the spacing between them is 1-10 μm. The N-type doping concentration range is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e. 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device;

[0056] In this embodiment, the thickness of the epitaxial wafer 1 is 350 μm, the thickness of the N+ substrate layer 13 is 300 μm, and the doping concentration is 2e. 19 .cm -3 The N-terminal withstand layer 14 has a thickness of 50 μm and a doping concentration of 1e. 16 .cm -3 The thickness of the P-body region 2 is 3 μm, the spacing is 2 μm, and the doping concentration is 3e. 18 .cm -3 The P-body region 2 was prepared using an ion implantation process.

[0057] Step S200: A plurality of N+ source regions 3 and N+ low-resistivity regions 4 are prepared at intervals within the P-body region 2; as shown... Figure 3 As shown;

[0058] Step S210: Using photolithography, a mask is used to protect the external regions of N+ source region 3 and N+ low-resistivity region 4; through diffusion or ion implantation, several N+ source regions 3 and N+ low-resistivity regions 4 are formed at intervals.

[0059] Several N+ source regions 3 are located between adjacent N+ low-resistivity regions 4, as in this case... Figure 3 As shown, two N+ source regions 3 are spaced apart between two N+ low-resistivity regions 4;

[0060] Correspondingly, the N+ source region 3 and the N+ low-resistivity region 4 extend downward from the top surface of the epitaxial wafer 1, with their bottom surfaces higher than the bottom surface of the P-body region 2, and their thicknesses ranging from 0.5 to 10 μm, with doping concentrations in the range of 1e. 18 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device;

[0061] In this embodiment, the thickness of N+ source region 3 and N+ low-resistivity region 4 is 3 μm, and the doping concentration is 2e⁻¹. 19. cm -3 The N+ source region 3 and the N+ low-resistivity region 4 were prepared using ion implantation.

[0062] Step S300: Prepare gate dielectric 5 on epitaxial wafer 1, such as... Figure 4 As shown; and a polysilicon 6 corresponding to the P-body region 2 sandwiched between the N+ source region 3 and the N+ low-resistivity region 4 is fabricated on the gate dielectric 5, as shown. Figure 5 As shown;

[0063] Step S310: The gate dielectric 5 is prepared on the epitaxial wafer 1 using a thermal oxidation technique;

[0064] Step S320: Using photolithography, a mask is used to protect the external region of the P-body region 2 sandwiched between the N+ source region 3 and the N+ low-resistivity region 4. Polycrystalline silicon 6 is then fabricated on the gate dielectric 5 above the P-body region 2 sandwiched between the N+ source region 3 and the N+ low-resistivity region 4 by chemical vapor deposition.

[0065] Correspondingly, the gate dielectric 5 is made of SiO2 with a thickness of 40-500nm, and the polysilicon 6 has a thickness of 100nm-5um;

[0066] In this embodiment, 80nm SiO2 is prepared using thermal oxidation technology as the gate dielectric 5, and 500nm polycrystalline silicon 6 is prepared using chemical vapor deposition.

[0067] Step S400, deposit isolation layer 7 on epitaxial wafer, such as Figure 6 As shown, windows are opened between adjacent N+ source regions 3 and above the P-body region 2 sandwiched between N+ source region 3 and N+ low-resistivity region 4, respectively. Figure 7 As shown, S electrode 8 and G electrode 9 are fabricated. Figure 8 As shown;

[0068] Step S410: Prepare isolation layer 7 using chemical vapor deposition. Using photolithography, use a mask to protect the external region of the adjacent N+ source region 3 and the P-body region 2 sandwiched between N+ source region 3 and N+ low-resistivity region 4. Use etching to open windows at the adjacent N+ source region 3 and the P-body region 2 sandwiched between N+ source region 3 and N+ low-resistivity region 4.

[0069] In step S420, by means of a stripping process or an etching process, the corresponding S electrode 8 and G electrode 9 are prepared at the window openings of the P body region 2 sandwiched between adjacent N+ source regions 3 and N+ low-resistivity region 4.

[0070] Correspondingly, the isolation layer 7 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. It is etched using ICP dry etching to create a window. The window depth is greater than the sum of the thicknesses of the isolation layer 7 and the gate dielectric 5. The S electrode 8 extends downward from the top surface of the isolation layer 7 and connects with the N+ source region 3 and the P body region 2 to form an ohmic contact. The G electrode 9 extends downward from the top surface of the isolation layer 7 and connects with the polysilicon 6 to form an ohmic contact.

[0071] In this embodiment, Si3N4 is used as the isolation layer 7 with a thickness of 200nm. ICP dry etching is used to create a window with a depth of 300nm. The S electrode 8 and G electrode 9 are fabricated using two Al / Ti metal layers.

[0072] Step S600: D electrode 10 is fabricated on the bottom of the epitaxial wafer, completing the fabrication of the entire device; as shown below. Figure 9 As shown;

[0073] In step S610, the D electrode 10 is fabricated on the bottom of the epitaxial wafer 1 through a thinning process and a back gold process, and the entire device is fabricated.

[0074] Accordingly, the epitaxial wafer 1 is thinned using a thinning process, and the D electrode 10 is fabricated using a back-gold process. The D electrode 10 and the N+ substrate layer 11 are connected to form an ohmic contact.

[0075] In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and the D electrode 10 is fabricated using two Al / Ti metal layers, thus completing the fabrication of the entire device.

[0076] A novel VDMOS includes, from bottom to top, a drain electrode 10, an epitaxial wafer 1, a gate dielectric 5, a polysilicon 6, and an isolation layer 7.

[0077] The top of the epitaxial wafer 1 is provided with:

[0078] P-body region 2 is provided with several spaced apart from each other, each extending downward from the top surface of the epitaxial sheet 1;

[0079] N+ source region 3 is provided in several parts, which extend downward from the top surface of P body region 2, and their bottom surface is higher than the bottom surface of P body region 2.

[0080] There are several N+ low-resistivity regions 4, which extend downward from the top surface of the P-body region 2, and their bottom surfaces are higher than the bottom surfaces of the P-body region 2; several N+ source regions 3 are located between adjacent N+ low-resistivity regions 4; the bottom surfaces of the N+ source regions 3 are flush with the bottom surfaces of the N+ low-resistivity regions 4.

[0081] Within the epitaxial wafer 1, along the horizontal direction of the region where the N+ low-resistivity region 4 is located, a repeating structure of N- withstand layer 12, N+ low-resistivity region 4, P-body region 2, N+ source region 3, P-body region 2, and N+ low-resistivity region 4 is formed;

[0082] The polysilicon 6 has several gate dielectric 5s that are spaced apart from each other and are located on the top surface of the P-body region 2 sandwiched between the N+ source region 3 and the N+ low-resistivity region 4.

[0083] The isolation layer 7 is located on the top surface of the gate dielectric 5 and the top surface of the polysilicon 6; the isolation layer 7 is provided with:

[0084] The S electrode 8 extends downward from the top surface of the isolation layer 7 into the P body region 2 and connects with the P body region 2 and the adjacent N+ source region 3 to form an ohmic contact.

[0085] The G electrode 9 extends downward from the top surface of the isolation layer 7 into the polysilicon 6 and forms an ohmic contact with the polysilicon 6.

[0086] Epitaxial wafer 1 includes an N+ substrate layer 11 and an N- withstand voltage layer 12 connected sequentially from bottom to top;

[0087] The D electrode 10 and the N+ substrate layer 11 are connected to form an ohmic contact.

[0088] The present invention has the following advantages:

[0089] Compared to traditional VDMOSFET structures, this invention introduces a highly doped N+ low-resistivity region 4 inside the P-body region 2 of the device. One side of this N+ low-resistivity region 4 is connected to the gate channel, effectively reducing the JFET resistance. Furthermore, the N+ low-resistivity region 4 is shielded by the P-body region 2 in the vertical direction, effectively reducing high-voltage surges from the bottom D electrode 10 when the device is off, thus not affecting the device's breakdown voltage. Moreover, the N+ low-resistivity region 4 and the N+ source region 3 of this invention are fabricated in the same step. Compared to currently commercial products, this does not require additional process steps, offering high cost-effectiveness and facilitating commercialization. Compared to traditional VDMOSFET structures (…),… Figure 10 Under the same process conditions, this invention prepares a novel VDMOSFET ( Figure 9 The on-resistance was reduced by 5%-10%.

[0090] Regarding the information disclosed in this case, the following points need to be clarified:

[0091] The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs.

[0092] Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0093] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A novel method for fabricating VDMOS, characterized in that, Includes the following steps: Step S100: Prepare several spaced P-body regions (2) within the epitaxial wafer (1); Step S200: Prepare several N+ source regions (3) and N+ low-resistivity regions (4) spaced apart in the P-body region (2). Step S300: A gate dielectric (5) is prepared on the epitaxial wafer (1), and polysilicon (6) is prepared on the gate dielectric (5) above the P-body region (2) sandwiched between the N+ source region (3) and the N+ low-resistivity region (4). Step S400: Deposit an isolation layer (7) on the epitaxial wafer, and open windows between adjacent N+ source regions (3) and above the P-body region (2) sandwiched between the N+ source region (3) and the N+ low-resistivity region (4) to prepare the S-electrode (8) and the G-electrode (9). Step S500: D electrode (10) is prepared on the bottom of the epitaxial wafer, and the entire device is prepared.

2. The novel VDMOS fabrication method according to claim 1, characterized in that, Step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the P-body region (2); through diffusion or ion implantation, several spaced P-body regions (2) are formed.

3. A novel VDMOS fabrication method according to claim 1 or 2, characterized in that, The thickness of the P-body region (2) is 1-20 μm, and the spacing is 1-10 μm.

4. The novel VDMOS fabrication method according to claim 1, characterized in that, Step S200 includes: In step S210, using photolithography, a mask is used to protect the external regions of the N+ source region (3) and the N+ low-resistivity region (4); through diffusion or ion implantation, several N+ source regions (3) and N+ low-resistivity regions (4) are formed at intervals.

5. A novel VDMOS fabrication method according to claim 1 or 4, characterized in that, The thicknesses of the N+ source region (3) and the N+ low-resistivity region (4) are 0.5-10 μm, respectively.

6. The novel VDMOS fabrication method according to claim 1, characterized in that, Step S300 includes: Step S310: The gate dielectric (5) is prepared on the epitaxial wafer (1) using the thermal oxidation technique. In step S320, a photolithography process is used to protect the external region of the P-body region (2) sandwiched between the N+ source region (3) and the N+ low-resistivity region (4). Polycrystalline silicon (6) is then fabricated on the gate dielectric (5) above the P-body region (2) sandwiched between the N+ source region (3) and the N+ low-resistivity region (4) by chemical vapor deposition.

7. The novel VDMOS fabrication method according to claim 1, characterized in that, Step S400 includes: Step S410: Prepare an isolation layer (7) using chemical vapor deposition. Using photolithography, use a mask to protect the external area of ​​the P-body region (2) sandwiched between adjacent N+ source regions (3) and between N+ source regions (3) and N+ low-resistivity regions (4). Use etching to open windows in the P-body region (2) sandwiched between adjacent N+ source regions (3) and between N+ source regions (3) and N+ low-resistivity regions (4). In step S420, the corresponding S electrode (8) and G electrode (9) are prepared at the opening of the P body region (2) sandwiched between adjacent N+ source regions (3) and N+ low-resistivity region (4) by stripping or etching process.

8. A novel VDMOS, prepared by the novel VDMOS preparation method according to any one of claims 1-7, characterized in that, It includes a D electrode (10), an epitaxial wafer (1), a gate dielectric (5), a polysilicon (6), and an isolation layer (7) arranged sequentially from bottom to top. The top of the epitaxial wafer (1) is provided with: The P-body region (2) is provided with several spaced apart from each other, each extending downward from the top surface of the epitaxial sheet (1); The N+ source region (3) is provided in several parts, which extend downward from the top surface of the P body region (2); The N+ low-resistivity region (4) is provided in several forms, which extend downward from the top surface of the P body region (2); the N+ source regions (3) are located between adjacent N+ low-resistivity regions (4); The polysilicon (6) is provided with several gate dielectrics (5) that are spaced apart from each other and located on the top surface of the P-body region (2) sandwiched between the N+ source region (3) and the N+ low-resistivity region (4); The isolation layer (7) is located on the top surface of the gate dielectric (5) and the top surface of the polysilicon (6); the isolation layer (7) is provided with: The S electrode (8) extends downward from the top surface of the isolation layer (7) into the P body region (2) and connects with the P body region (2) and the adjacent N+ source region (3) to form an ohmic contact; The G electrode (9) extends downward from the top surface of the isolation layer (7) into the polysilicon (6) and forms an ohmic contact with the polysilicon (6).

9. A novel VDMOS according to claim 8, characterized in that, The epitaxial wafer (1) includes an N+ substrate layer (11) and an N- withstand voltage layer (12) connected sequentially from bottom to top. The D electrode (10) and the N+ substrate (11) are connected to form an ohmic contact.

10. A novel VDMOS according to claim 8, characterized in that, The N+ source region (3) and the N+ low-resistivity region (4) extend downward from the top surface of the epitaxial wafer (1), and their bottom surfaces are higher than the bottom surface of the P-body region (2).

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