Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure comprises providing a substrate; forming a mask structure on the substrate, the mask structure comprising an initial first mask layer, an initial second mask layer located on the initial first mask layer, and an initial third mask layer located on the initial second mask layer, the mask structure exposing a portion of the substrate surface; etching the substrate using the mask structure as a mask to form a first groove in the substrate; removing a portion of the initial second mask layer in a direction parallel to the substrate surface to form a second mask layer, and forming a second groove between adjacent initial first and initial third mask layers; removing the initial first mask layer from the sidewalls of the second groove to form a first mask layer, the first mask layer exposing a portion of the substrate surface adjacent to the first groove; and forming a buffer layer on the substrate surface, the sidewall surfaces, and the bottom surface of the first groove exposed by the first mask layer. The semiconductor structure formed by this method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor structures, shallow trench isolation technology has gradually replaced traditional isolation methods due to its advantages in improving device density and reducing leakage current.

[0003] In shallow trench isolation technology, in order to repair the shallow trench corners and prevent leakage, a buffer layer needs to be generated on the shallow trench surface.

[0004] However, as the size of devices decreases, there are further requirements for the performance of the buffer layer. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of a buffer layer.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a mask structure on the substrate, the mask structure including an initial first mask layer, an initial second mask layer located on the initial first mask layer, and an initial third mask layer located on the initial second mask layer, the mask structure exposing a portion of the substrate surface; etching the substrate with the mask structure as a mask to form a first groove in the substrate; removing a portion of the initial second mask layer in a direction parallel to the substrate surface to form a second mask layer, and forming a second groove between adjacent initial first mask layers and initial third mask layers; removing the initial first mask layer from the sidewalls of the second groove to form a first mask layer, the first mask layer exposing a portion of the substrate surface adjacent to the first groove; forming a buffer layer on the substrate surface, the sidewall surface of the first groove, and the bottom surface exposed by the first mask layer.

[0007] Optionally, the process of removing part of the initial second mask layer includes a wet etching process, wherein the etching rate of the wet etching process on the initial second mask layer is greater than the etching rate of the initial first mask layer, and the etching rate of the wet etching process on the initial second mask layer is greater than the etching rate of the initial third mask layer.

[0008] Optionally, the etching solution of the wet etching process includes phosphoric acid.

[0009] Optionally, the initial first mask layer and the initial second mask layer are made of different materials, and the initial third mask layer and the initial second mask layer are made of different materials.

[0010] Optionally, the material of the initial first mask layer includes silicon oxide; the material of the initial second mask layer includes silicon nitride; and the material of the initial third mask layer includes silicon oxide or silicon oxynitride.

[0011] Optionally, while removing the initial first mask layer on the sidewall of the second groove, the method further includes: removing the initial third mask layer on the sidewall of the second groove to form a third mask layer.

[0012] Optionally, the process of removing the initial first mask layer and the initial third mask layer includes a wet etching process.

[0013] Optionally, the etching solution of the wet etching process includes hydrofluoric acid with a concentration of 49%.

[0014] Optionally, the thickness of the initial first mask layer is smaller than the thickness of the initial second mask layer, and the thickness of the initial first mask layer is smaller than the thickness of the initial third mask layer.

[0015] Optionally, the ratio of the thickness of the initial first mask layer, the thickness of the initial second mask layer, and the thickness of the initial third mask layer is in the range of 1:(8-10):(8-10).

[0016] Optionally, the buffer layer has a thickness ranging from 50 angstroms to 110 angstroms.

[0017] Optionally, the process of etching the substrate using the mask structure as a mask includes a dry etching process, and an etching rate of the substrate by the dry etching process is greater than an etching rate of the initial third mask layer.

[0018] Optionally, the process for forming the buffer layer includes an in-situ steam generation process or a furnace tube process.

[0019] Optionally, the material of the buffer layer includes silicon oxide.

[0020] Optionally, the method further includes: forming an initial isolation layer in the first groove and on the mask structure; planarizing the initial isolation layer and the third mask layer until the surface of the second mask layer is exposed, and forming an isolation layer in the first groove.

[0021] Optionally, the material of the initial isolation layer is the same as that of the first mask layer.

[0022] Optionally, the material of the initial isolation layer includes silicon oxide.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] The formation method of the present invention first removes the initial second mask layer to form a second mask layer, then removes the initial first mask layer on the sidewalls of the second groove to form a first mask layer, and forms a buffer layer on the substrate surface, the sidewall surfaces, and the bottom surface of the first groove exposed by the first mask layer. The buffer layer is continuously formed on the sidewall surfaces and bottom surfaces of the first groove, as well as the substrate surface adjacent to the first groove, so that the buffer layer on the substrate surface and the buffer layer on the sidewalls of the first groove are smoothly connected. The buffer layer at the top corner of the first groove has sufficient thickness and few sharp surfaces. After the isolation layer is subsequently formed in the first groove, the risk of leakage at the top corner of the first groove is less likely to occur.

[0025] Furthermore, an initial third mask layer is provided on the initial second mask layer, and the material of the initial second mask layer is different from that of the initial third mask layer. Therefore, the initial third mask layer can protect the surface of the initial second mask layer, so that the wet etching process only removes part of the initial second mask layer in a direction parallel to the substrate surface. The surface of the initial second mask layer will not be damaged, which is beneficial for the subsequent etching stop layer serving as the initial isolation layer.

[0026] Furthermore, the initial third mask layer protects the surface of the initial second mask layer from damage by the wet etching process, the surface of the second mask layer is relatively flat and smooth, and the thickness of the second mask layer is not lost. When the planarization of the initial isolation layer and the third mask layer stops at the surface of the second mask layer, the stop position of the planarization process is easy to control, and the height of the transition isolation layer is also easy to control, which is conducive to fine-tuning the control of each step in the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 and Figure 2 is a structural schematic diagram of a semiconductor structure forming process in one embodiment;

[0028] Figures 3 to 9 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the performance of the buffer layer needs to be improved.

[0030] Figure 1 and Figure 2 1 is a schematic structural diagram of a semiconductor structure forming process in one embodiment.

[0031] Please refer to Figure 1, providing a substrate 100; forming an initial protective layer (not shown) on the substrate 100; forming an initial hard mask layer (not shown) and a photoresist layer (not shown) located on the initial hard mask layer on the initial protective layer, the photoresist layer exposing a portion of the surface of the initial hard mask layer; etching the initial hard mask layer, the initial protective layer and the substrate 100 using the photoresist layer as a mask to form a groove 103 in the substrate 100, and forming a hard mask layer 102 and a protective layer 101; and laterally etching the hard mask layer 102 so that the hard mask layer 102 exposes a portion of the surface of the protective layer 101.

[0032] Please refer to Figure 2 A buffer layer 104 is formed on the sidewall and bottom surfaces of the groove 103; an isolation layer (not shown) is formed in the groove 103, and the isolation layer is located on the buffer layer 104. The buffer layer 104 is used to repair the surface condition of the groove 103 and prevent leakage.

[0033] During the formation of the semiconductor structure, the hard mask layer 102 is laterally etched so that the hard mask layer 102 exposes a portion of the surface of the protective layer 101. This is so that when the material forming the isolation layer is deposited in the groove 103, the space at the top of the groove 103 is larger, which facilitates the filling of the isolation layer material at the bottom of the groove 103. When forming the buffer layer 104, an in-situ water vapor generation process is used to generate a thinner buffer layer 104. Since the in-situ water vapor generation process only oxidizes the silicon material on the sidewall surface and the bottom surface of the groove 103, the material thickness at the vertex of the junction between the buffer layer 104 and the protective layer 101 is relatively thin ( Figure 2 The surface of the material layer is not smooth enough. After the isolation layer is formed in the groove 103, the corners of the isolation layer ( Figure 2 The middle area A) is prone to generate a strong electric field, which can easily lead to leakage problems.

[0034] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure. The method first removes an initial second mask layer to form a second mask layer, then removes the initial first mask layer on the sidewalls of the second groove to form a first mask layer. A buffer layer is formed on the substrate surface, the sidewall surfaces, and the bottom surface of the first groove exposed by the first mask layer. The buffer layer is continuously formed on the sidewall surfaces and bottom surfaces of the first groove, as well as on the substrate surface adjacent to the first groove. This ensures a smooth transition between the buffer layer on the substrate surface and the buffer layer on the sidewalls of the first groove. This ensures that the buffer layer at the top corners of the first groove has sufficient thickness and few sharp surfaces. This reduces the risk of leakage at the top corners of the first groove after an isolation layer is subsequently formed within the first groove.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 3 to 9 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0037] Please refer to Figure 3 , providing a substrate 200; forming a mask structure material layer on the substrate 200, the mask structure material layer including a first mask material layer 201, a second mask material layer 202 located on the first mask material layer 201, a third mask material layer 203 located on the second mask material layer 202, and a photoresist layer 220 located on the third mask material layer 203, wherein the photoresist layer 220 exposes a portion of the surface of the third mask material layer 203.

[0038] In this embodiment, the first mask material layer 201 and the second mask material layer 202 are made of different materials, and the third mask material layer 203 is made of different materials from the second mask material layer 202 .

[0039] The material of the first mask material layer 201 includes silicon oxide; the material of the second mask material layer 202 includes silicon nitride; and the material of the third mask material layer 203 includes silicon oxide or silicon oxynitride.

[0040] In this embodiment, the first mask material layer and the third mask material layer can be made of the same material.

[0041] In other embodiments, the materials of the first mask material layer and the third mask material layer may be different.

[0042] The thickness of the first mask material layer 201 is smaller than the thickness of the third mask material layer 203 , and the thickness of the first mask material layer 201 is smaller than the thickness of the second mask material layer 202 .

[0043] In this embodiment, the ratio of the thickness of the first mask material layer 201 , the thickness of the second mask material layer 202 , and the thickness of the third mask material layer 203 is in the range of 1:(8-10):(8-10).

[0044] In this embodiment, the substrate 200 is made of silicon.

[0045] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] Please refer to Figure 4 , using the photoresist layer 220 as a mask, the third mask material layer 203, the second mask material layer 202 and the first mask material layer 201 are etched to form a mask structure, wherein the mask structure includes an initial first mask layer 204, an initial second mask layer 205 located on the initial first mask layer 204, and an initial third mask layer 206 located on the initial second mask layer 205, and the mask structure exposes a portion of the surface of the substrate 200.

[0047] The process of etching the third mask material layer 203, the second mask material layer 202 and the first mask material layer 201 using the photoresist layer 220 as a mask includes a dry etching process. During the etching process of the third mask material layer 203, the second mask material layer 202 and the first mask material layer 201, the photoresist layer 220 is naturally consumed.

[0048] The initial first mask layer 204 is formed by etching the first mask material layer 201 , the initial second mask layer 205 is formed by etching the second mask material layer 202 , and the initial third mask layer 206 is formed by etching the third mask material layer 203 .

[0049] The initial first mask layer 204 and the initial second mask layer 205 are made of different materials. The initial first mask layer 204 and the initial second mask layer 205 are made of different materials.

[0050] Please continue to refer to Figure 4 , the substrate 200 is etched using the mask structure as a mask to form a first groove 221 in the substrate 200 .

[0051] The process of etching the substrate 200 using the mask structure as a mask includes a dry etching process. The etching rate of the substrate 200 by the dry etching process is greater than the etching rate of the initial third mask layer 206 .

[0052] Please refer to Figure 5 A portion of the initial second mask layer 205 is removed in a direction parallel to the surface of the substrate 200 to form a second mask layer 207 , and a second groove 208 is formed between the adjacent initial first mask layer 204 and the initial third mask layer 206 .

[0053] In this embodiment, the process of removing a portion of the initial second mask layer 205 includes a wet etching process. The wet etching process is isotropic and can etch the initial second mask layer 205 in a direction parallel to the surface of the substrate 200 .

[0054] The wet etching process has a higher etching rate for the initial second mask layer 205 than for the initial first mask layer 204 . The wet etching process has a higher etching rate for the initial second mask layer 205 than for the initial third mask layer 206 .

[0055] Since the initial first mask layer 204 and the initial second mask layer 205 are made of different materials, and the initial first mask layer 204 and the initial third mask layer 206 are made of different materials, the wet etching process has a large etching selectivity ratio for the initial first mask layer 204 and the initial third mask layer 206 .

[0056] In this embodiment, the etching solution of the wet etching process includes phosphoric acid.

[0057] The initial second mask layer 205 has an initial third mask layer 206, and the initial second mask layer 205 is made of a different material from the initial third mask layer 206. Therefore, the initial third mask layer 206 can protect the surface of the initial second mask layer 205, so that the wet etching process only removes a portion of the initial second mask layer 205 in a direction parallel to the surface of the substrate 200. The surface of the initial second mask layer 205 will not be damaged, which is beneficial for the subsequent etching stop layer as an initial isolation layer.

[0058] Please refer to Figure 6 The initial first mask layer 204 on the sidewall of the second groove 208 is removed to form a first mask layer 209 . The first mask layer 209 exposes a portion of the surface of the substrate 200 adjacent to the first groove 221 .

[0059] In this embodiment, the initial first mask layer 204 and the initial third mask layer 206 are made of the same material. When removing the initial first mask layer 204 from the sidewall of the second groove 208 , the process also includes: removing the initial third mask layer 206 from the sidewall of the second groove 208 to form a third mask layer 210 .

[0060] In this embodiment, the process of removing the initial first mask layer 204 and the initial third mask layer 206 includes a wet etching process.

[0061] In this embodiment, the etching solution of the wet etching process includes hydrofluoric acid with a concentration of 49%.

[0062] In other embodiments, the initial first mask layer and the initial third mask layer are made of different materials, and the initial first mask layer and the initial third mask layer on the sidewall of the second groove are removed in different process steps.

[0063] The first mask layer 209, the second mask layer 207 and the third mask layer 210 expose part of the surface of the substrate 200, and the top opening size of the first groove 221 is expanded. When a material layer forming an isolation layer is subsequently deposited in the first groove 221, the material of the isolation layer can easily reach the bottom of the first groove 221, so that the structure of the formed isolation layer is dense and the quality is good.

[0064] Please refer to Figure 7 A buffer layer 211 is formed on the surface of the substrate 200 exposed by the first mask layer 209 and the sidewall surfaces and bottom surface of the first groove 221 .

[0065] The buffer layer 104 can repair surface defects of the groove 103 and prevent leakage, and can also serve as a stress buffer between the subsequently formed isolation layer and the substrate 200 to avoid yield problems caused by uneven stress matching.

[0066] The process of forming the buffer layer 211 includes an in-situ steam generation process or a furnace tube process.

[0067] In this embodiment, the process for forming the buffer layer 211 includes an in-situ water vapor generation process. The buffer layer formed by the in-situ water vapor generation process has a dense structure and good quality.

[0068] In this embodiment, the material of the buffer layer 211 includes silicon oxide.

[0069] In this embodiment, the thickness of the buffer layer 211 is the same as the thickness of the first mask layer 209 .

[0070] In this embodiment, the thickness of the buffer layer 211 ranges from 50 angstroms to 110 angstroms.

[0071] In this embodiment, the material of the buffer layer 211 is the same as that of the first mask layer 209 .

[0072] Since the buffer layer 211 is formed on the side wall surface and the bottom surface of the first groove 221, and the surface of the substrate 200 adjacent to the first groove 221, the buffer layer 211 is continuously formed on the side wall surface and the bottom surface of the first groove 221, and the surface of the substrate 200 adjacent to the first groove 221, so that the buffer layer 211 located on the surface of the substrate 200 is smoothly connected with the buffer layer 211 on the side wall of the first groove 221, so that the buffer layer 211 at the top corner of the first groove 221 has sufficient thickness and few sharp surfaces. After the isolation layer is subsequently formed in the first groove 221, the risk of leakage is less likely to occur at the top corner of the first groove 221.

[0073] Please refer to Figure 8 , forming an initial isolation layer (not shown) in the first groove 221 and on the mask structure; planarizing the initial isolation layer and the third mask layer 210 until the surface of the second mask layer 207 is exposed, and forming an isolation layer 212 in the first groove 221.

[0074] In this embodiment, the initial isolation layer and the first mask layer 209 are made of the same material, and the initial isolation layer and the third mask layer 210 are made of the same material.

[0075] The initial isolation layer and the third mask layer 210 are made of the same material. Therefore, during the process of planarizing the initial isolation layer, the third mask layer 210 can be planarized at the same time and stops at the surface of the second mask layer 207 .

[0076] In this embodiment, the material of the initial isolation layer includes silicon oxide.

[0077] In this embodiment, the process of planarizing the initial isolation layer and the third mask layer 210 includes a chemical mechanical polishing process.

[0078] Since the initial third mask layer 206 protects the surface of the initial second mask layer 205 from damage by the wet etching process, the surface of the second mask layer 207 is relatively flat and smooth, and the thickness of the second mask layer 207 is not lost. When the initial isolation layer and the third mask layer 210 are planarized and stopped on the surface of the second mask layer 207, the stop position of the planarization process is easy to control, and the height of the isolation layer 212 is also easy to control, which is conducive to fine-tuning the control of each step in the process.

[0079] In this embodiment, the height of the isolation layer 212 is higher than the surface of the substrate 200 .

[0080] Please refer to Figure 9 , remove the second mask layer 207.

[0081] The process of removing the second mask layer 207 includes a wet etching process. In this embodiment, the process further includes: removing the first mask layer 209 and the isolation layer 212 above the surface of the substrate 200; after removing the first mask layer 209 and the isolation layer 212 above the surface of the substrate 200, forming a gate oxide layer on the surface of the substrate; and forming a gate layer on the surface of the gate oxide layer.

[0082] The initial isolation layer is made of the same material as the first mask layer 209 , so that the first mask layer 209 and the isolation layer 212 above the surface of the substrate 200 can be removed simultaneously.

[0083] In this embodiment, the process of removing the first mask layer 209 and the isolation layer 212 above the surface of the substrate 200 includes a wet etching process.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a mask structure on a substrate, the mask structure comprising an initial first mask layer, an initial second mask layer located on the initial first mask layer, and an initial third mask layer located on the initial second mask layer, wherein the mask structure exposes a portion of the substrate surface; etching the substrate using the mask structure as a mask to form a first groove in the substrate; removing a portion of the initial second mask layer in a direction parallel to the substrate surface to form a second mask layer, and forming a second groove between adjacent initial first mask layers and initial third mask layers; removing the initial first mask layer from the sidewall of the second groove to form a first mask layer, wherein the first mask layer exposes a portion of the substrate surface adjacent to the first groove; A buffer layer is formed on the substrate surface, the sidewall surface and the bottom surface of the first groove exposed by the first mask layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing part of the initial second mask layer includes a wet etching process, wherein the etching rate of the initial second mask layer by the wet etching process is greater than the etching rate of the initial first mask layer, and the etching rate of the initial second mask layer by the wet etching process is greater than the etching rate of the initial third mask layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etching solution of the wet etching process includes phosphoric acid.

4. The method for forming a semiconductor structure according to claim 1, wherein: The initial first mask layer and the initial second mask layer are made of different materials, and the initial third mask layer and the initial second mask layer are made of different materials.

5. The method for forming a semiconductor structure according to claim 4, wherein: The material of the initial first mask layer includes silicon oxide; the material of the initial second mask layer includes silicon nitride; and the material of the initial third mask layer includes silicon oxide or silicon oxynitride.

6. The method for forming a semiconductor structure according to claim 4, wherein: While removing the initial first mask layer on the sidewall of the second groove, the method further includes: removing the initial third mask layer on the sidewall of the second groove to form a third mask layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the initial first mask layer and the initial third mask layer includes a wet etching process.

8. The method for forming a semiconductor structure according to claim 7, wherein: The etching solution of the wet etching process includes hydrofluoric acid with a concentration of 49%.

9. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the initial first mask layer is smaller than the thickness of the initial second mask layer, and the thickness of the initial first mask layer is smaller than the thickness of the initial third mask layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The ratio of the thickness of the initial first mask layer, the thickness of the initial second mask layer, and the thickness of the initial third mask layer is in the range of 1:(8-10):(8-10).

11. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the buffer layer ranges from 50 angstroms to 110 angstroms.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the substrate using the mask structure as a mask includes a dry etching process, and the etching rate of the substrate by the dry etching process is greater than the etching rate of the initial third mask layer.

13. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the buffer layer includes an in-situ steam generation process or a furnace tube process.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the buffer layer includes silicon oxide.

15. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming an initial isolation layer in the first groove and on the mask structure; The initial isolation layer and the third mask layer are planarized until the surface of the second mask layer is exposed, forming an isolation layer in the first groove; and removing the second mask layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The material of the initial isolation layer is the same as that of the first mask layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The material of the initial isolation layer includes silicon oxide.

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