Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The application provides a semiconductor structure, comprising: a substrate comprising a plurality of device regions; a channel layer on the substrate and a first electrical interconnection layer, a second electrical interconnection layer and a third electrical interconnection layer overlapping the channel layer, the channel layer comprising a channel structure on each device region, the first electrical interconnection layer comprising a drain electrode on each device region, the second electrical interconnection layer comprising a source electrode on each device region, the third electrical interconnection layer comprising a gate electrode on each device region, each channel structure being electrically connected to the drain electrode and the source electrode, and each channel structure being separated from the gate electrode; an electrolyte layer on each device region, the electrolyte layer being on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode and the surface of the gate electrode, and the electrolyte layers of different device regions being isolated from each other. The technical scheme provided by the application solves the problem of crosstalk in a synaptic transistor array.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular to a semiconductor structure and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] Artificial synapse devices have great potential in intelligent perception, machine learning, and brain-computer interface fields, and are key components for realizing neuromorphic computing. However, with the rapid growth of electronic data in the big data era, there is an urgent need for computing technology that can provide faster computing speed and lower energy consumption. Therefore, it is particularly important to prepare artificial synapse arrays in neuromorphic computing to construct highly parallel processing and adaptive learning neural networks. Current research mainly focuses on single artificial synapse devices, and it is still challenging to prepare high-density artificial synapse arrays with excellent electrical performance and good uniformity. Among various synaptic devices, electrolyte-gated synaptic transistors (EGT) are a favorable choice for artificial synapse array units due to their high specific capacitance (~1-10 μF / cm2), environmental compatibility, and low operating voltage (<1 V). Electrolyte-gated synaptic transistors (EGT) play an important role in realizing neuromorphic devices or architectures due to their low operating voltage, high specific capacitance, and environmental compatibility.

[0003] In biological nervous systems, synapses are important connection points for signal transmission between neurons. Synaptic transistors are artificial neuron devices that mimic synaptic connections between biological neurons. The main feature of synaptic transistors is adjustable multi-level conductance, which simulates the adjustment of synaptic weights in biology based on the adjustment of conductance, similar to synaptic plasticity in biological synapses. This means that it can adjust the strength of the connection (i.e., the size of the conductance) according to the intensity and frequency of the input signal, thereby simulating learning and memory functions. It plays a role in the fields of artificial intelligence and neural networks.

[0004] In synaptic transistors, electrolyte material is an electronically insulating, ionically conductive material. Based on the double-layer modulation effect formed at the electrolyte / semiconductor channel interface and the electrolyte / gate interface, during operation of the synaptic transistor, the "write" operation is on the gate, and the "read" operation is on the source-drain covered by the semiconductor channel. By applying a gate voltage, ions in the electrolyte are induced to migrate, thereby modulating the conductance.

[0005] Synaptic transistor array is widely used for realizing spatial direction recognition, sound positioning and spatial summation due to its double layer modulation effect of multi-gate / single channel and single gate / multi-channel. In the manufacturing process of the synaptic transistor array based on electrolyte synaptic transistor, the electrolyte is uniformly coated on the surface of the array device. The traditional electrolyte preparation method ignores the influence of the spatial correlation function of the electrolyte on the weight update of the array device, thereby causing serious crosstalk problem. When a gate voltage is applied to a device in the synaptic transistor array prepared by the preparation method, the conductivity of the surrounding devices will change, and with the continuous expansion of the device density in the array, the crosstalk problem becomes more and more obvious. SUMMARY

[0006] The technical problem solved by the present application is the serious crosstalk problem caused by the spatial correlation function of the electrolyte, and a semiconductor structure and a manufacturing method thereof are provided to solve the crosstalk problem in the synaptic transistor array.

[0007] To solve the above technical problem, the embodiment of the present application provides a semiconductor structure, comprising:

[0008] a substrate comprising a plurality of device regions;

[0009] a channel layer on the substrate, and a first electrical interconnection layer, a second electrical interconnection layer and a third electrical interconnection layer overlapping the channel layer, the channel layer comprising a channel structure on each of the device regions, the first electrical interconnection layer comprising a drain electrode on each of the device regions, the second electrical interconnection layer comprising a source electrode on each of the device regions, and the third electrical interconnection layer comprising a gate electrode on each of the device regions, each of the channel structures being electrically connected to the drain electrode and the source electrode, and each of the channel structures being mutually separated from the gate electrode;

[0010] an electrolyte layer on each of the device regions, the electrolyte layer being on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode and the surface of the gate electrode, and the electrolyte layers of different device regions being mutually isolated.

[0011] Optionally, each of the drain electrodes is on the substrate, each of the source electrodes and each of the gate electrodes is on the drain electrode, and each of the source electrodes and each of the gate electrodes is mutually separated from the gate electrode, and each of the channel structures is on the corresponding source electrode and gate electrode.

[0012] Optionally, the semiconductor structure further comprises an insulation layer and a protection layer, the insulation layer is located between the drain electrode and the gate electrode, the source electrode and the channel structure, and exposes the surface of the drain electrode, and the protection layer is located on the insulation layer, the gate electrode, the source electrode and the channel structure, and exposes the surfaces of the drain electrode, the gate electrode, the source electrode and the channel structure.

[0013] The embodiment of the present application further provides a manufacturing method of a semiconductor structure, comprising:

[0014] A substrate is provided, and the substrate comprises a plurality of device regions.

[0015] A channel layer, a first electrically interconnected layer, a second electrically interconnected layer and a third electrically interconnected layer are formed on the substrate, the channel layer comprises channel structures located on each of the device regions, the first electrically interconnected layer comprises drain electrodes located on each of the device regions, the second electrically interconnected layer comprises source electrodes located on each of the device regions, and the third electrically interconnected layer comprises gate electrodes located on each of the device regions, each of the channel structures is electrically connected with the drain electrode and the source electrode, and each of the channel structures is separated from the gate electrode.

[0016] An electrolyte layer is formed on each of the device regions, the electrolyte layer is located on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode and the surface of the gate electrode, and the electrolyte layers of different device regions are separated from each other.

[0017] Optionally, the method for forming the electrolyte layer on each of the device regions comprises:

[0018] A photosensitive electrolyte material is deposited on the substrate.

[0019] After the photosensitive electrolyte material is formed, annealing is performed on the photosensitive electrolyte material to obtain a homogeneous photosensitive electrolyte film.

[0020] A patterned mask is used to perform photolithography on the homogeneous photosensitive electrolyte film to form the electrolyte layer on each of the device regions.

[0021] Optionally, the temperature for annealing the photosensitive electrolyte material is 40-90 ℃.

[0022] Optionally, the photosensitive electrolyte material is a mixed solution of polyvinyl alcohol and diazonium photosensitizer, and an electrolyte material mixed with chitosan polyamine salt aqueous solution at a ratio.

[0023] Optionally, in the mixed solution of polyvinyl alcohol and diazonium photosensitizer, the mixing ratio of polyvinyl alcohol and diazonium photosensitizer is 100:1 in mass ratio; and in the aqueous solution of chitosan polyamine salt, the concentration of chitosan polyamine salt is 5wt%-10wt%.

[0024] Optionally, when the homogeneous photosensitive electrolyte thin film is subjected to photoetching by using a patterned mask, a developing solution of NaCl salt solution is selected; and the concentration of the NaCl salt solution is 1wt%-10wt%.

[0025] Optionally, the photosensitive electrolyte material further comprises a biological electrolyte material or an organic electrolyte material.

[0026] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0027] In the semiconductor structure of the technical scheme, by manufacturing, on each device region of a substrate, a plurality of channel layers including a channel structure located on each device region, and a first electrically interconnected layer of a drain electrode overlapping the channel layer, a second electrically interconnected layer of a source electrode located on each device region, and a third electrically interconnected layer of a gate electrode located on each device region, and manufacturing an electrolyte layer isolated from each other on each device region, the electrolyte spatial correlation function is effectively avoided, the phenomenon that the conductivity of surrounding devices also changes due to the application of a gate voltage to a device in a certain device region is avoided, the device crosstalk problem caused by the electrolyte spatial correlation function is successfully solved, and the expandability of an array in the semiconductor structure, and the large density and high uniformity configuration of devices in the array are realized.

[0028] In the manufacturing method of the semiconductor structure of the technical scheme, by manufacturing the electrolyte layer isolated from each other on different device regions, the phenomenon that the conductivity of surrounding devices also changes due to the application of a gate voltage to a device in a certain device region is avoided, the device crosstalk problem caused by the electrolyte spatial correlation function is successfully solved, and the expandability of an array in the semiconductor structure, and the large density and high uniformity configuration of devices in the array are realized. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figures 1 to 14 is a structure schematic diagram of different process stages of a semiconductor structure prepared according to the manufacturing method of the semiconductor structure provided by an embodiment. DETAILED DESCRIPTION

[0030] As described in the background, there is a serious crosstalk problem in a conventional synaptic transistor array, and the higher the density of the device array is, the more serious the crosstalk problem is.

[0031] So far, EGT arrays have tried to achieve high electrical performance and high-density fabrication. For example, high-density integration of EGTs (electrolyte-gate transistors) has been developed, and 100x100 EGTs have been integrated on a 2.5x2.5cm 2 glass substrate with a unit density of up to 1600 devices / cm 2 . In addition, a 20x20 EGT array has been designed with indium gallium zinc oxide as the semiconductor channel and C2F6LiNO4S2-doped polyacrylonitrile as the electrolyte, which has the characteristics of a large adjustable range of electrical conductivity, low energy consumption (6.984fJ) for read-write operation, good repeatability, and quasi-linear update.

[0032] However, in the current fabrication process of electrolyte-based synaptic transistor arrays, the electrolyte is uniformly coated on the surface of the array devices. Since the electrolyte is in flow and not isolated on the surface of different devices, applying a gate voltage to one device in the array will cause the conductivity of the surrounding devices to change, resulting in a serious crosstalk problem. Moreover, the higher the density of the device array, the more serious the crosstalk problem.

[0033] To solve the above problems, the embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising:

[0034] providing a substrate, the substrate comprising a plurality of device regions.

[0035] forming a channel layer and a first, second and third electrically interconnected layer overlapping the channel layer on the substrate, the channel layer comprising a channel structure on each of the device regions, the first electrically interconnected layer comprising a drain electrode on each of the device regions, the second electrically interconnected layer comprising a source electrode on each of the device regions, and the third electrically interconnected layer comprising a gate electrode on each of the device regions, each of the channel structures being electrically connected to the drain and source electrodes, and each of the channel structures being mutually separated from the gate electrode.

[0036] forming an electrolyte layer on each of the device regions, the electrolyte layer being located on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode, and the surface of the gate electrode, and the electrolyte layers of different device regions being mutually isolated.

[0037] Herein the surface means the direction, i.e. the electrolyte layer is located above the drain electrode, above the channel structure, the surface of the source electrode and above the gate electrode, not the meaning of direct contact; the electrolyte actually only contacts the surface of the channel and the surface of the gate, and has no contact with the source electrode and the drain electrode, because the channel structure has covered the source electrode and the drain electrode, thus the electrolyte cannot contact the source electrode and the drain electrode.

[0038] By making several channel layers in each device area of the substrate, and the first, second and third electrically interconnected layers overlapping the channel layers, and making the electrolyte layers isolated from each other on each device area, the influence on the conductivity of the surrounding other devices caused by applying the gate voltage to the device of a certain device area in the semiconductor structure is avoided, thus the serious crosstalk problem between different device areas is avoided, thus the device performance of the semiconductor structure is improved; and further the expansion of the density of the device array in the semiconductor structure is possible.

[0039] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0040] Figures 1 to 14 is the structural schematic diagram of different process stages of the semiconductor structure prepared according to the manufacturing method of the semiconductor structure of the embodiments of the present application.

[0041] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 the cross-sectional view along the direction of aa'.

[0042] The substrate 10 is provided, which includes several device areas. The device areas are defined for convenience of description.

[0043] In some specific examples, the substrate 10 is a glass substrate or a polyimide substrate.

[0044] When the substrate 10 is a glass substrate, a clean glass substrate is selected as the substrate 10.

[0045] When the substrate 10 is a polyimide substrate, the preparation method of the polyimide substrate includes: first, a clean glass substrate is selected, and polyimide solvent is spin-coated on the glass substrate; second, the glass substrate with spin-coated polyimide reagent is treated according to the set annealing temperature; then, after the annealing treatment, a buffer layer composed of silicon nitride and silicon dioxide is prepared on the substrate by plasma enhanced chemical vapor deposition process, to obtain a flexible polyimide substrate.

[0046] The annealing temperature is set at 430℃.

[0047] A first electrical interconnection layer 101 is formed on the substrate 10.

[0048] The method of forming the first electrical interconnection layer 101 includes: first, sputtering the first electrical interconnection layer 101 material on the substrate by sputtering process. In some specific examples, the first electrical interconnection layer 101 material uses a composite electrode of molybdenum and indium tin oxide, aluminum and indium tin oxide, or titanium and indium tin oxide. Specifically, the sputtering sequence of the first electrical interconnection layer 101 material is: sputtering molybdenum or aluminum or titanium first, and then sputtering indium tin oxide.

[0049] After sputtering the first electrical interconnection layer 101 material on the substrate, the drain electrode plate, the drain electrode conductive connection structure, and the drain electrode pad are obtained by mask and wet etching technology, that is, the first electrical interconnection layer 101 is prepared. The processes and technologies involved in the step of obtaining the patterned electrode are all known to those skilled in the art, and will not be described here.

[0050] The first electrical interconnection layer includes: a drain electrode 1012, a drain electrode conductive connection structure 1013, and a drain electrode pad 1011. The drain electrode conductive connection structure 1013 is used to electrically connect a plurality of drain electrodes 1012, and the drain electrode pad 1011 is used to lead out the drain electrode 1012.

[0051] A plurality of drain electrodes 1012 are arranged in an array on the substrate, and the number thereof is not limited.

[0052] In a typical example, the semiconductor structure includes an array of 9 drain electrodes 1012, i.e. a 3x3 array is formed. The 3 drain electrodes 1012 along one of the array arrangement directions are electrically connected by a drain electrode conductive connection structure 1013, and the ends of the drain electrode conductive connection structure 1013 are connected to the drain electrode pad 1011.

[0053] Please refer to Figure 3 and Figure 4 , Figure 4 for Figure 3 the cross-sectional view along the aa' direction.

[0054] After forming the first electrical interconnection layer, an insulating material layer 20 is formed on the substrate 10 and the first electrical interconnection layer 101.

[0055] The insulating material layer 20 is prepared on the substrate 10 and the first electrical interconnection layer 101 by plasma-enhanced chemical vapor deposition process when forming the insulating material layer 20. In some specific examples, the material of the insulating material layer 20 is at least one of silicon nitride and silicon oxide.

[0056] The thickness of the insulating material layer 20 is 100-300 nm.

[0057] After forming the insulating material layer 20, the second electric interconnection layer 202 and the third electric interconnection layer 201 are formed on the insulating material layer 20.

[0058] The second electric interconnection layer 202 includes source electrodes 2022, source electrode conductive connection structures 2023 for electrically connecting a plurality of source electrodes 2022, and source electrode pads 2021 for leading out the source electrodes 2022. The third electric interconnection layer 201 includes gate electrodes 2013, gate electrode conductive connection structures 2012 for electrically connecting a plurality of gate electrodes 2013, and gate electrode pads 2011 for leading out the gate electrodes 2013. In each device region, each source electrode 2022 and each gate electrode 2013 correspond to a drain electrode, thereby serving as an electrode of a corresponding channel structure.

[0059] The second electric interconnection layer 202 and the third electric interconnection layer 201 are formed by a sputtering process.

[0060] Please refer to Figure 5 and Figure 6 , Figure 6 are Figure 5 are cross-sectional views along the direction aa' in FIG.

[0061] After forming the second electric interconnection layer 202 and the third electric interconnection layer 201, the insulating material layer 20 above the drain electrode and the drain electrode pad is etched using a mask plate, so that the insulating layer 21 is formed by exposing the surface of the insulating layer 21 to the drain electrode pad and the drain electrode.

[0062] Please refer to Figure 7 and Figure 8 , Figure 8 are Figure 7 are cross-sectional views along the direction aa' in FIG.

[0063] After forming the insulating layer 21, a channel layer is formed on the source electrodes 2022 and the gate electrodes 2013. The channel layer includes channel structures 203 on each device region, each channel structure 203 is electrically connected to the drain electrode and the source electrode 2022, and each channel structure 203 is separated from the gate electrode 2013. One corresponding transistor is formed in each device region on the substrate, and a plurality of transistors form a transistor array. In a typical example, the transistor array is a synaptic transistor array.

[0064] A channel layer is formed on the source electrode and the gate electrode 2013 by a sputtering process and an etching process. The etching process is similar to the aforementioned patterning process, and thus is not described herein.

[0065] In some embodiments, the channel layer is made of at least one of ZnO, InZnO, or InGaZnO.

[0066] Please refer to Figure 9 and Figure 10 , Figure 10 is Figure 9 a cross-sectional view along aa' direction in

[0067] After the channel layer is formed, a protective layer 30 is formed. The protective layer 30 is located on the insulating layer 21, the gate electrode 2013, the source electrode, and the channel structure 203, and exposes the surfaces of the gate electrode 2013, the source electrode, and the channel structure 203.

[0068] The method of forming the protective layer 30 includes forming a protective material layer on the insulating layer 21, the second electrically conductive layer, the third electrically conductive layer, and the channel layer. The protective material layer on the drain electrode, the gate electrode 2013, the source electrode, the drain electrode pad 1011, the gate electrode pad 2011, the source electrode pad 2021, and the channel structure 203 is etched to form the protective layer 30.

[0069] The protective material layer is formed by a plasma-enhanced chemical vapor deposition process.

[0070] The thickness of the protective material layer is 100-300 nm.

[0071] In some embodiments, the protective material layer is a structure made of at least one of silicon nitride and silicon oxide.

[0072] After the protective layer is formed, an electrolyte layer is formed on each of the device regions. The electrolyte layer is located on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode, and the surface of the gate electrode, and is isolated from the electrolyte layers of other device regions. The process of forming the electrolyte layer is shown in Figures 11 to 14 .

[0073] The present application realizes the fabrication of the electrolyte layer by a full photolithography process.

[0074] The method of forming the electrolyte layer on each of the device regions is described in detail below with reference to the accompanying drawings:

[0075] Please refer to Figure 11 and Figure 12 , Figure 12 isFigure 11 Figure 2 is a cross-sectional view along the direction aa' of Figure 1.

[0076] A photosensitive electrolyte material 40 is deposited on the substrate.

[0077] In one embodiment, the photosensitive electrolyte material 40 is prepared by a spin-coating process.

[0078] In one embodiment, the photosensitive electrolyte material 40 is a mixed solution of polyvinyl alcohol and diazonium photosensitizer, mixed with an aqueous solution of chitosan polyamine salt in equal proportions.

[0079] In one embodiment, the mixed solution of polyvinyl alcohol and diazonium photosensitizer has a mixing ratio of polyvinyl alcohol to diazonium photosensitizer of 100:1 (by weight), and the aqueous solution of chitosan polyamine salt has a concentration of 5wt% to 10wt% of chitosan polyamine salt.

[0080] The preparation process of the photosensitive electrolyte material includes: preparing an aqueous solution of chitosan polyamine salt with a solubility of 5wt% to 10wt%. Polyvinyl alcohol (PVA) particles are dissolved in deionized water to obtain an aqueous solution of polyvinyl alcohol with a concentration of 5wt% to 10wt%. Then, the aqueous solution of polyvinyl alcohol with a concentration of 5wt% to 10wt% is mixed with diazonium photosensitizer (DS) in a mass ratio of 100:1 to obtain a PVA / DS solution. Then, the mixed solution of polyvinyl alcohol and diazonium photosensitizer is mixed with the aqueous solution of chitosan polyamine salt in equal proportions to obtain the photosensitive electrolyte material.

[0081] In one embodiment, the photosensitive electrolyte material 40 includes the above-mentioned electrolyte material which is a mixed solution of polyvinyl alcohol and diazonium photosensitizer, mixed with an aqueous solution of chitosan polyamine salt in equal proportions.

[0082] In other embodiments of the present application, the photosensitive electrolyte material 40 further includes a biological electrolyte material or an organic electrolyte material.

[0083] After the photosensitive electrolyte material 40 is formed, the photosensitive electrolyte material is annealed to obtain a homogeneous photosensitive electrolyte film.

[0084] In one embodiment, the temperature for annealing the photosensitive electrolyte material is 40°C to 90°C.

[0085] Please refer to Figure 13 and Figure 14 , Figure 14 is Figure 13 Figure 2 is a cross-sectional view along the direction aa' of Figure 1.

[0086] After the annealing forms the homogeneous photosensitive electrolyte thin film, the homogeneous photosensitive electrolyte thin film is photoetched by using a patterned mask, and the electrolyte layer 401 is formed on each device area. In a typical example, the homogeneous photosensitive electrolyte thin film is photoetched under the environment of ultraviolet light irradiation.

[0087] When the homogeneous photosensitive electrolyte thin film is photoetched by using a patterned mask, the developing solution selected is a NaCl salt solution; the concentration of the NaCl salt solution is 1wt%-10wt%.

[0088] The experimental results show that the semiconductor structure inner array prepared after the photoetching of the photosensitive electrolyte material has excellent electrical properties, indicating that the full photoetching patterned electrolyte layer has satisfactory large-scale uniformity. In particular, the prepared synaptic transistor array successfully simulates typical neural morphological characteristics, including short-term and long-term plasticity and double-pulse facilitation. Moreover, the simulation results show that the device has good recognition accuracy for neural morphological calculation. A reliable strategy is established for manufacturing scalable, repeatable and stable synaptic transistor arrays.

[0089] In summary, the photosensitive electrolyte material is reasonably configured, and the photosensitive electrolyte material is spin-coated on the substrate, the homogeneous electrolyte thin film is photoetched, the exposed areas isolated from each other are formed in each device area, then the exposed areas in each device area are exposed by using the developing solution configured above, and finally a plurality of electrolyte layers isolated from each other are formed in each device area. It can be seen that the patterned preparation of the homogeneous electrolyte thin film is realized by full photoetching in the present application, the problem of mutual influence and cross talk between the conductivities of devices in different device areas is solved, and the device performance of the semiconductor structure is improved. Moreover, the problem of cross talk in the synaptic transistor caused by the electrolyte layer is solved, so that the further expansion of the density of the device array in the semiconductor structure becomes possible.

[0090] The following will describe a semiconductor structure according to an embodiment of the present application in detail.

[0091] Please refer to Figure 13 and Figure 14 , the semiconductor structure comprises a substrate 10 comprising a plurality of device areas.

[0092] Channel layers located on the substrate 10 and first, second and third electrically interconnected layers 101, 202 and 201 overlapping the channel layers, the channel layers comprising channel structures 203 located on each of the device regions, the first electrically interconnected layers 101 comprising drain electrodes located on each of the device regions, the second electrically interconnected layers 202 comprising source electrodes located on each of the device regions, and the third electrically interconnected layers 201 comprising gate electrodes located on each of the device regions, each of the channel structures 203 being electrically connected to the drain and source electrodes, and each of the channel structures 203 being mutually separated from the gate electrodes.

[0093] Each of the drain electrodes is located on the substrate 10, each of the source electrodes and each of the gate electrodes being located on the drain electrodes, and each of the source electrodes and each of the gate electrodes being mutually separated from the gate electrodes, and each of the channel structures being located on the corresponding source electrodes and gate electrodes.

[0094] The semiconductor structure further comprises an insulating layer 21 located between the drain electrodes and the gate electrodes, the source electrodes and the channel structures 203, and exposing surfaces of the drain electrodes, and a protective layer 30 located on the insulating layer 30, the gate electrodes, the source electrodes and the channel structures 203, and exposing surfaces of the drain electrodes, the gate electrodes, the source electrodes and the channel structures 203. An electrolyte layer 401 located on each of the device regions, the electrolyte layer 401 being located on the surfaces of the drain electrodes, the surfaces of the channel structures 203, the surfaces of the source electrodes and the surfaces of the gate electrodes, and the electrolyte layers 203 of different device regions being mutually separated.

[0095] In summary, the semiconductor structure provided by the present application solves the problem of mutual influence and crosstalk between devices in different device regions by forming a plurality of mutually separated electrolyte layers in different device regions, and improves the device performance of the semiconductor structure, and further makes it possible to further expand the density of the device array in the semiconductor structure.

[0096] Although the present application has been disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes several device regions; The substrate includes a channel layer and a first electrical interconnect layer, a second electrical interconnect layer, and a third electrical interconnect layer overlapping the channel layer. The channel layer includes a channel structure located on each of the device regions. The first electrical interconnect layer includes a drain electrode located on each of the device regions. The second electrical interconnect layer includes a source electrode located on each of the device regions. The third electrical interconnect layer includes a gate electrode located on each of the device regions. Each channel structure is electrically connected to the drain electrode and the source electrode, and each channel structure is separate from the gate electrode. An electrolyte layer is located on each of the device regions, the electrolyte layer being located on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode, and the surface of the gate electrode, and the electrolyte layers of different device regions are isolated from each other.

2. The semiconductor structure as described in claim 1, characterized in that, Each of the drain electrodes is located on the substrate; each of the source electrodes and each of the gate electrodes are located on the drain electrodes, and each of the source electrodes and each of the gate electrodes are separate from each other; each of the channel structures is located on the corresponding source electrodes and each of the gate electrodes.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: An insulating layer and a protective layer are provided, wherein the insulating layer is located between the drain electrode and the gate electrode, the source electrode and the channel structure, and exposes the surface of the drain electrode, and the protective layer is located on the insulating layer, the gate electrode, the source electrode and the channel structure, and exposes the surfaces of the drain electrode, the gate electrode, the source electrode and the channel structure.

4. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of device regions; A channel layer and a first electrical interconnect layer, a second electrical interconnect layer, and a third electrical interconnect layer overlapping the channel layer are formed on the substrate. The channel layer includes a channel structure located on each of the device regions. The first electrical interconnect layer includes a drain electrode located on each of the device regions. The second electrical interconnect layer includes a source electrode located on each of the device regions. The third electrical interconnect layer includes a gate electrode located on each of the device regions. Each channel structure is electrically connected to the drain electrode and the source electrode, and each channel structure is separate from the gate electrode. An electrolyte layer is formed on each of the device regions, the electrolyte layer being located on the surface of the drain electrode, the surface of the channel structure, the surface of the source electrode, and the surface of the gate electrode, and the electrolyte layers of different device regions are isolated from each other.

5. The method for fabricating a semiconductor structure as described in claim 4, characterized in that, The method for forming an electrolyte layer on each of the device regions includes: A photosensitive electrolyte material is deposited on the substrate; After forming the photosensitive electrolyte material, the photosensitive electrolyte material is annealed to obtain a homogeneous photosensitive electrolyte film; Using a patterned mask, the homogeneous photosensitive electrolyte film is photolithographically etched to form an electrolyte layer on each of the device regions.

6. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, The annealing temperature for the photosensitive electrolyte material is 40℃~90℃.

7. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, The photosensitive electrolyte material is a mixture of polyvinyl alcohol and diazo photosensitizer, and an electrolyte material mixed in equal proportion with an aqueous solution of chitosan polyamine salt.

8. The method for fabricating a semiconductor structure as described in claim 7, characterized in that, In the mixed solution of polyvinyl alcohol and diazo photosensitizer, the mixing ratio of polyvinyl alcohol to diazo photosensitizer is 100:1 (by weight); in the aqueous solution of chitosan polyamine salt, the concentration of chitosan polyamine salt is: 5wt% to 10wt%.

9. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, When performing photolithography on the homogeneous photosensitive electrolyte film using a patterned mask, the developing solution selected is a NaCl salt solution; The concentration of the NaCl salt solution is 1 wt% to 10 wt%.

10. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, The photosensitive electrolyte material also includes: bioelectrolyte material or organic electrolyte material.

Images