A semiconductor device with ESD protection structure and preparation method thereof

Abstract

The present application provides a semiconductor device with an ESD protection structure and a preparation method thereof, comprising a substrate, a source metal, a gate metal lead and an ESD protection structure, wherein the substrate comprises a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region; the source metal is located in the source region; the gate metal lead is located in the gate region; the ESD protection structure is located in the ESD region, and the ESD protection structure comprises gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon, and the ESD polysilicon, ESD gate polysilicon and ESD protection structure are provided. The SD source polysilicon is located on the gate oxide, the extension direction of the ESD polysilicon is the same as the extension direction of the gate metal lead and has a parallel PN structure, the ESD gate polysilicon is connected to the ESD polysilicon and is respectively located on the side of the ESD polysilicon close to the source region and the gate region, the ESD source polysilicon and the ESD gate polysilicon are spaced apart and connected to the side of the ESD polysilicon close to the source region, the ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead to improve the ESD protection performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device with an ESD protection structure and a preparation method thereof. Background Art

[0002] Electrostatic discharge (ESD) is the transfer of static charge between two objects of different static types caused by direct contact or electrostatic field induction. Static electricity is a very common phenomenon. We carry static voltage on our bodies and around us. For example, chemical fiber clothing, as well as people's walking and friction, will generate strong static electricity. The voltage of this static electricity is as high as thousands of volts, which is fatal to most semiconductors and integrated circuits. As we all know, most substances are composed of atoms and protons. When a substance gains or loses electrons, its electrical balance will change and become an object with positive / negative charge. Contact pressure, friction coefficient, separation rate, etc. are important factors affecting the accumulation of charge. Static charge continues to accumulate until the effect of the charge disappears, the charge is released, or it reaches a strength sufficient to break through the surrounding material. When the medium is broken down, the electrostatic charge will quickly enter a state of equilibrium. This rapid neutralization of charge is called electrostatic discharge. Due to the rapid discharge of voltage on a very small resistor, the discharge current will be very large, which may exceed 20 amperes. If this discharge is carried out through power semiconductor devices or other integrated circuits, such a large current will cause serious damage to the device or circuit.

[0003] Therefore, in order to prevent electrostatic discharge of semiconductor devices, an ESD protection structure is usually set inside the device. However, due to design defects, the existing ESD protection structure has poor ESD antistatic performance, causing damage to the film layer of the device, thereby affecting the performance of the semiconductor device. Summary of the invention

[0004] In view of this, the present application provides a semiconductor device with an ESD protection structure and a preparation method thereof to improve the ESD protection performance.

[0005] The present application provides a semiconductor device with an ESD protection structure, comprising:

[0006] A substrate, the substrate having a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region;

[0007] A source metal, located on the source region of the substrate;

[0008] A gate metal lead, located on the gate region of the substrate;

[0009] An ESD protection structure is arranged on the ESD area of ​​the substrate, and the ESD protection structure includes gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon. The ESD polysilicon is a parallel PN structure. The ESD polysilicon, the ESD gate polysilicon and the ESD source polysilicon are all located on the gate oxide. The extension direction of the ESD polysilicon is the same as the extension direction of the gate metal lead. The ESD gate polysilicon is connected to the ESD polysilicon and is respectively located on one side of the ESD polysilicon close to the source area and the gate area. The ESD source polysilicon is spaced apart from the ESD gate polysilicon and is connected to the side of the ESD polysilicon close to the source area. The ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead.

[0010] In some embodiments, the ESD gate polysilicon and the ESD source polysilicon are both vertically connected to the ESD polysilicon, the ESD polysilicon is disposed around the source region, and an extension length of the ESD polysilicon is greater than an outer perimeter of the source region.

[0011] In some embodiments, in the direction from the source region toward the gate region, the orthographic projection of the ESD gate polysilicon does not overlap with the orthographic projection of the ESD source polysilicon, and the orthographic projection of the ESD gate polysilicon located on the side of the ESD polysilicon close to the source region overlaps with the orthographic projection of the ESD gate polysilicon located on the side of the ESD polysilicon close to the gate region.

[0012] In some embodiments, the substrate has a source region trench, a buffer region trench and a cutoff region trench, the source region trench is located in the source region, the buffer region trench and the cutoff region trench are located outside the gate region, the buffer region trench is located on the side of the cutoff region trench close to the source region trench, the source region trench, the buffer region trench and the cutoff region trench are all filled with trench polysilicon, and the ESD protection structure is located on the substrate between the source region trench and the buffer region trench.

[0013] In some embodiments, the source region trench includes a main trench and a sub-trench, the main trench is located on a side of the sub-trench close to the ESD protection structure, the width of the main trench is greater than the width of the sub-trench, and the trench polysilicon in the main trench is connected to the ESD polysilicon and the gate metal lead through the ESD gate polysilicon.

[0014] In some embodiments, the ESD gate polysilicon and the ESD source polysilicon have the same type of doping ions.

[0015] In some embodiments, the semiconductor device also includes a dielectric layer disposed on the ESD protection structure, the dielectric layer having an ESD source region contact hole and an ESD gate region contact hole penetrating the dielectric layer, the ESD source region contact hole exposing the ESD source polysilicon, the ESD gate region contact hole exposing the ESD gate polysilicon, the source metal is connected to the ESD source polysilicon through the ESD source region contact hole, and the gate metal lead is connected to the ESD gate polysilicon through the ESD gate region contact hole.

[0016] In some embodiments, the number of the buffer zone grooves is at least two, and the distance between every two adjacent buffer zone grooves is greater than 1 μm.

[0017] The present application also provides a method for preparing a semiconductor device having an ESD protection structure, which is used to prepare the semiconductor device as described above, comprising:

[0018] Providing a substrate, the substrate having a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region;

[0019] An ESD protection structure is formed on the ESD region of the substrate, wherein the ESD protection structure includes gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon, wherein the ESD polysilicon, the ESD gate polysilicon and the ESD source polysilicon are all located on the gate oxide, the ESD gate polysilicon is connected to the ESD polysilicon and are respectively located on one side of the ESD polysilicon close to the source region and the gate region, and the ESD source polysilicon is spaced apart from the ESD gate polysilicon and connected to one side of the ESD polysilicon close to the source region;

[0020] A gate metal lead and a source metal are formed on the substrate and the ESD protection structure. The extension direction of the gate metal lead is the same as the extension direction of the ESD polysilicon. The ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead.

[0021] In some embodiments, after forming an ESD protection structure on the ESD region of the substrate, and before forming a gate metal lead and a source metal disposed at intervals on the substrate and the ESD protection structure, the method further includes:

[0022] A dielectric layer is formed on the ESD protection structure and the substrate, the dielectric layer having an ESD source region contact hole and an ESD gate region contact hole penetrating the dielectric layer, the ESD source region contact hole exposing the ESD source polysilicon, the ESD gate region contact hole exposing the ESD gate polysilicon, the source metal is connected to the ESD source polysilicon through the ESD source region contact hole, and the gate metal lead is connected to the ESD gate polysilicon through the ESD gate region contact hole.

[0023] The present application provides a semiconductor device with an ESD protection structure and a preparation method thereof, comprising a substrate, a source metal, a gate metal lead and an ESD protection structure, wherein the substrate has a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region; the source metal is located on the source region of the substrate; the gate metal lead is located on the gate region of the substrate; the ESD protection structure is arranged on the ESD region of the substrate, and the ESD protection structure comprises gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon, wherein the ESD polysilicon is a PN junction connected in parallel. The invention discloses a structure in which the ESD polysilicon, the ESD gate polysilicon and the ESD source polysilicon are all located on the gate oxide, the extension direction of the ESD polysilicon is the same as the extension direction of the gate metal lead, the ESD gate polysilicon is connected to the ESD polysilicon and are respectively located on the side of the ESD polysilicon close to the source region and the gate region, the ESD source polysilicon and the ESD gate polysilicon are spaced apart and connected to the side of the ESD polysilicon close to the source region, the ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead to improve the ESD protection performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a schematic diagram of a planar structure of a semiconductor device provided by the present application;

[0026] Figure 2 yes Figure 1 The schematic diagram of the structure at S is enlarged;

[0027] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of the semiconductor device along line AB;

[0028] Figure 4 It is a schematic diagram of a process for preparing a semiconductor device provided by the present application;

[0029] Figure 5-Figure 11 It is a schematic diagram of the process structure of the method for preparing a semiconductor device provided in this application.

[0030] Reference numerals:

[0031] 10. Semiconductor device; 100. Substrate; 200. Epitaxial layer; 210. Main trench; 220. Sub-trench; 230. Buffer trench; 240. Cut-off region trench; 300. ESD protection structure; 301. Polysilicon layer; 310. Gate oxide; 320. ESD polysilicon; 330. ESD gate polysilicon; 340. ESD source polysilicon; 400. Gate metal lead; 500. Peripheral metal layer; 600. Source metal layer; 700. ESD source metal lead; 800. Source region; 900. Body region; 1000. Dielectric layer; 1010. ESD source region contact hole; 1020. ESD gate region contact hole; 1030. Source region contact hole; 1040. Cut-off region contact hole; 1100. Passivation layer; 1200. Back metal layer. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by a person skilled in the art to which this application belongs. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more related listed items. The terms "connection", "electrical connection", and "electrical connection" used herein include any direct and indirect electrical or structural connection means. Therefore, if the text describes a first device coupled / connected / electrically connected to a second device, it means that the first device can be directly electrically / structurally connected to the second device, or indirectly electrically / structurally connected to the second device through other devices or connection means.

[0035] The present application provides a semiconductor device with an ESD protection structure, including a substrate, a source metal, a gate metal lead and an ESD protection structure, wherein the substrate has a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region; the source metal is located on the source region of the substrate; the gate metal lead is located on the gate region of the substrate; the ESD protection structure is arranged on the ESD region of the substrate, and the ESD protection structure includes gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon, wherein the ESD polysilicon is P in parallel N structure, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon are all located on the gate oxide, the extension direction of the ESD polysilicon is the same as the extension direction of the gate metal lead, the ESD gate polysilicon is connected to the ESD polysilicon and are respectively located on the side of the ESD polysilicon close to the source region and the gate region, the ESD source polysilicon and the ESD gate polysilicon are spaced apart and connected to the side of the ESD polysilicon close to the source region, the ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead.

[0036] In the present application, the ESD protection structure is composed of gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon. The ESD polysilicon, ESD gate polysilicon and ESD source polysilicon are all arranged on the gate oxide, and the ESD gate polysilicon is arranged to be connected to the ESD polysilicon and are respectively located on both sides of the ESD polysilicon, and the ESD source polysilicon is arranged to be spaced apart from the ESD gate polysilicon and connected to the side of the ESD polysilicon close to the source region, that is, the planar shape of the ESD protection structure is similar to a forked finger shape, so that the perimeter of the ESD protection structure is increased. , thereby improving the ESD protection performance, reducing the risk of gate oxide and other film layers being broken down, thereby improving the performance of the semiconductor device; in addition, the ESD protection structure is set between the gate metal lead and the source metal, saving the area of ​​the gate, so that while improving the ESD protection performance, the source area chip density can be increased, and the FOM (Figure of Merit, performance indicator parameter) can be optimized, thereby improving the performance of the semiconductor device; in addition, the preparation of the ESD protection structure provided by the present application does not require the addition of a new mask plate, the manufacturing process is simple, and is compatible with existing processes and easy to operate.

[0037] See also Figure 1-Figure 3 , Figure 1 is a schematic diagram of a planar structure of a semiconductor device provided by the present application; Figure 2 yes Figure 1 The schematic diagram of the structure at S is enlarged; Figure 3 yes Figure 2 The schematic diagram of the cross-sectional structure of the semiconductor device along the AB line in FIG. 1 is to be noted that, in order to clearly show the relationship between the ESD protection structure 300 and the source metal layer 600 and the gate metal lead 400, Figure 2The schematic diagram of the planar structure of the semiconductor device in the diagram only draws part of the film layer structure, but it does not mean that there is no film layer structure. The present application provides a semiconductor device 10 with an ESD protection structure 300, including a substrate, a source metal, a gate metal lead 400 and an ESD protection structure 300. The substrate has a source region, an ESD region and a gate region, and the ESD region is located between the source region and the gate region; the source metal is located on the source region of the substrate; the gate metal lead 400 is located on the gate region of the substrate; the ESD protection structure 300 is arranged on the ESD region of the substrate, and the ESD protection structure 300 includes a gate oxide 310, an ESD polysilicon 320, an ESD gate polysilicon 330 and an ESD source polysilicon 340, and the ESD polysilicon is a parallel PN structure, and the ESD polysilicon 320, the ESD gate The ESD source polysilicon 330 and the ESD source polysilicon 340 are both located on the gate oxide 310, the extension direction of the ESD polysilicon 320 is the same as the extension direction of the gate metal lead 400, the ESD gate polysilicon 330 is connected to the ESD polysilicon 320 and are respectively located on the side of the ESD polysilicon 320 close to the source region and the gate region, the ESD source polysilicon 340 and the ESD gate polysilicon 330 are spaced apart and connected to the side of the ESD polysilicon 320 close to the source region, that is, the planar shape of the ESD protection structure 300 is similar to a forked finger shape, the ESD source polysilicon 340 is connected to the source metal, and the ESD gate polysilicon 330 is connected to the gate metal lead 400. Specifically, the ESD region is arranged around the source region, the gate region is located on a side of the ESD region away from the source region, and the gate region is arranged around the ESD region, the substrate includes a base 100 and an epitaxial layer 200 arranged on the base 100, the base 100 is an N+ base 100, the epitaxial layer 200 is an N- epitaxial layer 200, the gate oxide 310 is arranged on the epitaxial layer 200, the ESD polysilicon 320, the ESD gate polysilicon 330 and the ESD source polysilicon 340 are arranged on the gate oxide 310 located in the ESD region, the gate oxide 310 is composed of silicon oxide or silicon nitride, and a gate PAD connected to a gate metal lead 400 is also arranged on the gate region; the substrate also has a buffer zone and a cut-off zone, the buffer zone is arranged around a side of the gate region away from the source region, and the cut-off zone is arranged around a side of the buffer zone away from the gate region.

[0038] In one embodiment, the ESD gate polysilicon 330 and the ESD source polysilicon 340 are doped with the same ions, that is, the ESD gate polysilicon 330 and the ESD source polysilicon 340 are both doped with the same type to enable better output signals or currents, to improve conductivity and to precisely control currents, thereby improving the performance of the semiconductor device 10.

[0039] In the present application, the ESD protection structure 300 is composed of a gate oxide 310, an ESD polysilicon 320, an ESD gate polysilicon 330, and an ESD source polysilicon 340. The ESD polysilicon 320, the ESD gate polysilicon 330, and the ESD source polysilicon 340 are arranged on the gate oxide 310 located in the ESD region, and the ESD gate polysilicon 330 is arranged to be connected to the ESD polysilicon 320 and respectively located on both sides of the ESD polysilicon 320, and the ESD source polysilicon 340 is arranged to be spaced apart from the ESD gate polysilicon 330. And it is connected to the side of the ESD polysilicon 320 close to the source region, that is, the planar shape of the ESD protection structure 300 is similar to a fork finger shape, so that the circumference of the ESD protection structure 300 is increased, thereby improving the ESD protection performance, reducing the risk of film layers such as the gate oxide 310 being broken down, thereby improving the performance of the semiconductor device 10; in addition, the ESD protection structure 300 is arranged between the gate metal lead 400 and the source metal, saving the area of ​​the gate, so that while improving the ESD protection performance, the source region chip density can be increased, and the FOM (Figure of Merit, performance indicator parameter or figure of merit) is optimized, thereby improving the performance of the semiconductor device 10; in addition, the preparation of the ESD protection structure 300 provided in the present application does not require the addition of a new mask plate, the manufacturing process is simple, the cost is reduced, and it is compatible with existing processes and easy to operate.

[0040] In one embodiment, the substrate has a source region trench, a buffer region trench 230 and a cutoff region trench 240, the source region trench is located in the source region, the buffer region trench 230 and the cutoff region trench 240 are located outside the gate region, the buffer region trench 230 is located on the side of the cutoff region trench 240 close to the source region trench, the source region trench, the buffer region trench 230 and the cutoff region trench 240 are all filled with trench polysilicon, and the ESD protection structure 300 is located on the substrate between the source region trench and the buffer region trench 230. Specifically, the buffer zone groove 230 is located in the buffer zone, the cut-off zone groove 240 is located in the cut-off zone, and the substrate provided with the ESD protection structure 300 is not etched to form a groove, that is, the ESD protection structure 300 is not arranged in the groove, the gate oxide 310 is arranged on the substrate and also extends into the groove bottom and the groove sidewall of the source zone groove, the buffer zone groove 230 and the cut-off zone groove 240, the trench polysilicon is arranged on the gate oxide 310 located in the source zone groove, the buffer zone groove 230 and the cut-off zone groove 240, and the surface of the trench polysilicon located in the source zone groove, the buffer zone groove 230 and the cut-off zone groove 240 is flush with the surface of the substrate. A buffer zone trench 230 is provided in the buffer zone, and trench polysilicon is provided in the buffer zone trench 230 to achieve the required withstand voltage, and a cut-off zone trench 240 is provided on the side of the buffer zone trench 230 away from the source zone trench, and trench polysilicon is provided in the cut-off zone trench 240, so that the required withstand voltage can be achieved while different circuits are separated to prevent interference between different circuits, thereby improving the working efficiency and stability of the device, and improving the cut-off efficiency, thereby improving the withstand voltage efficiency and reducing directional leakage current.

[0041] In one embodiment, a TBO oxide layer is also provided between the gate oxide 310 located at the bottom of the source trench, the buffer trench 230 and the cut-off trench 240 and the bottom of the source trench, the buffer trench 230 and the cut-off trench 240, and between the ESD polysilicon 320 and the gate oxide 310 located below the ESD polysilicon 320. The TBO oxide layer is formed by a TBO process to achieve thick oxygen isolation, protect the bottom of the trench, prevent current leakage and breakdown, improve the voltage resistance and reliability of the device, and improve the junction capacitance Cgd. At the same time, by increasing the isolation thickness of the bottom of the ESD polysilicon, thick oxygen isolation is achieved, and the electrostatic protection performance of the ESD protection structure 300 is improved, thereby improving the reliability of the ESD protection structure 300.

[0042] In one embodiment, the source trench includes a main trench 210 and a sub-trench 220, the main trench 210 is located on a side of the sub-trench 220 close to the ESD protection structure 300, the width of the main trench 210 is greater than the width of the sub-trench 220, the trench polysilicon in the main trench 210 is connected to the ESD polysilicon 320 and the gate metal lead 400 through the ESD gate polysilicon 330, and the trench polysilicon in the main trench 210 is connected to the trench polysilicon in the sub-trench 220. By setting the width of the main trench 210 to be greater than the width of the sub-trench 220, the trench polysilicon in the main trench 210 can be better connected to the ESD polysilicon 320 and the gate metal lead 400 through the ESD gate polysilicon 330, thereby improving the protection performance of the ESD protection structure 300, thereby further improving the reliability of the device.

[0043] In one embodiment, the depths of the source trench, the buffer trench 230, and the cut-off trench 240 are all greater than 0.5 μm. Specifically, the depths of the source trench, the buffer trench 230, and the cut-off trench 240 may be 0.51 μm, 0.58 μm, 0.66 μm, 0.69 μm, 0.74 μm, 0.82 μm, or 1 μm, etc. In the present application, by setting the depths of the source trench, the buffer trench 230, and the cut-off trench 240 within this range, the source trench, the buffer trench 230, and the cut-off trench 240 can provide a shorter current path, thereby reducing resistance, and at the same time, reducing the side effects caused by the breakdown voltage, thereby improving the performance of the device.

[0044] In one embodiment, the number of the buffer grooves 230 is at least two, and the spacing between each two adjacent buffer grooves 230 is greater than 1 μm. Specifically, the number of the buffer grooves 230 can be 2, 3, 5, 9 or 11, etc. In this embodiment, the number of the buffer grooves 230 is 2 as an example, and the spacing between each two adjacent buffer grooves 230 can be 1.1 μm, 1.51 μm, 1.58 μm, 1.66 μm, 2.69 μm, 2.74 μm, 3.82 μm or 4.1 μm, etc. In the present application, by setting the number of the buffer grooves 230 to at least two and the spacing between each two adjacent buffer grooves 230 to be greater than 1 μm, the voltage resistance performance of the device can be further improved.

[0045] In one embodiment, the width of the main trench 210 is greater than 0.3 μm. Specifically, the width of the main trench 210 may be 0.31 μm, 0.4 μm, 0.54 μm, 0.65 μm, 0.78 μm, 0.9 μm or 1.2 μm, etc., so that the trench polysilicon in the main trench 210 can be better connected with the ESD polysilicon 320 and the gate metal lead 400 through the ESD gate polysilicon 330, thereby improving the protection performance of the ESD protection structure 300, thereby further improving the reliability of the device.

[0046] In one embodiment, the width of the trench polysilicon in the main trench 210 is greater than 1 μm. Specifically, the width of the trench polysilicon in the main trench 210 may be 1.1 μm, 1.3 μm, 1.7 μm, 2.3 μm, 2.7 μm or 3.9 μm.

[0047] In one embodiment, the ESD gate polysilicon 330 and the ESD source polysilicon 340 are vertically connected to the ESD polysilicon 320, and the ESD polysilicon 320 is arranged around the source region, and the extension length of the ESD polysilicon 320 is greater than the outer perimeter of the source region, that is, the ESD polysilicon 320 is completely wrapped around the outside of the source metal layer. This further improves the ESD protection performance, reduces the risk of the gate oxide 310 and other film layers being broken down, and thus improves the performance of the semiconductor device 10.

[0048] In one embodiment, in the direction from the source region to the gate region, the orthographic projection of the ESD gate polysilicon 330 does not overlap with the orthographic projection of the ESD source polysilicon 340, and the orthographic projection of the ESD gate polysilicon 330 located on the side of the ESD polysilicon 320 close to the source region overlaps with the orthographic projection of the ESD gate polysilicon 330 located on the side of the ESD polysilicon 320 close to the gate region, that is, the planar shape of the ESD protection structure 300 is similar to a cross-finger shape, thereby further improving the protection performance of the ESD protection structure 300.

[0049] In some embodiments, the planar shape of the source region trench includes, but is not limited to, a strip, a square, a triangle, a quadrilateral, a pentagon, a hexagon, or a circle, etc. In this embodiment, the planar shape of the source region trench is a strip as an example for explanation. In this application, the planar shape of the source region trench is designed to be this shape so that the source region trench can provide a shorter current path, thereby reducing resistance, and at the same time, reducing the side effects caused by the breakdown voltage, thereby improving the performance of the device.

[0050] In one embodiment, the ESD polysilicon 320 includes at least one first doping portion and at least two second doping portions arranged on both sides of the first doping portion, the first doping portion is one of N-type doping and P-type doping, and the second doping portion is the other of N-type doping and P-type doping, so that the ESD polysilicon 320 is composed of a plurality of NP diode parallel structures such as NPN, PNP, NPNPN or PNPNP, and further a plurality of NP diode parallel structures such as NPN, PNP, NPNPN or PNPNP are provided between the ESD source polysilicon 340 and the ESD gate polysilicon 330, thereby improving the protection performance of the ESD protection structure 300.

[0051] In one embodiment, the semiconductor device 10 further includes a source region 800 and a body region 900, and the source region 800 and the body region 900 are located on the substrate between every two adjacent source region grooves in the source region. The source region 800 is located on a side of the body region 900 close to the ESD polysilicon 320. The body region 900 is also provided between every two adjacent buffer region grooves 230 in the cut-off region and between the buffer region groove 230 and the cut-off region groove 240. The source region 800 and the body region 900 are also provided on the side of the cut-off region groove 240 away from the buffer region groove 230, so as to prevent mutual interference between devices and improve FOM, thereby improving the reliability of the device.

[0052] In one embodiment, the semiconductor device 10 also includes a dielectric layer 1000 disposed on the ESD protection structure 300, the dielectric layer 1000 having an ESD source region contact hole 1010 and an ESD gate region contact hole 1020 penetrating the dielectric layer 1000, the ESD source region contact hole 1010 exposing the ESD source polysilicon 340, the ESD gate region contact hole 1020 exposing the ESD gate polysilicon 330, the source metal is connected to the ESD source polysilicon 340 through the ESD source region contact hole 1010, and the gate metal lead 400 is connected to the ESD gate polysilicon 330 through the ESD gate region contact hole 1020. Furthermore, the dielectric layer 1000 also includes a source region contact hole 1030 and a stop region contact hole 1040 penetrating the dielectric layer 1000, the source region contact hole 1030 is located in the source region and exposes the source region 800, and the stop region contact hole 1040 is located in the stop region and exposes the trench polysilicon located in the stop region trench 240; the semiconductor device 10 also includes a peripheral metal layer 500 arranged in the stop region. The source metal, the gate metal lead 400 and the peripheral metal layer 500 are arranged at intervals on the dielectric layer 1000, the gate metal lead 400 and the peripheral metal layer 500 are arranged at intervals, the source metal includes a source metal layer 600 and an ESD source metal lead 700 connected to the source metal layer 600, the source metal layer 600 is connected to the source region 800 through the source region contact hole 1030, the ESD source metal lead 700 is connected to the ESD source polysilicon 340 through the ESD source region contact hole 1010, the gate metal lead 400 is connected to the ESD gate polysilicon 330 through the ESD gate region contact hole 1020, and the peripheral metal layer 500 is connected to the trench polysilicon located in the cut-off region trench 240 through the cut-off region contact hole 1040.

[0053] In one embodiment, the semiconductor device 10 further includes a passivation layer 1100 and a back metal layer 1200. The passivation layer 1100 is disposed on the ESD source region metal lead 700, the dielectric layer 1000, the gate metal lead 400 and the peripheral metal layer 500. The back metal layer 1200 is disposed on a side of the substrate away from the passivation layer 1100, and the back metal layer 1200 forms a drain region.

[0054] See also Figure 4-Figure 11 , Figure 4 It is a schematic diagram of a process for preparing a semiconductor device provided by the present application; Figure 5-Figure 11 The present application also provides a method for preparing a semiconductor device 10 having an ESD protection structure 300, which is used to prepare the semiconductor device 10 provided by the present application, comprising:

[0055] S11. Provide a substrate, wherein the substrate has a source region, an ESD region and a gate region, and the ESD region is located between the source region and the gate region.

[0056] See also Figure 5 Specifically, the substrate has an active area, an ESD area, a gate area, a buffer area and a cut-off area. The buffer area is arranged around the side of the gate area away from the source area, and the cut-off area is arranged around the side of the buffer area away from the gate area. The substrate includes a base 100 and an epitaxial layer 200 arranged on the base 100. The base 100 is an N+ base 100, and the epitaxial layer 200 is an N-epitaxial layer 200. An oxide layer is formed on the epitaxial layer 200, and the thickness of the oxide layer is 0.2-0.6um. Then, after the oxide layer is blocked The epitaxial layer 200 is etched to form a source region groove, a buffer region groove 230 and a cutoff region groove 240, wherein the source region groove is located in the source region, the buffer region groove 230 is located in the buffer region, and the cutoff region groove 240 is located in the cutoff region, wherein the source region groove includes a main groove 210 and a sub-groove 220, wherein the main groove 210 is located on a side of the sub-groove 220 close to the ESD protection structure 300, and the width of the main groove 210 is greater than the width of the sub-groove 220; then, the surface blocking oxide layer is removed.

[0057] See also Figure 6 In one embodiment, after step S11, the process further includes: forming a sacrificial oxide layer in the source region trench, the buffer region trench 230 and the cut-off region trench 240, wherein the temperature for forming the sacrificial oxide layer is 900-1150° C. and the thickness of the sacrificial oxide layer is 0.02-0.15 um; and then, removing the sacrificial oxide layer by wet etching to remove impurities in the trench or repair damage to the bottom and sidewall of the trench to make the interior of the trench smooth.

[0058] See also Figure 6 In one embodiment, after forming a sacrificial oxide layer in the source trench, the buffer trench 230 and the cut-off trench 240, the method further includes: using a TBO process on the epitaxial layer 200 to thicken the bottom of the source trench, the buffer trench 230 and the cut-off trench 240 and the epitaxial layer 200 located between the buffer trench 230 and the cut-off trench 240, so as to form a TBO oxide layer on the epitaxial layer 200 at the bottom of the source trench, the buffer trench 230 and the cut-off trench 240 and the buffer trench 230 and the cut-off trench 240, so as to achieve thick oxygen isolation, protect the bottom of the trench, prevent current leakage and breakdown, improve the voltage resistance and reliability of the device, and improve the junction capacitance Cgd. At the same time, by increasing the ESD polysilicon bottom isolation thickness, thick oxygen isolation is achieved, and the electrostatic protection performance of the ESD protection structure 300 is improved, thereby improving the reliability of the ESD protection structure 300.

[0059] See also Figure 6In one embodiment, after the epitaxial layer 200 is thickened by TBO process on the bottom of the source trench, the buffer trench 230 and the cut-off trench 240 and the epitaxial layer 200 between the buffer trench 230 and the cut-off trench 240, the process further includes: generating an oxide layer or a nitride layer on the epitaxial layer 200 as a gate oxide 310, the thickness of the gate oxide 310 is 0.01-0.1 um, and the temperature for generating the oxide layer is 900-1200°C.

[0060] S12. An ESD protection structure is formed on the ESD region of the substrate, wherein the ESD protection structure includes gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon. The ESD polysilicon is a parallel PN structure. The ESD polysilicon, ESD gate polysilicon and ESD source polysilicon are all located on the gate oxide. The ESD gate polysilicon is connected to the ESD polysilicon and are respectively located on one side of the ESD polysilicon close to the source region and the gate region. The ESD source polysilicon is spaced apart from the ESD gate polysilicon and is connected to the side of the ESD polysilicon close to the source region.

[0061] See also Figure 7 It should be noted that Figure 7 Figure (a) is a schematic diagram of the planar structure of the semiconductor device in this step. Figure 7 Figure (b) is Figure 7The schematic diagram of the cross-sectional structure of the semiconductor device along the AB line in (a) of FIG. Specifically, a polysilicon layer 301 is formed on the gate oxide 310, and the thickness of the polysilicon layer 301 is 0.6-1.2um; then, the polysilicon layer 301 is subjected to ion implantation, and the implanted ions may be B, and the concentration of the implanted ions is 1E12-5E15, to form P-type doped polysilicon; then, the polysilicon layer 301 located in the source region and the polysilicon layer 301 located in the gate region are etched back to make the polysilicon layer 301 located in the source region and the polysilicon layer 301 located in the gate region flush with the plane of the epitaxial layer 200 to form trench polysilicon, and at the same time, the polysilicon layer 301 located in the ESD region is etched to form an ESD protection structure 300, and the ESD protection structure 300 includes a gate oxide 310, an ESD polysilicon 320, ESD gate polysilicon 330 and ESD source polysilicon 340, ESD polysilicon 320, ESD gate polysilicon 330 and ESD source polysilicon 340 are all located on the gate oxide 310, ESD gate polysilicon 330 is connected to ESD polysilicon 320 and are respectively located on the side of ESD polysilicon 320 close to the source region and the gate region, ESD source polysilicon 340 and ESD gate polysilicon 330 are spaced apart and connected to the side of ESD polysilicon 320 close to the source region, the trench polysilicon in the main trench 210 is connected to ESD polysilicon 320 and the gate metal lead 400 through the ESD gate polysilicon 330, and the trench polysilicon located in the main trench 210 is connected to the trench polysilicon located in the sub-trench 220.

[0062] See also Figure 8 It should be noted that Figure 8 Figure (a) is a schematic diagram of the planar structure of the semiconductor device in this step. Figure 8 Figure (b) is Figure 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device along line AB in FIG. 1. In one embodiment, after S12, the method further includes:

[0063] The body region 900 is implanted and annealed at high temperature through self-alignment of the source region trench to form the body region 900. The implanted ions may be B, the implanted ion concentration is 1E12-5E15, and the annealing temperature is 800-1200°C. The source region 800 is implanted and annealed at high temperature through self-alignment of the source region trench. The implanted ions may be As or P, etc., the implanted ions concentration is 1E14-1E18, and the annealing temperature is 850-1200°C to form the source region 800. The ESD polysilicon 320 is simultaneously implanted with N+ to form an NP back-to-back diode structure composed of a first doping portion and a second doping portion. At the same time, the ESD gate polysilicon 330 and the ESD source polysilicon 340 are also implanted with the same ions.

[0064] See also Fig. 9It should be noted that Fig. 9 Figure (a) is a schematic diagram of the planar structure of the semiconductor device in this step. Fig. 9 Figure (b) is Fig. 9 Schematic diagram of the cross-sectional structure of the semiconductor device along line AB in (a) of FIG. In one embodiment, after forming the body region 900 and the source region 800, it also includes: an ESD protection structure 300 and a dielectric layer 1000 formed on the substrate, the dielectric layer 1000 has an ESD source region contact hole 1010 and an ESD gate region contact hole 1020 penetrating the dielectric layer 1000, the ESD source region contact hole 1010 exposes the ESD source polysilicon 340, the ESD gate region contact hole 1020 exposes the ESD gate polysilicon 330, the source metal is connected to the ESD source polysilicon 340 through the ESD source region contact hole 1010, and the gate metal lead 400 is connected to the ESD gate polysilicon 330 through the ESD gate region contact hole 1020. Specifically, a dielectric layer 1000 is deposited on the ESD protection structure 300 and the substrate, and an ESD source region contact hole 1010, an ESD gate region contact hole 1020, a source region contact hole 1030, and a cut-off region contact hole 1040 are formed by etching through a mask plate. The ESD source region contact hole 1010, the ESD gate region contact hole 1020, the source region contact hole 1030, and the cut-off region contact hole 1040 are injected with the same ions as the body region 900 and annealed. The injected ions may be B, and the concentration of the injected ions is 1E12-1E17. The annealing is performed. The temperature is 800-1200°C, the ESD source region contact hole 1010 exposes the ESD source polysilicon 340, the ESD gate region contact hole 1020 exposes the ESD gate polysilicon 330, the source metal is connected to the ESD source polysilicon 340 through the ESD source region contact hole 1010, the gate metal lead 400 is connected to the ESD gate polysilicon 330 through the ESD gate region contact hole 1020, the source region contact hole 1030 is located in the source region and exposes the source region 800, and the stop region contact hole 1040 is located in the stop region and exposes the trench polysilicon located in the stop region trench 240.

[0065] S13. Forming gate metal leads and source metals spaced apart on the substrate and the ESD protection structure. The extension direction of the gate metal leads is the same as the extension direction of the ESD polysilicon. The ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal leads.

[0066] See also Fig.10Specifically, a source metal, a gate metal lead 400 and a peripheral metal layer 500 are formed on the dielectric layer 1000, the gate metal lead 400 and the peripheral metal layer 500 are spaced apart, the peripheral metal layer 500 is located in the cut-off region, the source metal includes a source metal layer 600 and an ESD source metal lead 700 connected to the source metal, the source metal layer 600 is connected to the source region 800 through a source region contact hole 1030, the ESD source metal lead 700 is connected to the ESD source polysilicon 340 through an ESD source region contact hole 1010, the gate metal lead 400 is connected to the ESD gate polysilicon 330 through an ESD gate region contact hole 1020, and the peripheral metal layer 500 is connected to the trench polysilicon located in the cut-off region trench 240 through a cut-off region contact hole 1040.

[0067] See also Fig.10 and Fig.11 In one embodiment, after S13, the process further includes: forming a passivation layer 1100 on the ESD source metal lead 700, the dielectric layer 1000, the gate metal lead 400 and the peripheral metal layer 500; and then forming a back metal layer 1200 on a side of the substrate away from the passivation layer 1100, the back metal layer 1200 forming a drain region.

[0068] In the present application, the semiconductor device 10 provided in the present application is prepared by the above method, and there is no need to add a new mask plate, the manufacturing process is simple, thereby reducing the cost, and it is compatible with the existing process and easy to operate; in addition, the ESD protection structure 300 is composed of a gate oxide 310, an ESD polysilicon 320, an ESD gate polysilicon 330 and an ESD source polysilicon 340, and the ESD gate polysilicon 330 is set to be connected to the ESD polysilicon 320 and respectively located on both sides of the ESD polysilicon 320, and the ESD source polysilicon 340 is set to be spaced apart from the ESD gate polysilicon 330. The ESD protection structure 300 is arranged and connected to the side of the ESD polysilicon 320 close to the source region, that is, the planar shape of the ESD protection structure 300 is similar to a forked finger shape, so that the circumference of the ESD protection structure 300 is increased, thereby improving the ESD protection performance, reducing the risk of film layers such as the gate oxide 310 being broken down, and thus improving the performance of the semiconductor device 10; in addition, the ESD protection structure 300 is arranged between the gate metal lead 400 and the source metal, which saves the area of ​​the gate, so that while improving the ESD protection performance, the source region chip density can be increased, and the FOM is optimized, thereby improving the performance of the semiconductor device 10.

[0069] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device having an ESD protection structure, characterized in that: include: A substrate, the substrate having a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region; A source metal, located on the source region of the substrate; A gate metal lead, located on the gate region of the substrate; An ESD protection structure is arranged on the ESD region of the substrate, the ESD protection structure includes gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon, the ESD polysilicon is a parallel PN structure, the ESD polysilicon, the ESD gate polysilicon and the ESD source polysilicon are all located on the gate oxide, the extension direction of the ESD polysilicon is the same as the extension direction of the gate metal lead, the ESD gate polysilicon is connected to the ESD polysilicon and is respectively located on one side of the ESD polysilicon close to the source region and the gate region, the ESD The D source polysilicon is spaced apart from the ESD gate polysilicon and connected to a side of the ESD polysilicon close to the source region, the ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead, wherein, in the direction from the source region toward the gate region, the orthographic projection of the ESD gate polysilicon does not overlap with the orthographic projection of the ESD source polysilicon, and the orthographic projection of the ESD gate polysilicon located on the side of the ESD polysilicon close to the source region overlaps with the orthographic projection of the ESD gate polysilicon located on the ESD polysilicon close to the gate region.

2. The semiconductor device with an ESD protection structure according to claim 1, characterized in that: The ESD gate polysilicon and the ESD source polysilicon are both vertically connected to the ESD polysilicon. The ESD polysilicon is arranged around the source region, and an extension length of the ESD polysilicon is greater than an outer perimeter of the source region.

3. The semiconductor device with an ESD protection structure according to claim 1, characterized in that: The substrate has a source region trench, a buffer region trench and a cutoff region trench, the source region trench is located in the source region, the buffer region trench and the cutoff region trench are located outside the gate region, the buffer region trench is located on a side of the cutoff region trench close to the source region trench, the source region trench, the buffer region trench and the cutoff region trench are all filled with trench polysilicon, and the ESD protection structure is located on the substrate between the source region trench and the buffer region trench.

4. The semiconductor device with an ESD protection structure according to claim 3, characterized in that: The source region trench includes a main trench and a sub-trench, the main trench is located on a side of the sub-trench close to the ESD protection structure, the width of the main trench is greater than the width of the sub-trench, and the trench polysilicon located in the sub-trench is connected to the ESD polysilicon and the gate metal lead through the trench polysilicon located in the main trench through the ESD gate polysilicon.

5. The semiconductor device with an ESD protection structure according to claim 1, characterized in that: The ESD gate polysilicon and the ESD source polysilicon have the same type of doping ions.

6. The semiconductor device with an ESD protection structure according to claim 1, characterized in that: The semiconductor device also includes a dielectric layer arranged on the ESD protection structure, the dielectric layer having an ESD source region contact hole and an ESD gate region contact hole penetrating the dielectric layer, the ESD source region contact hole exposing the ESD source polysilicon, the ESD gate region contact hole exposing the ESD gate polysilicon, the source metal is connected to the ESD source polysilicon through the ESD source region contact hole, and the gate metal lead is connected to the ESD gate polysilicon through the ESD gate region contact hole.

7. The semiconductor device with an ESD protection structure according to claim 3, characterized in that: The number of the buffer zone grooves is at least two, and the distance between every two adjacent buffer zone grooves is greater than 1 μm.

8. A method for preparing a semiconductor device having an ESD protection structure, characterized in that: For preparing a semiconductor device as claimed in any one of claims 1 to 7, comprising: Providing a substrate, the substrate having a source region, an ESD region and a gate region, wherein the ESD region is located between the source region and the gate region; An ESD protection structure is formed on the ESD region of the substrate, wherein the ESD protection structure includes gate oxide, ESD polysilicon, ESD gate polysilicon and ESD source polysilicon, wherein the ESD polysilicon is a parallel PN structure, wherein the ESD polysilicon, the ESD gate polysilicon and the ESD source polysilicon are all located on the gate oxide, wherein the ESD gate polysilicon is connected to the ESD polysilicon and are respectively located on one side of the ESD polysilicon close to the source region and the gate region, and wherein the ESD source polysilicon is spaced apart from the ESD gate polysilicon and is connected to one side of the ESD polysilicon close to the source region; A gate metal lead and a source metal are formed on the substrate and the ESD protection structure. The extension direction of the gate metal lead is the same as the extension direction of the ESD polysilicon. The ESD source polysilicon is connected to the source metal, and the ESD gate polysilicon is connected to the gate metal lead.

9. The method for preparing a semiconductor device with an ESD protection structure according to claim 8, characterized in that: After forming an ESD protection structure on the ESD region of the substrate, and before forming a gate metal lead and a source metal disposed at intervals on the substrate and the ESD protection structure, the method further includes: A dielectric layer is formed on the ESD protection structure and the substrate, the dielectric layer having an ESD source region contact hole and an ESD gate region contact hole penetrating the dielectric layer, the ESD source region contact hole exposing the ESD source polysilicon, the ESD gate region contact hole exposing the ESD gate polysilicon, the source metal is connected to the ESD source polysilicon through the ESD source region contact hole, and the gate metal lead is connected to the ESD gate polysilicon through the ESD gate region contact hole.

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