Shielded gate metal oxide semiconductor field effect transistor and method of manufacturing the same

Abstract

The application provides a shield gate metal oxide semiconductor field effect transistor and a manufacturing method thereof. The semiconductor field effect transistor is formed by an auxiliary gate anode oxide layer, a first conductive type shield gate polysilicon region and a first conductive type auxiliary gate anode polysilicon region to form an auxiliary gate structure. The auxiliary gate is a reverse conducting diode. When the device is reversely conducted, the auxiliary gate is preferentially conducted due to a lower conduction voltage, and is a unipolar conducting diode. The hole concentration in the device is reduced, and therefore the reverse recovery performance of the traditional shield gate metal oxide semiconductor field effect transistor is greatly improved. In addition, a Schottky contact is formed between a source metal layer and a second conductive type body region, the influence of a parasitic triode structure in the traditional structure is reduced, and therefore the working reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor electronic devices, and in particular to a shielded gate metal oxide semiconductor field effect transistor and a manufacturing method thereof. Background Art

[0002] With the development of power integrated circuits, the development of power semiconductor devices has continued to flourish. Against this backdrop, the shielded-gate metal-oxide-semiconductor field-effect transistor (SGT-MOSFET) has emerged. Its high cell density, low on-resistance, and low switching losses make it a promising device for power electronics and new energy applications, particularly in the low-voltage range.

[0003] However, a problem faced by traditional shielded-gate metal-oxide-semiconductor field-effect transistor (SGT-MOSFET) devices is that they place high demands on the reverse recovery performance of their body diodes when operating in the third quadrant. The body diodes of traditional shielded-gate metal-oxide-semiconductor field-effect transistors (SGT-MOSFETs) are bipolar devices. Due to the presence of an excess of minority carriers in the body diode, their reverse recovery performance is poor, resulting in a large reverse recovery current, which is detrimental to their use in rectifier circuits. Furthermore, due to the presence of a parasitic triode structure at the source, traditional SGT-MOSFET devices are prone to carrier multiplication, which can lead to device damage and poor reliability.

[0004] Therefore, how to design a shielded gate metal oxide semiconductor field effect transistor with fast reverse recovery and high reliability is a problem that needs to be solved urgently. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present invention provides a shielded gate metal oxide semiconductor field effect transistor to solve at least one of the above-mentioned technical problems.

[0006] In order to achieve the above-mentioned objectives and other related objectives, the technical solutions provided in this application are as follows.

[0007] In a first aspect, the present application provides a shielded gate metal oxide semiconductor field effect transistor, comprising:

[0008] A drain metal layer, and a first conductive type substrate layer and a first conductive type drift region sequentially stacked on the drain metal layer;

[0009] Two first grooves are provided in the first conductive type drift region;

[0010] A gate oxide layer, a first conductivity type shielding gate polysilicon region, and a first conductivity type gate polysilicon region are provided in the first first groove, the gate oxide layer wraps the first conductivity type shielding gate polysilicon region and the first conductivity type gate polysilicon region, the first conductivity type gate polysilicon region is located on the first conductivity type shielding gate polysilicon region and is isolated by the gate oxide layer;

[0011] An auxiliary gate anode oxide layer, a first conductivity type shielding gate polysilicon region, and a first conductivity type auxiliary gate anode polysilicon region are provided in the second first groove, the auxiliary gate anode oxide layer wraps the first conductivity type shielding gate polysilicon region and a portion of the first conductivity type auxiliary gate anode polysilicon region, the first conductivity type auxiliary gate anode polysilicon region is located on the first conductivity type shielding gate polysilicon region and is isolated by the auxiliary gate anode oxide layer;

[0012] A second conductive type anode injection region and a second conductive type body region are provided on the first conductive type drift region;

[0013] A source metal layer is provided on the gate oxide layer, the auxiliary gate anode oxide layer, the second conductive type anode injection region, the second conductive type body region, and the first conductive type auxiliary gate anode polysilicon region.

[0014] In one embodiment of the present invention, a portion of the gate oxide layer in the horizontal direction is located between the first conductive type drift regions, a portion is located between the second conductive type body regions, and a portion is located between the source metal layers; a portion of the auxiliary gate anode oxide layer in the horizontal direction is located between the first conductive type drift regions, and a portion is located between the second conductive type body regions, and the horizontal direction is parallel to the direction of the drain metal layer.

[0015] In one embodiment of the present invention, in the horizontal direction, a portion of the gate oxide layer and the auxiliary gate anode oxide layer are isolated by the first conductive type drift region, and a portion are isolated by the second conductive type anode injection region, the second conductive type body region and a portion of the source metal layer; and a portion of the source metal layer and the second conductive type anode injection region are located between two second conductive type body regions in the horizontal direction.

[0016] In one embodiment of the present invention, the first conductive type gate polysilicon region is isolated from the second conductive type body region in the horizontal direction by a first gate oxide layer formed by the gate oxide layer, and the first conductive type auxiliary gate anode polysilicon region is isolated from the second conductive type body region in the horizontal direction by a second gate oxide layer formed by the auxiliary gate anode oxide layer, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0017] In one embodiment of the present invention, an auxiliary gate anode oxide layer and a first conductivity type auxiliary gate anode polysilicon region are disposed in the second first groove, and the auxiliary gate anode oxide layer partially wraps the first conductivity type auxiliary gate anode polysilicon region.

[0018] In one embodiment of the present invention, in the horizontal direction, the gate oxide layer and the auxiliary gate anode oxide layer are partially isolated by the first conductive type drift region and partially isolated by the second conductive type body region, and the second conductive type body region and the second conductive type anode injection region are sequentially arranged on the left side of the gate oxide layer.

[0019] In one embodiment of the present invention, a first conductive type source region is provided on the second conductive type body region, and the source metal layer covers the second conductive type anode injection region, part of the second conductive type body region, part of the gate oxide layer, part of the auxiliary gate anode oxide layer, the first conductive type auxiliary gate anode polysilicon region and the first conductive type source region; and the first conductive type source region is located between the second conductive type body region and the gate oxide layer in the horizontal direction.

[0020] In a second aspect, the present application further provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, comprising:

[0021] S1. Providing a first conductive type substrate layer, wherein the first conductive type substrate layer includes a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer to form a first conductive type drift region;

[0022] S2. forming a second conductive type body region on the first conductive type drift region based on ion implantation;

[0023] S3, etching the first conductive type drift region and the second conductive type body region to form two first grooves, forming a gate oxide layer, a first conductive type shielding gate polysilicon region, and a first conductive type gate polysilicon region in the first first groove, and forming an auxiliary gate anode oxide layer, the first conductive type shielding gate polysilicon region, and a first conductive type auxiliary gate anode polysilicon region in the second first groove;

[0024] S4, performing ion implantation on a portion of the second conductive type body region to form a second conductive type anode implantation region;

[0025] S5, etching the second conductive type anode injection region to form a source metal layer based on metal spraying and annealing;

[0026] S6. Perform metal spraying and annealing on the back side of the first conductive type substrate layer to form a drain metal layer.

[0027] In a third aspect, the present application further provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, comprising:

[0028] S1. Providing a first conductive type substrate layer, wherein the first conductive type substrate layer includes a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer to form a first conductive type drift region;

[0029] S2. forming a second conductive type body region on the first conductive type drift region based on ion implantation;

[0030] S3, etching the first conductive type drift region and the second conductive type body region to form two first grooves, forming a gate oxide layer, a first conductive type shielding gate polysilicon region, and a first conductive type gate polysilicon region in the first first groove, and forming an auxiliary gate anode oxide layer and the first conductive type auxiliary gate anode polysilicon region in the second first groove;

[0031] S4, performing ion implantation on a portion of the second conductive type body region to form a second conductive type anode implantation region;

[0032] S5, etching the second conductive type anode injection region to form a source metal layer based on metal spraying and annealing;

[0033] S6. Perform metal spraying and annealing on the back side of the first conductive type substrate layer to form a drain metal layer.

[0034] In a fourth aspect, the present application further provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, comprising:

[0035] S1. Providing a first conductive type substrate layer, wherein the first conductive type substrate layer includes a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer to form a first conductive type drift region;

[0036] S2. forming a second conductive type body region on the first conductive type drift region based on ion implantation;

[0037] S3, etching the first conductive type drift region and the second conductive type body region to form two first grooves, forming a gate oxide layer, a first conductive type shielding gate polysilicon region, and a first conductive type gate polysilicon region in the first first groove, and forming an auxiliary gate anode oxide layer and the first conductive type auxiliary gate anode polysilicon region in the second first groove;

[0038] S4, performing ion implantation on a portion of the second conductive type body region to form a second conductive type anode implantation region and a first conductive type source region;

[0039] S5, etching the second conductive type anode injection region to form a source metal layer based on metal spraying and annealing;

[0040] S6. Perform metal spraying and annealing on the back side of the first conductive type substrate layer to form a drain metal layer.

[0041] The present application provides a shielded-gate metal-oxide-semiconductor field-effect transistor and a method for manufacturing the same. The semiconductor field-effect transistor comprises an auxiliary gate structure formed by an auxiliary gate anode oxide layer, a first-conductivity-type shielded gate polysilicon region, and a first-conductivity-type auxiliary gate anode polysilicon region. The auxiliary gate acts as a reverse-conducting diode. When the device is reverse-conducting, the auxiliary gate preferentially conducts due to its lower turn-on voltage. As a unipolar conduction diode, this reduces the hole concentration within the device, thereby significantly improving the reverse recovery performance of a conventional shielded-gate metal-oxide-semiconductor field-effect transistor. Furthermore, because the source metal layer forms a Schottky contact with the second-conductivity-type body region, the influence of the parasitic triode structure in the conventional structure is reduced, thereby improving the device's operating reliability.

[0042] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that a person skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0044] Figure 1 A schematic cross-sectional view of a shielded gate metal oxide semiconductor field effect transistor according to an exemplary embodiment of the present invention;

[0045] Figure 2 A schematic cross-sectional view of a shielded gate metal oxide semiconductor field effect transistor with an improved auxiliary gate structure according to an exemplary embodiment of the present invention;

[0046] Figure 3 An exemplary embodiment of the present invention is shown in Figure 2 A schematic cross-sectional view of an improved shielded gate metal oxide semiconductor field effect transistor based on the present invention;

[0047] Figure 4 An exemplary embodiment of the present invention is shown in Figure 3 A schematic cross-sectional view of a shielded gate metal oxide semiconductor field effect transistor having a first conductivity type source region added thereto;

[0048] Figure 5 A schematic diagram showing a comparison of reverse recovery characteristics according to an exemplary embodiment of the present invention;

[0049] Figure 6 A flow chart showing a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor according to an exemplary embodiment of the present invention;

[0050] Figures 7 to 12 A schematic cross-sectional view corresponding to a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor according to an exemplary embodiment of the present invention is shown.

[0051] Explanation of the figure marks: 1-drain metal layer, 2-heavily doped first conductive type substrate layer, 3-heavily doped first conductive type drift region, 4-gate oxide layer, 5-auxiliary gate anode oxide layer, 6-first conductive type shielding gate polysilicon region, 7-second conductive type anode injection region, 8-second conductive type body region, 9-first conductive type gate polysilicon region, 10-first conductive type auxiliary gate anode polysilicon region, 11-source metal layer, 20-first gate oxide layer, 21-second gate oxide layer, 30-first conductive type source region. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.

[0053] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0054] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0055] With the development of power integrated circuits, power semiconductor devices are constantly being updated. Against this backdrop, shielded-gate metal-oxide-semiconductor field-effect transistors (SGT-MOSFETs) have emerged. Their high cell density, low on-resistance, and low switching losses make them very promising in power electronics and new energy applications, especially in the low-voltage range.

[0056] However, traditional shielded-gate metal-oxide-semiconductor field-effect transistor (SGT-MOSFET) devices face a problem: when operating in the third quadrant, they place high demands on the reverse recovery performance of the body diode. The body diode of a traditional shielded-gate metal-oxide-semiconductor field-effect transistor (SGT-MOSFET) is a bipolar device. Due to the presence of an excess of minority carriers in the body diode, its reverse recovery performance is poor, resulting in a large reverse recovery current, which is not conducive to its use in rectifier circuits. In addition, due to the presence of a parasitic triode structure at the source, traditional shielded-gate metal-oxide-semiconductor field-effect transistor (SGT-MOSFET) devices are prone to carrier multiplication effects, which can cause device damage and poor reliability.

[0057] First, as Figure 1 As shown, in an exemplary embodiment, a shielded gate metal oxide semiconductor field effect transistor includes:

[0058] A drain metal layer 1 and a first conductive type substrate layer 2 and a first conductive type drift region 3 sequentially stacked on the drain metal layer 1;

[0059] Two first grooves are provided in the first conductive type drift region 3;

[0060] A gate oxide layer 4, a first conductivity type shielding gate polysilicon region 6, and a first conductivity type gate polysilicon region 9 are provided in the first first groove. The gate oxide layer 4 wraps the first conductivity type shielding gate polysilicon region 6 and the first conductivity type gate polysilicon region 9. The first conductivity type gate polysilicon region 9 is located on the first conductivity type shielding gate polysilicon region 6 and is isolated by the gate oxide layer 4.

[0061] An auxiliary gate anode oxide layer 5, a first conductivity type shielding gate polysilicon region 6, and a first conductivity type auxiliary gate anode polysilicon region 10 are provided in the second first groove. The auxiliary gate anode oxide layer 5 wraps the first conductivity type shielding gate polysilicon region 6 and a portion of the first conductivity type auxiliary gate anode polysilicon region 10. The first conductivity type auxiliary gate anode polysilicon region 10 is located on the first conductivity type shielding gate polysilicon region 6 and is isolated by the auxiliary gate anode oxide layer 5.

[0062] A second conductive type anode injection region 7 and a second conductive type body region 8 are provided on the first conductive type drift region 3;

[0063] A source metal layer 11 is provided on the gate oxide layer 4 , the auxiliary gate anode oxide layer 5 , the second conductivity type anode injection region 7 , the second conductivity type body region 8 , and the first conductivity type auxiliary gate anode polysilicon region 10 .

[0064] It should be emphasized that if Figure 1 As shown, the gate oxide layer 4, the first conductivity type shielding gate polysilicon region 6, and the first conductivity type gate polysilicon region 9 together form a shielded gate structure of the field effect transistor; the auxiliary gate anode oxide layer 5, the first conductivity type shielding gate polysilicon region 6, and the first conductivity type auxiliary gate anode polysilicon region 10 together form an auxiliary gate structure. A Schottky contact is formed between the source metal layer 11 and the second conductivity type body region 8, and an ohmic contact is formed between the source metal layer 11 and the second conductivity type anode injection region 7.

[0065] It should be noted that the first conductive type substrate layer 2, the first conductive type shielding gate polysilicon region 6, the second conductive type anode injection region 7, the first conductive type gate polysilicon region 9, and the first conductive type auxiliary gate anode polysilicon region 10 are heavily doped, and the first conductive type drift region 3 is lightly doped.

[0066] Specifically, the main material of the shielded gate metal oxide semiconductor field effect transistor is silicon material, and the doping concentration of the lightly doped first conductive type drift region 3 is in the range of 1×10 15 cm -3 to 8×10 15 cm -3 The doping concentration of the auxiliary gate anode oxide layer 5 and the heavily doped first conductivity type shielding gate polysilicon region 6 is in the range of 1×10 20 cm -3 to 1×10 21 cm -3 The heavily doped first conductivity type gate polysilicon region 9 and the heavily doped first conductivity type auxiliary gate anode polysilicon region 10 have a value range of 1×10 20 cm -3 to 1×10 21 cm -3 The doping concentration of the second conductive type body region 8 is in the range of 1×10 17 cm -3 to 5×10 17 cm -3 The doping concentration of the heavily doped second conductivity type anode injection region 7 is in the range of 2×10 18 cm -3 to 1×10 19 cm -3 .

[0067] In detail, such as Figure 1 As shown, a portion of the gate oxide layer 4 is located between the first conductive type drift regions 3 in the horizontal direction, a portion is located between the second conductive type body regions 8, and a portion is located between the source metal layers 11; a portion of the auxiliary gate anode oxide layer 5 is located between the first conductive type drift regions 3 in the horizontal direction, and a portion is located between the second conductive type body regions 8, and the horizontal direction is parallel to the direction of the drain metal layer 1.

[0068] In more detail, Figure 1-2 As shown, in the horizontal direction, a portion of the gate oxide layer 4 and the auxiliary gate anode oxide layer 5 are isolated by the first conductive type drift region 3, and a portion are isolated by the second conductive type anode injection region 7, the second conductive type body region 8 and a portion of the source metal layer 11; and a portion of the source metal layer 11 and the second conductive type anode injection region 7 are located between the two second conductive type body regions 8 in the horizontal direction.

[0069] In detail, such as Figure 1-4As shown, the first conductive type gate polysilicon region 9 is isolated from the second conductive type body region 8 in the horizontal direction by a first gate oxide layer 20 formed by the gate oxide layer 4, and the first conductive type auxiliary gate anode polysilicon region 10 is isolated from the second conductive type body region 8 in the horizontal direction by a second gate oxide layer 21 formed by the auxiliary gate anode oxide layer 5, wherein the thickness of the first gate oxide layer 20 is greater than the thickness of the second gate oxide layer 21. Specifically, the thickness of the first gate oxide layer 20 ranges from 40nm to 100nm, and the thickness of the second gate oxide layer 21 ranges from 10nm to 25nm. When the shielded gate metal oxide semiconductor field effect transistor is forward-conducting, a current conduction channel is generated in the first gate oxide layer 20; when the shielded gate metal oxide semiconductor field effect transistor is reverse-conducting, a current conduction channel is generated in the second gate oxide layer 21.

[0070] In detail, such as Figure 2 As shown, the second first groove is provided with an auxiliary gate anode oxide layer 5 and a first conductive type auxiliary gate anode polysilicon region 10, and the auxiliary gate anode oxide layer 5 partially wraps the first conductive type auxiliary gate anode polysilicon region 10. Specifically, as Figure 2 As shown, the size of the first first groove is the same as the size of the second groove, but the size of the first conductive type auxiliary gate anode polysilicon region 10 is larger than that of the first conductive type auxiliary gate anode polysilicon region 10. Figure 1 The size of the first conductive type auxiliary gate anode polysilicon region 10 is shown, and the auxiliary gate anode oxide layer 5 and the first conductive type auxiliary gate anode polysilicon region 10 together constitute an auxiliary gate structure. Since the first conductive type shielding gate polysilicon region 6 is not present in the auxiliary gate structure, the process flow is simpler, the conduction performance of the auxiliary gate remains unchanged, and the cost of the device is reduced.

[0071] In detail, such as Figure 3 As shown, in the horizontal direction, between the gate oxide layer 4 and the auxiliary gate anode oxide layer 5, a portion is isolated by the first conductivity type drift region 3, and a portion is isolated by the second conductivity type body region 8, and the left side of the gate oxide layer 4 is sequentially provided with the second conductivity type body region 8 and the second conductivity type anode injection region 7. Specifically, as Figure 3 As shown, the gate oxide layer 4 in the first first groove and the auxiliary gate anode oxide layer 5 in the second second groove are in the horizontal direction. Since the gate oxide layer 4 and a part of the auxiliary gate anode oxide layer 5 are only isolated by the second conductive type body region 8, the distance between the gate oxide layer 4 and the auxiliary gate anode oxide layer 5 is shortened, thereby improving the shielding effect of the first conductive type shielding gate polysilicon region 6 in the first first groove.

[0072] In more detail, Figure 4As shown, a first conductive type source region 30 is arranged on the second conductive type body region 8, and the source metal layer 11 covers the second conductive type anode injection region 7, part of the second conductive type body region 8, part of the gate oxide layer 4, part of the auxiliary gate anode oxide layer 5, the first conductive type auxiliary gate anode polysilicon region 10 and the first conductive type source region 30; and the first conductive type source region 30 is located between the second conductive type body region 8 and the gate oxide layer 4 in the horizontal direction; wherein, the contact surface between the source metal layer 11 and the first conductive type source region 30 forms an ohmic contact.

[0073] Specifically, the material of the oxide layer used in the shielded gate metal oxide semiconductor field effect transistor is silicon dioxide.

[0074] like Figure 5 As shown, the shielded gate metal oxide semiconductor field effect transistor provided by the present application has a smaller reverse recovery peak current, a shorter reverse recovery time, a lower reverse recovery charge, and better reverse recovery performance compared with the reverse recovery characteristics of the traditional shielded gate metal oxide semiconductor field effect transistor.

[0075] Second, as Figure 6 As shown, the present application also provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, which method at least includes steps S1 to S6:

[0076] S1. Providing a first conductive type substrate layer 2, the first conductive type substrate layer 2 including a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer 2 to form a first conductive type drift region 3;

[0077] S2, forming a second conductivity type body region 8 on the first conductivity type drift region 3 based on ion implantation;

[0078] S3, etching the first conductivity type drift region 3 and the second conductivity type body region 8 to form two first grooves, forming a gate oxide layer 4, a first conductivity type shielding gate polysilicon region 6, and a first conductivity type gate polysilicon region 9 in the first first groove, and forming an auxiliary gate anode oxide layer 5, a first conductivity type shielding gate polysilicon region 6, and a first conductivity type auxiliary gate anode polysilicon region 10 in the second first groove;

[0079] S4, performing ion implantation on a portion of the second conductivity type body region 8 to form a second conductivity type anode implantation region 7;

[0080] S5, etching the second conductive type anode injection region 7, and forming a source metal layer 11 based on metal spraying and annealing;

[0081] S6 , performing metal spraying and annealing on the back side of the first conductive type substrate layer 2 to form a drain metal layer 1 .

[0082] Specifically, if Figure 7 As shown, a first conductive type substrate layer 2 is provided, and a first conductive type drift region 3 is covered on the front surface of the first conductive type substrate layer 2 by epitaxial growth technology; Figure 8 As shown, a second conductive type body region 8 is formed on the first conductive type drift region 3 by ion implantation technology.

[0083] like Figure 9 As shown, the first conductive type drift region 3 and the second conductive type body region 8 are etched to form two first grooves, a gate oxide layer 4 is formed in the first first groove by thermal growth, and polysilicon is deposited by a polysilicon deposition process to form a first conductive type shielding gate polysilicon region 6 on the gate oxide layer 4 in the first first groove. Similarly, thermal growth is first performed to form an auxiliary gate anode oxide layer 5 in the second first groove, and then polysilicon is deposited by a polysilicon deposition process to form a first conductive type shielding gate polysilicon region 6 on the auxiliary gate anode oxide layer 5 in the second first groove; as shown Figure 10 As shown, a dielectric layer deposition process is used to form a gate oxide layer 4 on the first conductive type shielding gate polysilicon region 6 in the first first groove. At the same time, an auxiliary gate anode oxide layer 5 is formed on the first conductive type shielding gate polysilicon region 6 in the second second groove, so as to realize a structure in which the gate oxide layer 4 and the auxiliary gate anode oxide layer 5 wrap the first conductive type shielding gate polysilicon region 6. Through an etching process and a polysilicon precipitation process, a first conductive type gate polysilicon region 9 is formed on the gate oxide layer 4 of the first first groove, and the first conductive type gate polysilicon region 9 is wrapped by the gate oxide layer 4. A first conductive type auxiliary gate anode polysilicon region 10 is formed on the auxiliary gate anode oxide layer 5 in the second first groove, and the first conductive type auxiliary gate anode polysilicon region 10 is partially wrapped by the auxiliary gate anode oxide layer 5.

[0084] like Figure 11 As shown, a second conductive type anode injection region 7 is formed in part of the second conductive type body region 8 by ion implantation, as shown in FIG. Figure 12 As shown, the second conductive type anode injection region 7 is etched to a certain depth, and the second conductive type anode injection region 7, the second conductive type body region 8, the gate oxide layer 4, the auxiliary gate anode oxide layer 5 and the first conductive type auxiliary gate anode polysilicon region 10 are first subjected to metal spraying and then rapid annealing to form a source metal layer 11; the back side of the first conductive type substrate layer 2 is subjected to metal spraying and rapid annealing to form a drain metal layer 1.

[0085] It should be noted that in step S3, the formation of the first conductive type shielding gate polysilicon region 6, the first conductive type gate polysilicon region 9 and the first conductive type auxiliary gate anode polysilicon region 10 also requires in-situ doping or impurity injection followed by annealing to complete the doping. In step S5, the deposited metal can be selected from Pt, PtNi, Ti or TiN.

[0086] In a third aspect, the present application further provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor. The difference between the manufacturing method provided in the second aspect is that the structure formed in the second groove is different, that is, the present method forms an auxiliary gate anode oxide layer 5 and a first conductive type auxiliary gate anode polysilicon region 10 in the second first groove. Specifically, in combination with Figure 2 In step S3, the structure in the second first groove is formed by first performing thermal growth to form an auxiliary gate anode oxide layer 5 in the second first groove, and then forming a first conductive type auxiliary gate anode polysilicon region 10 on the auxiliary gate anode oxide layer 5 in the second first groove through an etching process and a polysilicon precipitation process. The first conductive type auxiliary gate anode polysilicon region 10 is partially wrapped by the auxiliary gate anode oxide layer 5.

[0087] In a fourth aspect, the present application further provides a method for manufacturing a shielded gate metal oxide semiconductor field effect transistor. The difference between the manufacturing method provided in the third aspect is that the structure formed after ion implantation of the second conductive type body region 8 in step S4 is different, that is, ion implantation is performed on part of the second conductive type body region 8 to form a second conductive type anode implantation region 7 and a first conductive type source region 30. Specifically, in combination with Figure 4 In step S4 , a second conductive type anode injection region 7 and a first conductive type source region 30 are formed in a portion of the second conductive type body region 8 by ion implantation.

[0088] The present application provides a shielded-gate metal-oxide-semiconductor field-effect transistor and a method for manufacturing the same. The semiconductor field-effect transistor incorporates an auxiliary gate, which acts as a reverse-conducting diode. When the device is reverse-conducting, the auxiliary gate preferentially conducts due to its lower turn-on voltage. As a unipolar conduction diode, this reduces the hole concentration within the device, thereby significantly improving the reverse recovery performance of a conventional shielded-gate metal-oxide-semiconductor field-effect transistor. Furthermore, because the source metal layer forms a Schottky contact with the second-conductivity-type body region, the impact of the parasitic triode structure in the conventional structure is reduced, thereby improving the device's operational reliability.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A shielded gate metal oxide semiconductor field effect transistor, characterized in that: include: A drain metal layer, and a first conductive type substrate layer and a first conductive type drift region sequentially stacked on the drain metal layer; Two first grooves are provided in the first conductive type drift region; A gate oxide layer, a first conductivity type shielding gate polysilicon region, and a first conductivity type gate polysilicon region are provided in the first first groove, the gate oxide layer wraps the first conductivity type shielding gate polysilicon region and the first conductivity type gate polysilicon region, the first conductivity type gate polysilicon region is located on the first conductivity type shielding gate polysilicon region and is isolated by the gate oxide layer; An auxiliary gate anode oxide layer, a first conductivity type shielding gate polysilicon region, and a first conductivity type auxiliary gate anode polysilicon region are provided in the second first groove, the auxiliary gate anode oxide layer wraps the first conductivity type shielding gate polysilicon region and a portion of the first conductivity type auxiliary gate anode polysilicon region, the first conductivity type auxiliary gate anode polysilicon region is located on the first conductivity type shielding gate polysilicon region and is isolated by the auxiliary gate anode oxide layer; A second conductive type anode injection region and a second conductive type body region are provided on the first conductive type drift region; A source metal layer is provided on the gate oxide layer, the auxiliary gate anode oxide layer, the second conductive type anode injection region, the second conductive type body region, and the first conductive type auxiliary gate anode polysilicon region.

2. The shielded gate metal oxide semiconductor field effect transistor according to claim 1, wherein: In the horizontal direction, a portion of the gate oxide layer is located between the first conductive type drift regions, a portion is located between the second conductive type body regions, and a portion is located between the source metal layers; A portion of the auxiliary gate anode oxide layer is located between the first conductive type drift regions and a portion is located between the second conductive type body regions in the horizontal direction. The horizontal direction is parallel to the drain metal layer.

3. The shielded gate metal oxide semiconductor field effect transistor according to claim 2, wherein: In the horizontal direction, a portion of the gate oxide layer and the auxiliary gate anode oxide layer is isolated by the first conductive type drift region, and a portion is isolated by the second conductive type anode injection region, the second conductive type body region and a portion of the source metal layer; and a portion of the source metal layer and the second conductive type anode injection region are located between two second conductive type body regions in the horizontal direction.

4. The shielded gate metal oxide semiconductor field effect transistor according to claim 2, wherein: The first conductive type gate polysilicon region is isolated from the second conductive type body region in the horizontal direction by a first gate oxide layer formed by the gate oxide layer, and the first conductive type auxiliary gate anode polysilicon region is isolated from the second conductive type body region in the horizontal direction by a second gate oxide layer formed by the auxiliary gate anode oxide layer, wherein the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

5. The shielded gate metal oxide semiconductor field effect transistor according to claim 1, wherein: An auxiliary gate anode oxide layer and a first conductivity type auxiliary gate anode polysilicon region are provided in the second first groove, and the auxiliary gate anode oxide layer partially wraps the first conductivity type auxiliary gate anode polysilicon region.

6. The shielded gate metal oxide semiconductor field effect transistor according to claim 2, wherein: In the horizontal direction, the gate oxide layer and the auxiliary gate anode oxide layer are partially isolated by the first conductive type drift region and partially isolated by the second conductive type body region, and the second conductive type body region and the second conductive type anode injection region are sequentially arranged on the left side of the gate oxide layer.

7. The shielded gate metal oxide semiconductor field effect transistor according to claim 6, wherein: A first conductive type source region is arranged on the second conductive type body region, and the source metal layer covers the second conductive type anode injection region, part of the second conductive type body region, part of the gate oxide layer, part of the auxiliary gate anode oxide layer, the first conductive type auxiliary gate anode polysilicon region and the first conductive type source region; and the first conductive type source region is between the second conductive type body region and the gate oxide layer in the horizontal direction.

8. A method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, characterized in that: include: S1. Providing a first conductive type substrate layer, wherein the first conductive type substrate layer includes a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer to form a first conductive type drift region; S2. forming a second conductive type body region on the first conductive type drift region based on ion implantation; S3, etching the first conductive type drift region and the second conductive type body region to form two first grooves, forming a gate oxide layer, a first conductive type shielding gate polysilicon region, and a first conductive type gate polysilicon region in the first first groove, and forming an auxiliary gate anode oxide layer, the first conductive type shielding gate polysilicon region, and a first conductive type auxiliary gate anode polysilicon region in the second first groove; S4, performing ion implantation on a portion of the second conductive type body region to form a second conductive type anode implantation region; S5, etching the second conductive type anode injection region to form a source metal layer based on metal spraying and annealing; S6. Perform metal spraying and annealing on the back side of the first conductive type substrate layer to form a drain metal layer.

9. A method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, characterized in that: include: S1. Providing a first conductive type substrate layer, wherein the first conductive type substrate layer includes a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer to form a first conductive type drift region; S2. forming a second conductive type body region on the first conductive type drift region based on ion implantation; S3, etching the first conductive type drift region and the second conductive type body region to form two first grooves, forming a gate oxide layer, a first conductive type shielding gate polysilicon region, and a first conductive type gate polysilicon region in the first first groove, and forming an auxiliary gate anode oxide layer and a first conductive type auxiliary gate anode polysilicon region in the second first groove; S4, performing ion implantation on a portion of the second conductive type body region to form a second conductive type anode implantation region; S5, etching the second conductive type anode injection region to form a source metal layer based on metal spraying and annealing; S6. Perform metal spraying and annealing on the back side of the first conductive type substrate layer to form a drain metal layer.

10. A method for manufacturing a shielded gate metal oxide semiconductor field effect transistor, characterized in that: include: S1. Providing a first conductive type substrate layer, wherein the first conductive type substrate layer includes a front surface and a back surface opposite to each other, performing epitaxial growth on the front surface of the first conductive type substrate layer to form a first conductive type drift region; S2. forming a second conductive type body region on the first conductive type drift region based on ion implantation; S3, etching the first conductive type drift region and the second conductive type body region to form two first grooves, forming a gate oxide layer, a first conductive type shielding gate polysilicon region, and a first conductive type gate polysilicon region in the first first groove, and forming an auxiliary gate anode oxide layer and a first conductive type auxiliary gate anode polysilicon region in the second first groove; S4, performing ion implantation on a portion of the second conductive type body region to form a second conductive type anode implantation region and a first conductive type source region; S5, etching the second conductive type anode injection region to form a source metal layer based on metal spraying and annealing; S6. Perform metal spraying and annealing on the back side of the first conductive type substrate layer to form a drain metal layer.

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