A circuit for generating a high voltage chopper switch control signal

Abstract

The present invention relates to the field of semiconductor technology, and more specifically, to a circuit for generating a control signal of a high-voltage chopper switch. The circuit includes a high-voltage chopper switch and a driving circuit for driving the high-voltage chopper switch to generate a chopper signal. The circuit is characterized in that the switch tube of the high-voltage chopper switch is a low-voltage tube, the driving circuit includes an input chopper switch clock level shifting circuit, the input chopper switch clock level shifting circuit is adaptively connected to the switch tube of the high-voltage chopper switch, and is used to send a high-voltage domain positive-phase clock signal Clkp and a high-voltage domain negative-phase clock signal Clkn to the switch tube of the high-voltage chopper switch, and the driving circuit includes a floating voltage source, and the floating voltage source inputs a variable common-mode input voltage V CM , forming a common-mode input voltage V CM The voltage source V DDL and voltage source V SSL , voltage source V DDL and voltage source V SSL The circuit is used as a voltage source for the input chopping switch clock level shift circuit. The mismatch problem can be improved by using the circuit.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a circuit for generating a high-voltage chopper switch control signal. Background Art

[0002] In precision op amp circuits, chopping technology is often used to achieve high precision requirements. Unlike low-voltage chopping systems, chopping switches in high-voltage circuits require good voltage resistance. The high-voltage voltage resistance mentioned here is reflected in the voltage resistance between the source and drain of the transistor, as well as the voltage resistance between the gate and source of the transistor. In the standard 5V CMOS process, the maximum source-drain voltage and the maximum gate-source voltage of MOS transistors are both 5V; in the high-voltage 40V CMOS process, the maximum source-drain voltage of DMOS transistors is 40V, and the maximum gate-source voltage is 5V.

[0003] To provide a suitable chopper switch under high power supply voltage, the prior art uses a high voltage chopper switch structure driven by a high voltage amplifier level conversion, such as Figure 1 As shown, the chopper switch in this structure is realized by using DMOS transistors. The principle of the high-voltage chopper switch structure driven by the high-voltage amplifier level conversion is to obtain the amplified clock signal at node A by inputting complementary clock signals OFF / ON to MN3 and MN4. Because the maximum gate-source voltage of the DMOS transistor used in the circuit is 5V, the clock swing at node A needs to be limited. Specifically, by using MN2, the minimum gate-source voltage of MN0 and MN 1 is limited to -Vthn2 (the threshold voltage of MN2); and by using D1-D3 and MP1, the maximum gate-source voltage of MN0 and MN01 is limited to 3Vthd+Vthp (where Vthd is the threshold voltage of D1-3 and Vthp is the threshold voltage of MP1). However, the chopper switch of this structure needs to use DMOS high-voltage tubes, which will produce larger parasitic capacitance and introduce greater mismatch to the circuit. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a circuit for generating a high-voltage chopper switch control signal, which can improve the mismatch problem.

[0005] In order to solve the above problems, the following technical solutions are provided:

[0006] The circuit for generating a high-voltage chopper switch control signal of the present invention includes a high-voltage chopper switch and a driving circuit for driving the high-voltage chopper switch to generate a chopper signal. It is characterized in that the switch tube of the high-voltage chopper switch is a low-voltage tube, and the driving circuit contains an input chopper switch clock level shifting circuit. The input chopper switch clock level shifting circuit is adaptively connected to the switch tube of the high-voltage chopper switch, and is used to send a high-voltage domain positive-phase clock signal Clkp and a high-voltage domain negative-phase clock signal Clkn to the switch tube of the high-voltage chopper switch; the driving circuit contains a floating voltage source, and the floating voltage source inputs a variable common-mode input voltage V CM , forming a common-mode input voltage V CM The voltage source V DDL and voltage source V SSL ; The voltage source V DDL and voltage source V SSL Used as a voltage source for the input chopper switch clock level shift circuit.

[0007] The floating voltage source includes a resistor R0 and a current source I1. The input end of the current source I1 is connected to the driving power supply VDD, the output end of the current source I1 is connected to one end of the resistor R0, the other end of the resistor R0 is connected to the drain of the MOS transistor MN0, the drain of the MOS transistor MN0 is connected to the gate of the MOS transistor MN0, and the source of the MOS transistor MN0 is connected to the source of the MOS transistor MP1 and the source of the MOS transistor MP0 respectively. The gate of the MOS transistor MP1 inputs the common mode input voltage V CM The drain of the MOS tube MP1 is grounded to VSS. The gate of the MOS tube MP0 is connected to the drain of the MOS tube MP0, the drain of the MOS tube MP0 is connected to the input end of the current source I2, and the output end of the current source I2 is grounded to VSS. The input end of the current source I1 forms the voltage source V DDL The gate of the MOS tube MP0 forms the voltage source V SSL .

[0008] The switch tubes of the high-voltage chopper switch include MOS tube MN1, MOS tube MN2, MOS tube MN3 and MOS tube MN4. The gates of the MOS tube MN1 and MOS tube MN3 are connected to the high-voltage domain inverse clock signal Clkn, and the gates of the MOS tube MN2 and MOS tube MN4 are connected to the high-voltage domain positive clock signal Clkp. The drains of the MOS tube MN1 and MOS tube MN4 are both connected to the input signal V inp The drains of the MOS transistors MN2 and MN3 are both connected to the input signal V inn The source electrodes of the MOS transistor MN1 and the MOS transistor MN2 form an output signal V outp The source electrodes of the MOS transistors MN3 and MN4 form the output signal Voutn .

[0009] The input chopping switch clock level shift circuit comprises a NAND gate NAND1 and a NAND gate NAND2; the voltage source V DDL The first input end of the NAND gate NAND1 is connected to one end of the capacitor C1 through the current mirror I3, and the other end of the capacitor C1 is connected to the low-voltage positive-phase clock signal Clkp0, and the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND2. DDL The first input end of the NAND gate NAND2 is connected through the current mirror I4, the first input end of the NAND gate NAND1 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the low-voltage inverted clock signal Clkn0, and the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND1. The output end of the NAND gate NAND1 forms the high-voltage domain positive-phase clock signal Clkp, and the output end of the NAND gate NAND2 forms the high-voltage domain inverted clock signal Clkn.

[0010] The amplitudes of the low voltage positive phase clock signal Clkp0 and the low voltage negative phase clock signal Clkn0 are within 5V, and the voltage of the low voltage positive phase clock signal Clkp0 is less than 5V. The amplitudes of the high voltage domain positive phase clock signal Clkp and the high voltage domain negative phase clock signal Clkn are within 5V.

[0011] The above solution has the following advantages:

[0012] Since the switch tube of the high-voltage chopper switch of the high-voltage chopper switch control signal generating circuit of the present invention is a low-voltage tube, the driving circuit includes an input chopper switch clock level shift circuit, the input chopper switch clock level shift circuit is adaptively connected to the switch tube of the high-voltage chopper switch, and is used to send a high-voltage domain positive-phase clock signal Clkp and a high-voltage domain negative-phase clock signal Clkn to the switch tube of the high-voltage chopper switch, and the driving circuit includes a floating voltage source, and the floating voltage source inputs a variable common-mode input voltage V CM , forming a common-mode input voltage V CM The voltage source V DDL and voltage source V SSL , voltage source V DDL and voltage source V SSL Used as the voltage source for the input chopper switch clock level shift circuit. This circuit uses a floating voltage source V DDL and voltage source V SSL As the driving voltage source of the input chopper switch clock level shift circuit, the high and low level voltage difference V DDL -V SSLWithin 5V, and works with the common-mode input V CM Floating V SSL ~V DDL In the high voltage domain, the source of the low voltage switch is connected to the input signal V inp 、Input signal V inn is the common mode input voltage V CM , thereby ensuring that the gate-source of the low-voltage switch tube has no withstand voltage problem, so that the switch tube of the high-voltage chopper switch uses an ordinary low-voltage tube, which has smaller parasitic capacitance and smaller mismatch than the high-voltage tube used in the background technology. Moreover, with the common-mode input voltage V CM The voltage source V DDL and voltage source V SSL The floating voltage source whose output varies with the reference voltage can be adapted to more application occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a circuit diagram of a high-voltage chopper switch structure driven by a high-voltage amplifier level conversion in the background technology;

[0014] Figure 2 It is a schematic diagram of a circuit for generating a high-voltage chopper switch control signal of the present invention;

[0015] Figure 3 The present invention is a schematic diagram of a level shift circuit for inputting a chopper switch clock in a circuit for generating a high-voltage chopper switch control signal. DETAILED DESCRIPTION

[0016] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0017] like Figure 2 As shown, the circuit for generating a high-voltage chopper switch control signal of the present invention includes a high-voltage chopper switch and a driving circuit for driving the high-voltage chopper switch to generate a chopper signal. The high-voltage chopper switch includes a MOS tube MN1, a MOS tube MN2, a MOS tube MN3 and a MOS tube MN4. The MOS tube MN1, the MOS tube MN2, the MOS tube MN3 and the MOS tube MN4 are all low-voltage tubes, and they are all switch tubes of the high-voltage chopper switch. Using a low-voltage tube as a switch tube has smaller parasitic capacitance and smaller mismatch than a high-voltage tube.

[0018] like Figure 2 As shown, the driving circuit includes an input chopping switch clock level shift circuit and a floating voltage source. The floating voltage source is adaptively connected to the input chopping switch clock level shift circuit, and the floating voltage source inputs a variable common-mode input voltage V CM , forming a common-mode input voltage V CM The voltage source VDDL and voltage source V SSL . Voltage source V DDL and voltage source V SSL As a voltage source for the input chopper switch clock level shift circuit. The input chopper switch clock level shift circuit is adaptively connected to the switch tube of the high-voltage chopper switch, and is used to send a high-voltage domain positive phase clock signal Clkp and a high-voltage domain negative phase clock signal Clkn to the switch tube of the high-voltage chopper switch.

[0019] like Figure 2 As shown, in this embodiment, the gates of MOS transistors MN1 and MOS transistors MN3 are connected to the high-voltage domain inverted clock signal Clkn, and the gates of MOS transistors MN2 and MOS transistors MN4 are connected to the high-voltage domain positive clock signal Clkp. The drains of MOS transistors MN1 and MOS transistors MN4 are both connected to the input signal V inp The drains of MOS tube MN2 and MOS tube MN3 are connected to the input signal V inn The source of MOS transistor MN1 and MOS transistor MN2 forms the output signal V outp。 The source electrodes of MOS transistors MN3 and MOS transistors MN4 form the output signal V outn .

[0020] like Figure 2 As shown, in this embodiment, the floating voltage source includes a resistor R0 and a current source I1. The input end of the current source I1 is connected to the driving power supply VDD, the output end of the current source I1 is connected to one end of the resistor R0, the other end of the resistor R0 is connected to the drain of the MOS transistor MN0, the drain of the MOS transistor MN0 is connected to the gate of the MOS transistor MN0, and the source of the MOS transistor MN0 is connected to the source of the MOS transistor MP1 and the source of the MOS transistor MP0 respectively. The gate of the MOS transistor MP1 inputs the common mode input voltage V CM , the drain of MOS tube MP1 is grounded to VSS. The gate of MOS tube MP0 is connected to the drain of MOS tube MP0, the drain of MOS tube MP0 is connected to the input end of current source I2, and the output end of current source I2 is grounded to VSS. The input end of current source I1 forms a voltage source V DDL , the gate of MOS tube MP0 forms a voltage source V SSL .

[0021] like Figure 3 As shown, the input chopping switch clock level shift circuit includes a NAND gate NAND1 and a NAND gate NAND2, and the NAND gate NAND1 and the NAND gate NAND2 are driven by a voltage source V DDL and voltage source V SSL Driver. Voltage source V DDLThe first input terminal of the NAND gate NAND1 is connected to one end of the capacitor C1 through the current mirror I3, and the other end of the capacitor C1 is connected to the low voltage positive phase clock signal Clkp0, and the second input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate NAND2. DDL The first input end of the NAND gate NAND2 is connected through the current mirror I4, the first input end of the NAND gate NAND1 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the low-voltage inverted clock signal Clkn0, and the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND1. The output end of the NAND gate NAND1 forms the high-voltage domain positive-phase clock signal Clkp, and the output end of the NAND gate NAND2 forms the high-voltage domain inverted clock signal Clkn. The amplitudes of the low-voltage positive-phase clock signal Clkp0 and the low-voltage inverted clock signal Clkn0 are within 5V, and the voltage of the low-voltage positive-phase clock signal Clkp0 is less than 5V. The amplitudes of the high-voltage domain positive-phase clock signal Clkp and the high-voltage domain inverted clock signal Clkn are within 5V, for example, the high-voltage domain positive-phase clock signal Clkp is 25V, and the high-voltage domain inverted clock signal Clkp is 20V.

[0022] like Figure 2 As shown, the principle of the circuit is that between the power supply voltage VDD and the ground VSS, the sum of the overall current of the circuit is I BIAS1 =I BIAS2 +I BIAS3 The gate voltage of MOS tube MP1 is a variable common-mode input voltage V CM , set the leakage current flowing through MP1 to I BIAS3 , the leakage current flowing through the MOS tube MP0 is I BIAS2 . According to the leakage current calculation formula:

[0023] ;

[0024] Leakage current I D If the MOS tube V GS The leakage current I of MP1 is BIAS3 Certainly, its V GS Determined, because the gate voltage is a variable reference voltage V CM , then the source voltage of MP1 V1=V CM +V GS_MP1 Similarly, the leakage current I BIAS2 Certainly, its V GS Since the source voltage is V1, the gate voltage of MP0 is V SSL =V1-V GS_MP0 Substituting the formula of V1, we can get V SSL With input voltage VCM The relationship is:

[0025] ;

[0026] At this time, because the current I flowing through MN0 and R0 BIAS1 Yes, MN0 V GS Determine, because the source voltage is V1, then the gate voltage of MN0 is V2=V1+V GS_MN0 In addition, the voltage drop across resistor R0 is V R =I BIAS1 *R0.

[0027] Output voltage V DDL =V2+V R Substituting the formula of V1, we can get V DDL With input voltage V CM The relationship is:

[0028] ;

[0029] Therefore, by properly setting the current I BIAS2 and I BIAS3 , resistor R0, can be obtained with V CM The voltage source V DDL 、V SSL In a high-voltage circuit, when a voltage source that changes with the reference voltage is required, this structure ensures the flexibility and reliability of the circuit. And ordinary low-voltage transistors are used as switch tubes, with smaller parasitics and smaller mismatch. In this embodiment, V DDL -V SSL ≤5V.

[0030] The chopper switch of this solution uses ordinary tubes, which have smaller parasitic capacitance and smaller mismatch than high-voltage tubes. Moreover, it can output a floating voltage source that changes with the reference voltage, and the output voltage difference is adjustable, which can adapt to more occasions.

Claims

1. A circuit for generating a high-voltage chopper switch control signal, comprising a high-voltage chopper switch and a driving circuit for driving the high-voltage chopper switch to generate a chopper signal; characterized in that: The switch tube of the high-voltage chopper switch is a low-voltage tube, and the driving circuit includes an input chopper switch clock level shift circuit; the input chopper switch clock level shift circuit is adaptively connected to the switch tube of the high-voltage chopper switch, and is used to send a high-voltage domain positive-phase clock signal Clkp and a high-voltage domain negative-phase clock signal Clkn to the switch tube of the high-voltage chopper switch; the driving circuit includes a floating voltage source, and the floating voltage source inputs a variable common-mode input voltage V CM , forming a common-mode input voltage V CM The voltage source V DDL and voltage source V SSL ; The voltage source V DDL and voltage source V SSL The floating voltage source is used as the voltage source of the input chopper switch clock level shift circuit; the floating voltage source includes a resistor R0 and a current source I1; the input end of the current source I1 is connected to the driving power supply VDD, the output end of the current source I1 is connected to one end of the resistor R0, the other end of the resistor R0 is connected to the drain of the MOS tube MN0, the drain of the MOS tube MN0 is connected to the gate of the MOS tube MN0, the source of the MOS tube MN0 is respectively connected to the source of the MOS tube MP1 and the source of the MOS tube MP0; the gate of the MOS tube MP1 inputs the common mode input voltage V CM , the drain of MOS tube MP1 is grounded to VSS; the gate of MOS tube MP0 is connected to the drain of MOS tube MP0, the drain of MOS tube MP0 is connected to the input end of current source I2, and the output end of current source I2 is grounded to VSS; the input end of current source I1 forms the voltage source V DDL The gate of the MOS tube MP0 forms the voltage source V SSL The switch tubes of the high-voltage chopper switch include MOS tube MN1, MOS tube MN2, MOS tube MN3 and MOS tube MN4; the gates of the MOS tube MN1 and MOS tube MN3 are connected to the high-voltage domain inverse clock signal Clkn, and the gates of the MOS tube MN2 and MOS tube MN4 are connected to the high-voltage domain positive clock signal Clkp; the drains of the MOS tube MN1 and MOS tube MN4 are both connected to the input signal V inp The drains of the MOS tube MN2 and the MOS tube MN3 are both connected to the input signal V inn The source electrodes of the MOS transistor MN1 and the MOS transistor MN2 form an output signal V outp The source electrodes of the MOS tube MN3 and the MOS tube MN4 form an output signal V outn .

2. The high voltage chopper switch control signal generating circuit according to claim 1, characterized in that: The input chopping switch clock level shift circuit comprises a NAND gate NAND1 and a NAND gate NAND2; the voltage source V DDL The current mirror I3 is connected to the first input terminal of the NAND gate NAND1, the first input terminal of the NAND gate NAND1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the low-voltage positive-phase clock signal Clkp0, and the second input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate NAND2; the voltage source V DDL The first input end of the NAND gate NAND2 is connected to the current mirror I4, the first input end of the NAND gate NAND1 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the low-voltage inverted clock signal Clkn0, and the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND1; the output end of the NAND gate NAND1 forms the high-voltage domain positive-phase clock signal Clkp, and the output end of the NAND gate NAND2 forms the high-voltage domain inverted clock signal Clkn.

3. The high voltage chopper switch control signal generating circuit according to claim 2, characterized in that: The amplitudes of the low-voltage positive-phase clock signal Clkp0 and the low-voltage negative-phase clock signal Clkn0 are within 5V, and the voltage of the low-voltage positive-phase clock signal Clkp0 is less than 5V; the amplitudes of the high-voltage domain positive-phase clock signal Clkp and the high-voltage domain negative-phase clock signal Clkn are within 5V.

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