Memory formation method

Abstract

An embodiment of the present disclosure provides a method for forming a memory, which includes: providing a first substrate; forming a transistor array with a vertical gate on the surface of the first substrate; bonding a carrier substrate to the surface of the transistor array; removing the first substrate and forming a capacitor structure electrically connected to the transistor array; wherein the first substrate is used as a first sacrificial layer for forming the capacitor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to, but not limited to, a method for forming a memory. Background Art

[0002] With the continuous advancement of science and technology, semiconductor devices are widely used in various electronic devices and products. Dynamic random access memory (DRAM), a volatile memory, is a commonly used semiconductor memory device in computers. The memory array in DRAM consists of many repeated memory cells, each of which typically includes a capacitor and a transistor.

[0003] To improve the storage capacity of memory, semiconductor devices are generally required to have higher integration density and smaller feature sizes. Therefore, a new solution is needed in process technology to achieve further increase in DRAM storage density. Summary of the Invention

[0004] In view of this, an embodiment of the present disclosure provides a method for forming a memory, comprising: providing a first substrate; forming a transistor array with a vertical gate on the surface of the first substrate; bonding a carrier substrate to the surface of the transistor array; removing the first substrate and forming a capacitor structure electrically connected to the transistor array; wherein the first substrate is used as a first sacrificial layer for forming the capacitor structure.

[0005] In some embodiments, removing the first substrate and forming a capacitor structure electrically connected to the transistor array includes: forming a plurality of first through holes penetrating the first substrate; wherein each transistor in the transistor array is exposed from the bottom of the first through hole; forming a first electrode connected to the transistor in the first through hole; removing the remaining first sacrificial layer; forming a dielectric layer covering at least the surface of the first electrode; forming a second electrode covering the outer surface of the dielectric layer; wherein the first electrode, the dielectric layer and the second electrode constitute the capacitor structure.

[0006] In some embodiments, the forming of multiple first through holes passing through the first substrate includes: forming a stacked first supporting layer, a second sacrificial layer, and a second supporting layer in sequence on a side of the first substrate away from the transistor array; and forming multiple first through holes passing through the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer.

[0007] In some embodiments, forming a first electrode connected to the transistor in the first through hole includes: filling the first through hole with a conductive material until the conductive material covers the surface of the transistor array layer on the side away from the carrier substrate, forming a conductive column filled in the first through hole and a conductive layer connecting each of the conductive columns; removing the conductive layer, retaining the conductive columns, and forming a plurality of first electrodes.

[0008] In some embodiments, after forming the first electrode connected to the transistor in the first through hole, removing the remaining first sacrificial layer specifically includes: removing the remaining first sacrificial layer and the second sacrificial layer.

[0009] In some embodiments, removing the remaining first sacrificial layer and the second sacrificial layer includes: forming a plurality of second through holes passing through the first supporting layer, the second sacrificial layer, the second supporting layer and the first sacrificial layer; wherein the second through holes are spaced apart from the first through holes; and etching from the second through holes toward one side of the first electrode to remove the remaining first sacrificial layer and the second sacrificial layer.

[0010] In some embodiments, the forming of the dielectric layer that covers at least the surface of the first electrode includes: depositing a dielectric material on the surface of the second supporting layer and the inner wall surface of the second through hole to form the dielectric layer; wherein the dielectric layer covers at least a portion of the surface of the first electrode, the outer surfaces of the first supporting layer and the second supporting layer, and the surface of the transistor array exposed from the bottom of the second through hole.

[0011] In some embodiments, forming the second electrode covering the outer surface of the dielectric layer includes: depositing a conductive material on the outer surface of the dielectric layer to form the second electrode.

[0012] In some embodiments, forming a transistor array with a vertical gate on the surface of the first substrate includes: forming a third supporting layer on the surface of the first substrate; forming the transistor array with a vertical gate on the third supporting layer, wherein each transistor in the transistor array passes through the third supporting layer.

[0013] In some embodiments, the transistor array with a vertical gate formed on the third supporting layer includes: forming a plurality of semiconductor pillars spaced apart from each other on the third supporting layer; doping the semiconductor pillars to sequentially form a drain region, a channel region, and a source region in a direction from the first substrate toward the carrier substrate; forming a surrounding gate insulating layer on the outside of the channel region; forming a surrounding gate layer on the outside of the gate insulating layer; wherein the doped semiconductor pillars, the gate insulating layer, and the gate layer constitute the transistor array; the gate layer electrically connects a plurality of transistors arranged in a first direction parallel to the surface of the first substrate.

[0014] In some embodiments, the formation method further includes: forming a plurality of bit lines on a side of the transistor array away from the first substrate; wherein the bit lines are electrically connected to a plurality of transistors in the transistor array arranged along a second direction parallel to the surface of the first substrate.

[0015] In the memory formation method provided by the embodiments of the present disclosure, a carrier substrate is bonded to the surface of the transistor array, and then the first substrate is removed to form a capacitor structure connected to the transistor array, wherein the first substrate serves as the first sacrificial layer for forming the capacitor structure. This, on the one hand, allows for a higher level of integration of the transistor array with vertical gates, which helps reduce the area occupied by memory cells and improves the storage density of the memory. On the other hand, by bonding the transistor array to the carrier substrate and removing the first substrate as the first sacrificial layer, process steps are saved, further optimizing the process of forming the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a method for forming a memory according to an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of a process for providing a first substrate according to an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of a process for forming a third supporting layer provided in an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of a process for forming a transistor array according to an embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of a process for forming a bit line according to an embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a process for forming a carrier substrate provided in an embodiment of the present disclosure;

[0022] Figure 7 A schematic diagram of a process for bonding a transistor array and a carrier substrate provided in an embodiment of the present disclosure;

[0023] Figure 8 A schematic diagram of a process for thinning the back side of a first substrate provided in an embodiment of the present disclosure;

[0024] Figure 9 A schematic diagram of a process for forming a support layer and a sacrificial layer provided in an embodiment of the present disclosure;

[0025] Figure 10 A schematic diagram of a process for forming a first through hole provided in an embodiment of the present disclosure;

[0026] Figure 11 A schematic diagram of a process for filling a first through hole with a conductive material according to an embodiment of the present disclosure;

[0027] Figure 12 A schematic diagram of a process for forming a first electrode provided in an embodiment of the present disclosure;

[0028] Figure 13 A schematic diagram of a process for forming a second through hole provided in an embodiment of the present disclosure;

[0029] Figure 14 A schematic diagram of the distribution of second through holes on the XY plane provided by an embodiment of the present disclosure;

[0030] Figure 15 A schematic diagram of a process for removing a sacrificial layer provided in an embodiment of the present disclosure;

[0031] Figure 16 A schematic diagram of a process for forming a capacitor structure according to an embodiment of the present disclosure;

[0032] Figure 17 A schematic diagram of a process for forming an electrode filling layer provided in an embodiment of the present disclosure;

[0033] Figure 18 A schematic diagram of a process for removing excess semiconductor material provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0035] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0036] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0037] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0039] First, as Figure 1 As shown, the embodiment of the present disclosure provides a method for forming a memory 10, and its corresponding structure is as follows Figures 2 to 16 As shown, the forming method includes the following steps:

[0040] Step S10: providing a first substrate 100;

[0041] Step S20 , forming a transistor array 200 having vertical gates on a surface of the first substrate 100 ;

[0042] Step S30 , bonding the carrier substrate 300 to the surface of the transistor array 200 ;

[0043] Step S40 , removing the first substrate 100 and forming a capacitor structure 400 electrically connected to the transistor array 200 ; wherein the first substrate 100 is used as a first sacrificial layer 100 a for forming the capacitor structure.

[0044] It should be understood that Figure 1 The steps shown in are not exclusive, and other steps may be performed before, after, or between any steps in the shown operations. In addition, in order to clearly illustrate each structure in the drawings, the size ratio relationship of each structure may not be consistent with the actual structure. In order to clearly describe the present disclosure, the following embodiments are described as follows: the first direction is the Y direction in the drawings, the second direction is the X direction in the drawings, and the thickness direction of the substrate is the Z direction. However, it should be noted that the description of the directions in the following embodiments is only used to illustrate the present disclosure and is not intended to limit the scope of the present disclosure.

[0045] like Figure 2 As shown, a first substrate 100 is provided. The material of the first substrate 100 may include a single semiconductor material, such as silicon (Si), germanium (Ge), etc., or a compound semiconductor material, such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc. In some embodiments, the first substrate 100 may also be doped, or include doped regions and undoped regions in the substrate.

[0046] like Figures 3 to 5As shown, a transistor array 200 with a vertical gate can be formed on the surface of the first substrate 100 by using processes such as deposition, doping, photolithography, and etching. The specific method of forming the transistor array 200 is detailed in the embodiments below. For example, a vertical all-around gate (Gate All Around, GAA) can be formed in the transistor array 200. It can be understood that the direction of the semiconductor column in the transistor here can be perpendicular to the substrate surface, that is, the direction of the semiconductor column is parallel to the Z direction, and the gate surrounds the outside of the channel region of the semiconductor column. The gates of multiple transistors arranged along the Y direction can be connected to each other, that is, as word lines (WL) of the memory. In this way, the transistor array 200 with a vertical gate has a higher degree of integration, which is conducive to reducing the occupied area of ​​the memory cell to improve the storage density of the memory. In some embodiments, after the transistor array 200 is formed on the surface of the first substrate 100, a plurality of bit lines BL can also be formed on the side of the transistor array 200 away from the first substrate 100. The etching process in the present disclosure can be divided into dry etching (Dry Etching) and wet etching (Wet Etching). Among them, dry etching can include ion milling etching (Ion Neam Milling Etching), plasma etching (Plasma Etching), reactive ion etching (Reactive Ion Etching) or laser ablation (Laser Ablation), etc.; wet etching is to use solvents or solutions for etching, such as acid and alkali solutions. Deposition processes include but are not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD) or physical vapor deposition (Physical Vapor Deposition, PVD), etc. Doping processes include but are not limited to thermal diffusion, ion implantation, etc.

[0047] like Figure 7 As shown, a carrier substrate 300 can be bonded to the surface of the transistor array 200 using face-to-back bonding technology. In other words, the front side of the device wafer is bonded to the back side of the carrier wafer. Compared to face-to-face wafer bonding, face-to-back wafer bonding requires simpler process steps and is less expensive. It is understood that the carrier substrate 300 can be another wafer without semiconductor devices formed thereon.

[0048] like Figures 8 to 16As shown, the first substrate 100 can be removed by etching or other processes, and a capacitor structure 400 electrically connected to the transistor array 200 can be formed by deposition, photolithography, etching or other processes. The first substrate 100 is used as a first sacrificial layer 100a for forming the capacitor structure 400, and the step of removing the first substrate 100 can be between multiple steps of forming the capacitor structure 400. That is, in the process of forming the capacitor structure 400, the first substrate 100 can be completely removed, and the finally formed memory is carried by the carrier substrate 300. For example, after the transistor array 200 is bonded to the carrier substrate 300, a plurality of support layers and sacrificial layers arranged at intervals can be formed on the side of the first substrate 100 away from the carrier substrate 300, and then a first electrode that penetrates the plurality of support layers and sacrificial layers and is connected to the transistor is formed, and then the plurality of sacrificial layers including the first substrate 100 are removed, thereby forming a dielectric layer and a second electrode on the surface of the first electrode and each support layer to form the capacitor structure 400. In this way, by bonding the transistor array 200 and the carrier substrate 300 and removing the first substrate 100 serving as the first sacrificial layer 100a, the manufacturing process of the capacitor structure can be further simplified; in addition, after removing the first substrate 100 and each sacrificial layer, each supporting layer and the first electrode increase the coverage area of ​​the subsequently formed second electrode, thereby increasing the capacitance and thus improving the performance of the memory.

[0049] In some embodiments, as Figure 3 and Figure 4 As shown, a transistor array 200 with a vertical gate is formed on the surface of a first substrate 100, including: forming a third supporting layer 110 on the surface of the first substrate 100; forming a transistor array 200 with a vertical gate on the third supporting layer 110, and each transistor 201 in the transistor array 200 passes through the third supporting layer 110.

[0050] In the embodiment of the present disclosure, Figure 3 As shown, a third supporting layer 110 can be formed on the surface of the first substrate 100 using a deposition process or other processes. The third supporting layer 110 may include a nitrogen-containing material, such as silicon nitride (SiN), silicon carbon nitride (SiCN), silicon boron nitride (SiBN), or a combination thereof. In some embodiments, the material of the third supporting layer 110 is SiBN. The third supporting layer 110 is used to support the capacitor structure 400 formed after removing the first substrate 100, thereby enhancing the structural stability of the memory 10.

[0051] like Figure 4As shown, a transistor array 200 with vertical gates can be further formed on the third supporting layer 110 using deposition, doping, photolithography, etching, and other processes, and each transistor 201 in the transistor array 200 penetrates the third supporting layer 110. It is worth noting that the "each transistor 201 penetrates the third supporting layer 110" here means that the drain region 211 of each transistor 201 penetrates the third supporting layer 110. In this way, after removing the first substrate 100 serving as the first sacrificial layer, the drain region 211 of each transistor 201 can be connected to the first electrode of the subsequently formed capacitor structure 400, thereby forming a memory cell.

[0052] In some embodiments, as Figure 4 As shown, forming a transistor array 200 with a vertical gate on the third supporting layer 110 includes: forming a plurality of mutually spaced semiconductor pillars 210 on the third supporting layer 110; doping the semiconductor pillars 210 to sequentially form a drain region 211, a channel region 212 and a source region 213 in a direction from the first substrate 100 toward the carrier substrate 300; forming a surrounding gate insulating layer 221 on the outer side of the channel region 212; forming a surrounding gate layer 222 on the outer side of the gate insulating layer 221; wherein the doped semiconductor pillars 210, the gate insulating layer 221 and the gate layer 222 constitute the transistor array 200; the gate layer 222 is electrically connected to a plurality of transistors 201 arranged in a first direction parallel to the surface of the first substrate 100.

[0053] In the embodiment of the present disclosure, a plurality of mutually spaced semiconductor pillars 210 can be formed on the third supporting layer 110 through deposition and other processes. The direction of the semiconductor pillars 210 is parallel to the Z direction. The material of the semiconductor pillars 210 includes but is not limited to silicon, germanium, etc. It can be understood that the semiconductor pillars 210 formed here penetrate the third supporting layer 110 and contact the first substrate 100, so that the drain region of the transistor 201 can be connected to the capacitor structure formed subsequently.

[0054] Next, the semiconductor column 210 can be doped using processes such as thermal diffusion and ion implantation to form a drain region 211, a channel region 212 and a source region 213, wherein the drain region 211 can be used to connect to a subsequently formed capacitor structure, and the source region 213 can be used to connect to a subsequently formed bit line.

[0055] Then, a surrounding gate insulating layer 221 can be formed on the outside of the channel region 212 by processes such as deposition or thermal oxidation. The materials of the gate insulating layer 221 include but are not limited to silicon oxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2), etc. Finally, a surrounding gate layer 222 can be formed on the outside of the gate insulating layer 221 by processes such as deposition. The gate layer 222 is a conductive material such as copper (Cu), tungsten (W), titanium nitride (TiN), doped semiconductor materials, etc. It is worth noting that the gate layer 222 formed here can extend along the Y direction and connect multiple transistors 201 in the extension direction. It is understandable that an isolation layer 202 can also be filled between multiple transistors 201. The isolation layer 202 can be an insulating material such as silicon oxide to reduce leakage problems between transistors 201.

[0056] In some embodiments, as Figure 5 As shown, the formation method further includes: forming a plurality of bit lines BL on a side of the transistor array 200 away from the first substrate 100; wherein the bit lines BL are electrically connected to a plurality of transistors 201 in the transistor array 200 arranged along a second direction parallel to the surface of the first substrate 100.

[0057] In the disclosed embodiments, a plurality of bit lines BL can be formed on a side of the transistor array 200 away from the first substrate 100 using a deposition process or other similar process. The bit lines BL are made of a conductive material, such as copper, tungsten, titanium nitride, or a doped semiconductor material. In some embodiments, the bit lines BL are made of titanium nitride. The bit lines BL can extend along the X-direction and connect the source regions 213 of the plurality of transistors 201 along the direction in which they extend.

[0058] In some embodiments, as Figure 6 As shown, the forming method further includes: providing a second substrate 301 ; and forming an insulating layer 302 on one side of the second substrate 301 to obtain a carrier substrate 300 .

[0059] In the embodiment of the present disclosure, the material of the second substrate 301 may include a single semiconductor material, such as silicon, germanium, etc., or a compound semiconductor material, such as gallium nitride, gallium arsenide, or indium phosphide, etc. An insulating layer 302 may be formed on one side of the second substrate 301 using a deposition process, thereby obtaining a carrier substrate 300. The material of the insulating layer 302 includes but is not limited to silicon oxide, silicon oxynitride, etc. It is understood that the carrier substrate 300 is used to support the transistor array 200 and the capacitor structure 400 after bonding, so the carrier substrate 300 may not have any devices. It is worth noting that Figure 6 The steps of forming the carrier substrate 300 are shown, and Figures 2 to 5 The steps of forming the transistor array 200 and the bit lines BL shown can be performed simultaneously without distinguishing the order, thereby saving process time and improving manufacturing efficiency.

[0060] In some embodiments, as Figure 8 As shown, after the carrier substrate 300 is bonded to the surface of the transistor array 200, the back side of the first substrate 100, that is, the side of the first substrate 100 away from the transistor array 200, can be thinned by etching, chemical mechanical polishing (CMP) and other processes to form a first sacrificial layer 100a, so as to facilitate the subsequent formation of a capacitor structure of a specific size and shape.

[0061] In some embodiments, as Figures 9 to 16 As shown, the first substrate 100 is removed and a capacitor structure 400 electrically connected to the transistor array 200 is formed, including: forming a plurality of first through holes 401 penetrating the first substrate 100; wherein each transistor 201 in the transistor array 200 is exposed from the bottom of the first through hole 401; forming a first electrode 410 connected to the transistor 201 in the first through hole 401; removing the remaining first sacrificial layer 100a; forming a dielectric layer 420 covering at least the surface of the first electrode 410; forming a second electrode 430 covering the outer surface of the dielectric layer 420; wherein the first electrode 410, the dielectric layer 420 and the second electrode 430 constitute the capacitor structure 400.

[0062] In the embodiment of the present disclosure, Figure 10 As shown, a plurality of first through holes 401 penetrating the first substrate 100 can be formed by processes such as photolithography and etching. The positions of the first through holes 401 correspond to the positions of the transistors 201 in the transistor array 200, so that the drain region 211 of each transistor 201 can be exposed from the bottom of the first through hole 401, facilitating the connection between the subsequently formed first electrode and the drain region 211 of the transistor 201.

[0063] like Figure 12 As shown, a conductive material can be filled into the first through hole 401 by a deposition process to form a first electrode 410 connected to the drain region 211 of the transistor 201. The conductive material includes, but is not limited to, copper, tungsten, titanium nitride, and doped semiconductor materials. In some embodiments, the material of the first electrode 410 is titanium nitride.

[0064] like Figure 15 As shown, the remaining first sacrificial layer 100a can be removed by photolithography, etching, etc. For example, a second through hole spaced apart from the first electrode 410 is first formed, the second through hole penetrates each sacrificial layer, and then the first sacrificial layer 100a is removed by etching through the second through hole.

[0065] like Figure 16As shown, a dielectric layer 420 covering at least the surface of the first electrode 410 and a second electrode 430 covering the surface of the dielectric layer 420 can be formed in sequence by using a deposition process. The dielectric layer 420 here can be a material with a high dielectric constant (High-K), such as aluminum oxide, zirconium oxide, etc., and the material of the second electrode 430 includes but is not limited to copper, tungsten, titanium nitride, doped semiconductor materials, etc. In some embodiments, the material of the second electrode 430 is titanium nitride. It will be understood that the above-mentioned first electrode 410, dielectric layer 420 and second electrode 430 constitute a capacitor structure 400. In this way, the coverage area of ​​the second electrode 430 can be increased, thereby increasing the capacitance and improving the performance of the memory.

[0066] In some embodiments, as Figure 9 and Figure 10 As shown, a plurality of first through holes 401 are formed through the first substrate 100, including: forming a stacked first supporting layer 402, a second sacrificial layer 403, and a second supporting layer 404 in sequence on a side of the first substrate 100 away from the transistor array 200; and forming a plurality of first through holes 401 through the second supporting layer 404, the second sacrificial layer 403, the first supporting layer 402, and the first sacrificial layer 100a.

[0067] In the embodiment of the present disclosure, Figure 9 As shown, a first supporting layer 402, a second sacrificial layer 403, and a second supporting layer 404 can be sequentially formed on a side of the first substrate 100 away from the transistor array 200 using deposition or other processes. The first supporting layer 402 and the second supporting layer 404 can comprise nitrogen-containing materials, such as silicon nitride, silicon carbon nitride, silicon boron nitride, or a combination thereof. In some embodiments, the material of the first supporting layer 402 and the second supporting layer 404 is SiCN. The first supporting layer 402 and the second supporting layer 404 are used to support the capacitor structure formed after the sacrificial layers are removed, and also provide a certain degree of insulation, thereby enhancing the structural stability and performance of the memory 10. Furthermore, the first supporting layer 402 and the second supporting layer 404 can also increase the coverage area of ​​the second electrode 430, thereby increasing the capacitance and further improving the performance of the memory. The material of the second sacrificial layer 403 can be boron phosphorus silicon glass (BPSG), so the surface morphology of the second sacrificial layer 403 is relatively flat, thereby providing a larger process window for subsequent processes including photolithography.

[0068] like Figure 10 As shown, multiple first through holes 401 can be formed by photolithography, etching and other processes, and the first through holes 401 penetrate the second supporting layer 404, the second sacrificial layer 403, the first supporting layer 402 and the first sacrificial layer 100a, so that the drain region 211 of the transistor 201 is exposed from the first through holes 401.

[0069] In some embodiments, a plurality of alternating support layers and sacrificial layers may be formed in sequence on a side of the first substrate 100 away from the transistor array 200, wherein the number of support layers is greater than or equal to 3 and the number of sacrificial layers is greater than or equal to 3, thereby further increasing the coverage area of ​​the second electrode to obtain a larger capacitance.

[0070] In some embodiments, as Figure 11 and Figure 12 As shown, a first electrode 410 connected to the transistor 201 is formed in the first through hole 401, including: filling the first through hole 401 with a conductive material until the conductive material covers the surface of the transistor array 200 layer away from the carrier substrate 300, forming a conductive column 405 filled in the first through hole 401 and a conductive layer 406 connecting each conductive column 405; removing the conductive layer 406, retaining the conductive column 405, to form a plurality of first electrodes 410.

[0071] In the embodiment of the present disclosure, Figure 11 As shown, a deposition process or the like can be used to fill the first through hole 401 with a conductive material until the conductive material covers the surface of the second support layer 404, thereby forming a conductive column 405 located in the first through hole 401, and a conductive layer 406 located on the surface of the second support layer 404 and connecting the conductive columns 405. The conductive material here can be titanium nitride.

[0072] like Figure 12 As shown, the conductive material above the surface of the second support layer 404, i.e., the conductive layer 406, can be removed by etching, chemical mechanical polishing, or other processes, while retaining the conductive pillars 405 located in the first through-holes 401, thereby forming a plurality of first electrodes 410. In this way, a relatively dense first electrode 410 can be formed, which is conducive to reducing defects.

[0073] In some embodiments, as Figures 13 to 15 As shown, after forming the first electrode 410 connected to the transistor 201 in the first through hole 401 , removing the remaining first sacrificial layer 100 a specifically includes removing the remaining first sacrificial layer 100 a and the second sacrificial layer 403 .

[0074] In some embodiments, as Figures 13 to 15 As shown, the remaining first sacrificial layer 100a and the second sacrificial layer 403 are removed, including: forming a plurality of second through holes 407 that penetrate the first supporting layer 402, the second sacrificial layer 403, the second supporting layer 404 and the first sacrificial layer 100a; wherein the second through holes 407 are spaced apart from the first through holes 401; etching is performed from the second through holes 407 toward one side of the first electrode 410 to remove the remaining first sacrificial layer 100a and the second sacrificial layer 403.

[0075] In the embodiment of the present disclosure, Figure 13 As shown, a plurality of second through holes 407 can be formed by processes such as photolithography and etching. The second through holes 407 penetrate the first sacrificial layer 100a, the first supporting layer 402, the second sacrificial layer 403, and the second supporting layer 404. It is worth noting that the second through holes 407 do not penetrate the third supporting layer 110 to avoid damage to the transistor array 200 when the first sacrificial layer 100a and the second sacrificial layer 403 are subsequently removed. In other words, the third supporting layer 110 can also protect the transistor array 200 during the process.

[0076] The second through hole 407 may be spaced apart from the first through hole 401 to effectively remove the first sacrificial layer 100a and the second sacrificial layer 403 between the plurality of first electrodes 410. For example, Figure 14 The figure shows a distribution diagram of the second through holes 407 in the XY direction. The opening of the second through hole 407 can be a cross shape. The second through holes 407 are distributed between multiple first through holes 401, and the second through holes 407 and the first through holes 401 are staggered in the X direction and the Y direction. This can further improve the effect of subsequent removal of the first sacrificial layer 100a and the second sacrificial layer 403.

[0077] like Figure 15 As shown, the remaining first sacrificial layer 100a and the second sacrificial layer 403 can be removed from the second through hole 407 by using etching or other processes to expose the first supporting layer 402, the second supporting layer 404 and the first electrode 410. In this way, the capacitor structure formed subsequently can be in the shape of a "stem", thereby increasing the capacitance.

[0078] In some embodiments, as Figure 16 As shown, a dielectric layer 420 is formed to cover at least the surface of the first electrode 410, including: depositing a dielectric material on the surface of the second supporting layer 404 and the inner wall surface of the second through hole 407 to form the dielectric layer 420; wherein the dielectric layer 420 covers at least a portion of the surface of the first electrode 410, the outer surfaces of the first supporting layer 402 and the second supporting layer 404, and the surface of the transistor array exposed from the bottom of the second through hole 407.

[0079] In the embodiment of the present disclosure, a high-k material can be deposited on the surface of the second supporting layer 404 and the inner wall of the second through hole 407 to form a dielectric layer 420 of the capacitor structure. It can be understood that after removing the first sacrificial layer 100a and the second sacrificial layer 403, the inner wall of the second through hole 407 includes a portion of the surface of the first electrode 410, the surface of the first supporting layer 402, and the surface of the portion of the transistor array (or the third supporting layer 110) exposed from the bottom of the second through hole 407. In this way, by depositing the high-k material on the surface of the second supporting layer 404 and the inner wall of the second through hole 407, the coverage area of ​​the formed dielectric layer 420 can be increased, thereby making the coverage area of ​​the subsequently formed second electrode 430 larger, which is conducive to improving the capacitance.

[0080] In some embodiments, as Figure 16 As shown, forming the second electrode 430 covering the outer surface of the dielectric layer 420 includes: depositing a conductive material on the outer surface of the dielectric layer 420 to form the second electrode 430 .

[0081] In the embodiment of the present disclosure, a conductive material, such as titanium nitride, may be further deposited on the outer surface of the dielectric layer 420 to form a second electrode 430 with a larger coverage area.

[0082] In some embodiments, as Figure 17 As shown, the forming method further includes: filling semiconductor material between the capacitor structures 400 until the capacitor structures 400 are covered to form an electrode filling layer 440 .

[0083] In the embodiment of the present disclosure, a semiconductor material, such as silicon germanium (SiGe), can be filled in the gaps between the capacitor structures 400 using a deposition process, until the semiconductor material covers the top surface of the capacitor structure 400, thereby forming an electrode filling layer 440. It is understood that the electrode filling layer 440 can improve the structural stability of the memory 10.

[0084] In some embodiments, as Figure 18 As shown, after the electrode filling layer 440 is formed, the excess semiconductor material on one side of the capacitor structure 400 in the X direction may be removed by etching or other processes.

[0085] Second, as Figure 18As shown, the embodiment of the present disclosure provides a memory 10 formed by the formation method of any of the above embodiments. It can be understood that, on the one hand, the transistor array with vertical gates has a higher degree of integration, which is conducive to reducing the occupied area of ​​the memory cell and improving the storage density of the memory; on the other hand, by bonding the transistor array to the carrier substrate and removing the first substrate as the first sacrificial layer, the process of forming the capacitor structure is further optimized; on the other hand, after removing the first substrate and each sacrificial layer, each supporting layer and the first electrode increases the coverage area of ​​the subsequently formed second electrode, thereby increasing the capacitance and thus improving the performance of the memory.

[0086] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory formed by the formation method of any one of the above embodiments.

[0087] It should be noted that the features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0088] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a memory, characterized in that: include: providing a first substrate; forming a transistor array having vertical gates on a surface of the first substrate; bonding a carrier substrate to the surface of the transistor array; The first substrate is removed and a capacitor structure electrically connected to the transistor array is formed; wherein the first substrate is used as a first sacrificial layer for forming the capacitor structure.

2. The method according to claim 1, characterized in that The removing of the first substrate and forming a capacitor structure electrically connected to the transistor array includes: forming a plurality of first through holes penetrating the first substrate, wherein each transistor in the transistor array is exposed from a bottom of the first through hole; forming a first electrode connected to the transistor in the first through hole; removing the remaining first sacrificial layer; forming a dielectric layer covering at least a surface of the first electrode; A second electrode is formed to cover the outer surface of the dielectric layer; wherein the first electrode, the dielectric layer and the second electrode constitute the capacitor structure.

3. The method according to claim 2, characterized in that The forming of a plurality of first through holes penetrating the first substrate includes: forming a stacked first supporting layer, a second sacrificial layer, and a second supporting layer in sequence on a side of the first substrate away from the transistor array; A plurality of first through holes are formed penetrating the second supporting layer, the second sacrificial layer, the first supporting layer, and the first sacrificial layer.

4. The method according to claim 3, characterized in that The forming of a first electrode connected to the transistor in the first through hole comprises: Filling the first through-hole with a conductive material until the conductive material covers the surface of the transistor array layer on a side away from the carrier substrate, thereby forming a conductive pillar filled in the first through-hole and a conductive layer connecting the conductive pillars; The conductive layer is removed, and the conductive pillars are retained to form a plurality of first electrodes.

5. The method according to claim 3, characterized in that After forming a first electrode connected to the transistor in the first through hole, removing the remaining first sacrificial layer specifically includes: The remaining first sacrificial layer and the second sacrificial layer are removed.

6. The method according to claim 5, characterized in that The removing of the remaining first sacrificial layer and the second sacrificial layer comprises: forming a plurality of second through holes penetrating the first supporting layer, the second sacrificial layer, the second supporting layer, and the first sacrificial layer; wherein the second through holes are spaced apart from the first through holes; Etching is performed from the second through hole toward one side of the first electrode to remove the remaining first sacrificial layer and the second sacrificial layer.

7. The method according to claim 6, characterized in that The forming of a dielectric layer covering at least the surface of the first electrode comprises: A dielectric material is deposited on the surface of the second supporting layer and the inner wall surface of the second through hole to form the dielectric layer; wherein the dielectric layer covers at least a portion of the surface of the first electrode, the outer surfaces of the first supporting layer and the second supporting layer, and the surface of the transistor array exposed from the bottom of the second through hole.

8. The method according to claim 6, characterized in that The forming of the second electrode covering the outer surface of the dielectric layer comprises: A conductive material is deposited on the outer surface of the dielectric layer to form the second electrode.

9. The method according to claim 1, characterized in that The forming of a transistor array having vertical gates on the surface of the first substrate comprises: forming a third supporting layer on the surface of the first substrate; The transistor array with vertical gates is formed on the third supporting layer, and each transistor in the transistor array penetrates the third supporting layer.

10. The method according to claim 9, characterized in that The forming of the transistor array having vertical gates on the third supporting layer comprises: forming a plurality of semiconductor pillars spaced apart from each other on the third supporting layer; Doping the semiconductor column to sequentially form a drain region, a channel region, and a source region in a direction from the first substrate toward the carrier substrate; forming a surrounding gate insulating layer outside the channel region; A surrounding gate layer is formed on the outside of the gate insulating layer; wherein the doped semiconductor column, the gate insulating layer and the gate layer constitute the transistor array; the gate layer is electrically connected to a plurality of transistors arranged in a first direction parallel to the surface of the first substrate.

11. The method according to claim 1, wherein The forming method further includes: forming a plurality of bit lines on a side of the transistor array away from the first substrate; wherein the bit lines are electrically connected to a plurality of transistors in the transistor array arranged along a second direction parallel to the surface of the first substrate.

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