A semiconductor device and a manufacturing method thereof

Abstract

This invention provides a semiconductor device and its manufacturing method, applicable to the field of semiconductor technology. In this invention, utilizing the film uniformity of atomic layer deposition (ALD) technology, a first connection pad layer of uniform thickness and a corresponding connection pad structure can be formed within a first interval between adjacent bit line structures. Furthermore, as the size of semiconductor structures shrinks, a first connection pad layer with internal voids and a corresponding connection pad structure of uniform thickness is formed within the first interval between adjacent bit line structures with gradually increasing aspect ratios, thereby improving the reliability and performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that comprises an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell includes a transistor electrically connected to a capacitor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuitry, through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell, can locate each memory cell to control its data access. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the reliability and performance of the semiconductor device.

[0004] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a semiconductor device, which may specifically include:

[0005] Base;

[0006] Multiple bit line structures are disposed on the substrate, spaced apart from each other;

[0007] A sidewall structure is located on the sidewall of the bit line structure;

[0008] Multiple contact structures are located between adjacent bit line structures, and cover a portion of the sidewall of the sidewall structure and define a first interval between adjacent bit line structures with the sidewall structure;

[0009] Multiple connecting pad structures are located on the contact structure, and the connecting pad structures include:

[0010] A first connecting pad layer, partially located in the first interval, is connected to the contact structure;

[0011] And a second connecting pad layer, located on the first connecting pad layer, wherein the bottom surface of the second connecting pad layer is higher than the top surface of the bit line structure.

[0012] In some optional examples, the semiconductor device may further include:

[0013] Multiple isolation structures are located between adjacent connecting pad structures and pass through the second connecting pad layer and the bit line structure to directly contact the first connecting pad layer.

[0014] In some optional examples, the bottom surface of the isolation structure may be completely covered by the bit line structure and the first connection pad layer.

[0015] In some alternative examples, the first connecting pad layer in the corresponding first interval may fill the first interval.

[0016] In some alternative examples, the first connecting pad layer located in the corresponding first interval may have voids.

[0017] In some alternative examples, the isolation structure is in direct contact with the gap and may extend to different depths of the gap.

[0018] In some alternative examples, the gap may be located on the vertical centerline of the first connecting pad layer.

[0019] In some optional examples, the semiconductor device may further include:

[0020] Multiple gate structures are disposed on the substrate, spaced apart from each other, with a second interval between adjacent gate structures;

[0021] The second connection pad layer includes a first portion located above the first interval and a second portion located within the second interval, wherein the bottom surface of the first portion is higher than the top surface of the bit line structure and the bottom surface of the second portion is lower than the top surface of the gate structure.

[0022] In some alternative examples, the second connecting pad is recessed on the lower surface of the first connecting pad towards the bottom of the isolation structure.

[0023] In some optional examples, the semiconductor device may further include:

[0024] A silicide layer is located between the contact structure and the first connection pad layer.

[0025] Secondly, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which may specifically include:

[0026] Provide a base, including a first zone and a second zone;

[0027] Multiple mutually separated position line structures and sidewall structures are formed, wherein the position line structures are located on the first region of the substrate, and the sidewall structures are located on the sidewalls of the position line structures;

[0028] Multiple contact structures are formed, the contact structures being located between adjacent bit line structures and covering a portion of the sidewall of the sidewall structure and defining a first interval between adjacent bit line structures with the sidewall structure;

[0029] Multiple connection pad structures are formed, the connection pad structures are located on the contact structure and include a first connection pad layer partially located in the first interval and a second connection pad layer located on the first connection pad layer, wherein the first connection pad layer is also connected to the contact structure, and the bottom surface of the second connection pad layer is higher than the top surface of the bit line structure.

[0030] In some optional examples, the method of manufacturing the semiconductor device may further include:

[0031] Multiple isolation structures are formed, which are located between adjacent connection pad structures and pass through the second connection pad layer and the bit line structure to directly contact the first connection pad layer.

[0032] In some alternative examples, the first connecting pad layer in the corresponding interval may fill the first interval.

[0033] In some optional examples, the method of manufacturing the semiconductor device may further include:

[0034] Multiple gate structures are formed on the second region and are spaced apart from each other, with a second interval between adjacent gate structures;

[0035] The second connection pad layer includes a first portion located above the first interval and a second portion located within the second interval, wherein the bottom surface of the first portion is higher than the top surface of the bit line structure and the bottom surface of the second portion is lower than the top surface of the gate structure.

[0036] In some optional examples, after forming the contact structure and before forming the connection pad structure, it may also include forming a silicide layer on the contact structure.

[0037] In this invention, by utilizing the film uniformity of atomic layer deposition, a first connection pad layer and a corresponding connection pad structure with uniform thickness can be formed in the first interval between adjacent bit line structures. Furthermore, as the size of the semiconductor structure shrinks, a first connection pad layer and a corresponding connection pad structure with internal voids and uniform thickness are formed in the first interval between adjacent bit line structures with gradually increasing aspect ratios, thereby improving the reliability and performance of the semiconductor device. Attached Figure Description

[0038] Figure 1 This is a top view of a substrate for forming a semiconductor device provided in one embodiment of the present invention.

[0039] Figures 2-6 This is a schematic diagram of the structure of the semiconductor device manufacturing method provided in one embodiment of the present invention during the preparation process.

[0040] The attached figures are labeled as follows:

[0041] 100 - Substrate, 100A - First Region, 100B - Second Region, 101 - Trench Isolation, 110 - Insulating Layer, SP1 - First Spacer, 120 - Bit Line Structure, 121 - Semiconductor Layer, 122 - Barrier Layer, 123 - Metal Layer, 124 - Cap Layer, 130 - Sidewall Structure, 131 - First Sidewall, 132 - Second Sidewall, 140 - Contact Structure, 150 - Silice Layer, 160 - Connector Pad Structure, 161 - First Connector Pad Layer, 162 - Second Connector Pad Layer, OP - Gap, INT - Vertical Centerline of First Connector Pad Layer, 170 - Isolation Structure, 220 - Gate Structure, SP2 - Second Spacer, R - Groove, 230 - First Dielectric Layer, 240 - Second Dielectric Layer. Detailed Implementation

[0042] The semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0043] For ease of understanding, the following text defines horizontal and vertical directions, where the horizontal direction is parallel to the surface of the substrate 100; and the vertical direction is perpendicular to the surface of the substrate 100. Figures 1-6 The X, Y, and Z directions are defined. The X direction corresponds to the horizontal direction, the Y direction corresponds to the vertical direction, and the horizontal and vertical directions are perpendicular to each other. The X and Y directions are perpendicular to each other, and the Z direction is perpendicular to the plane containing the X and Y directions.

[0044] Please refer to Figure 1The illustration shows a top view of a substrate for forming a semiconductor device according to an embodiment of the present invention. The substrate in this embodiment may include a first region 100A and a second region 100B. In one embodiment, the first region 100A is, for example, a cell region of the semiconductor device, and the second region 100B is, for example, a peripheral region of the semiconductor device, and the second region 100B surrounds, for example, the outside of the first region 100A, but is not limited thereto. Since the main inventive point of the semiconductor device and its manufacturing method provided in this embodiment is on the first region 100A of the substrate, it will be understood by those skilled in the art that most of the figures provided in this embodiment only illustrate the preparation process of the corresponding semiconductor structure and its manufacturing method on the first region 100A, while a small portion of the figures illustrate the preparation process of the corresponding semiconductor structure and its manufacturing method on the second region 100B.

[0045] Please refer to Figure 6 The illustration shown is a cross-sectional view of a semiconductor device provided in one embodiment of the present invention. Figure 6As shown, the semiconductor device includes a substrate 100, multiple bit line structures 120, sidewall structures 130, multiple contact structures 140, a silicide layer 150, multiple connection pad structures 160, and multiple isolation structures 170. The substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. Multiple trench isolations 101 are also provided within the substrate 100 to define multiple active areas (AA, not shown). Specifically, the trench isolation 101 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but are not limited thereto. Exemplarily, the trench isolation 101 in this embodiment may be elongated with its long axis extending along the Y direction. Furthermore, an insulating layer 110 is also disposed on the substrate 100. Specifically, the insulating layer 110 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or it may be a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but is not limited thereto.

[0046] In one embodiment, multiple bit line structures 120 are disposed on the first region 100A with spacing between them, and have multiple layers of bit line material, such as a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and a capping layer 124 stacked sequentially from bottom to top. The semiconductor layer 121 may be made of crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The barrier layer 122 may be made of metal, metal silicide, or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The conductive layer 123 may be made of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The capping layer 124 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. Exemplarily, the semiconductor layer 121 is made of polycrystalline silicon, the barrier layer 122 is made of cobalt silicide (CoSi), the conductive layer 123 is made of tungsten (W), and the capping layer 124 is made of silicon nitride (SiN). It should be understood that forming a multilayer bit line material layer on the first region 100A of the substrate 100 further includes forming the multilayer bit line material layer on the second region 100B of the substrate 100, and then forming a gate structure 220 on the second region 100B of the substrate 100. It should be understood that, in this embodiment of the invention, the interval between adjacent bit line structures 120 is exemplarily referred to as the first interval and identified by reference numeral SP1, while the interval between adjacent gate structures 220 is referred to as the second interval and identified by reference numeral SP2.

[0047] The sidewall structure 130 is located on the sidewalls of the bit line structure 120 and the gate structure 220, and may have a multilayer structure, for example... Figure 2The first sidewall 131 and the second sidewall 132 are sequentially arranged along the X direction, and the first sidewall 131 is in direct contact with the sidewall of the bit line structure 120 or the gate structure 220. Specifically, the first sidewall 131 and the second sidewall 132 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. For example, the material of the first sidewall 131 is silicon oxide (SiO2), and the material of the second sidewall 132 is silicon nitride (SiN). The contact structure 140 is located at a first spacing SP1 between adjacent bit line structures 120 (combined with... Figure 2The contact structure 140 is located within the active region (substrate 100), and its two sides are separated from each other by the sidewall structure 130 and the bit line structure 120 without direct contact. Its bottom directly contacts the end of the active region (substrate 100). The material of the contact structure 140 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. In one embodiment, the material of the contact structure 140 is phosphorus-doped silicon (SiP). The silicide layer 150 is located on the contact structure 140, and the connecting pad structure 160 conformally covers the top surface of the contact structure 140, the top surface of the sidewall structure 130, and the top surface of the bit line structure 120. Furthermore, the connection pad structure 160 in this embodiment includes a first connection pad layer 161 and a second connection pad layer 162 stacked sequentially from bottom to top, and the bottom surface of the second connection pad layer 162 is higher than the top surface of the bit line structure 120. Specifically, the first connection pad layer 161 in the connection pad structure 160 can wrap around the outer surface of the bit line structure 120 and the silicide layer 150, and its top surface is higher than the top surface of the bit line structure 120, while the second connection pad layer 162 in the connection pad structure 160 covers the first connection pad layer 161. In one embodiment, the material of the first connection pad layer 161 may include titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials, and is preferably titanium nitride (TiN), but is not limited thereto. The material of the second connecting pad 162 may include metals such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, and is preferably tungsten (W), but is not limited thereto. For example, since the second connecting pad 162 of the connecting pad structure 160 has different structures in the first region 100A and the second region 100B, for ease of distinction, in this embodiment of the invention, the second connecting pad 162 located above the corresponding first interval SP1 in the first region 100A can be defined as the first part of the second connecting pad 162, while the second connecting pad 162 located above the corresponding second interval SP2 in the second region 100B can be defined as the second part of the second connecting pad 162.

[0048] It should be specifically noted that, for the first region 100A, since the first connecting pad 161 and the second connecting pad 162 in this embodiment are formed using atomic layer deposition (ALD), and the uniformity of film formation characteristic of ALD and the high aspect ratio of the first spacing SP1 between adjacent bit line structures 120 result in the formation of a first connecting pad 161 with voids and uniform thickness within the first spacing SP1 between adjacent bit line structures 120. In one embodiment, as... Figure 6As shown and combined Figure 4 In some cases, gaps OP are provided within the first interval SP1 between adjacent bit line structures 120, while gaps OP are not provided within the first interval SP1 between adjacent bit line structures 120. Specifically, when there are no gaps OP in the first interval SP1 between adjacent bit line structures 120, the first connecting pad 161 filling it completely fills the first interval SP1. When there are gaps OP in the first interval SP1 between adjacent bit line structures 120, the gaps OP can be located on the vertical center line INT of the first connecting pad 161, and the gaps OP can be circular structures symmetrically arranged on both sides of the vertical center line INT of the first connecting pad 161 within the corresponding first interval SP1, such as elliptical structures, but not limited thereto. Furthermore, since the second connecting pad 162 in this embodiment of the invention is also deposited by atomic layer deposition, the top surface of the first portion of the second connecting pad 162 with or without gap OP in the first interval SP1 between adjacent bit line structures 120 has a seam that is recessed towards the surface of the substrate 100 at a position near the vertical center line INT, and the bottom surface of the first portion is higher than the top surface of the bit line structure 120, but this is not a limitation.

[0049] For the second region 100B, a first dielectric layer 230 and a second dielectric layer 240 are also provided on the substrate 100, and a connecting pad structure 160 is also provided. At this time, the connecting pad structure 160 includes a first connecting pad layer 161 and a second connecting pad layer 162 arranged in sequence. Specifically, the first dielectric layer 230 fills the second space SP2 between adjacent gate structures 220, and its top surface is flush with the top surface of the gate structure 220. The second dielectric layer 240 is located on the gate structure 220 and the first dielectric layer 230. The connection pad structure 160 is located within the second space SP2 between adjacent gate structures 220 and extends to cover the top surface of the second dielectric layer 240 above the gate structure 220. Since the width of the second space SP2 in the X direction is greater than the width of the first space SP1 in the X direction, the first connection pad layer 161 of the connection pad structure 160 located within the corresponding second space SP2 formed by atomic layer deposition has a groove R. Consequently, the second connection pad layer 162 of the connection pad structure 160 is not only located on the first connection pad layer 161 but also fills the groove R. Furthermore, the bottom surface of the second portion of the second connection pad layer 162 located above the second space SP2 between adjacent gate structures 220 in the second region 100B is also lower than the top surface of the gate structure 220.

[0050] The isolation structure 170 is disposed between adjacent connection pad structures 160. The isolation structure 170 located in the first region 100A passes through the second connection pad layer 162 of the corresponding connection pad structure 160 and the bit line structure 120, directly contacting the first connection pad layer 161 of the corresponding connection pad structure 160. That is, the bottom surface of the isolation structure 170 in the first region 100A is completely covered by the corresponding bit line structure 120 and the first connection pad layer 161. The isolation structure 170 located in the second region 100B passes through the corresponding connection pad structure 160 and the second dielectric layer 240, isolating itself from the gate structure 220 located below it. Furthermore, when a gap OP is provided in the first connection pad layer 161 within the corresponding first interval SP1 in the first region 100A, the isolation structure 170 is also in direct contact with the corresponding gap OP, and different isolation structures 170 can extend along the Y direction to different depths of the corresponding gap OP. In one embodiment, the material of the isolation structure 190 may include nitrides, such as silicon nitride, or oxides, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0051] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0052] In order to enable those skilled in the art to easily understand the manufacturing method of the semiconductor device in the embodiments of the present invention, the manufacturing method of the semiconductor device proposed in the present invention will be further described below with reference to the various structural schematic diagrams in the preparation process of the manufacturing method.

[0053] Please refer to Figures 2-6 As shown, the diagram illustrates the structural structure of the semiconductor device manufacturing method provided in the embodiment of the present invention during the preparation process.

[0054] like Figure 2 As shown, and in combination Figure 6First, a substrate 100 is provided, and multiple trenches are formed within the substrate 100 using an etching process. Then, an insulating material (such as silicon oxide, silicon nitride, etc.) is filled into the multiple trenches using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to form multiple trench isolations 101. The multiple trench isolations 101 define multiple active regions within the substrate 100. Next, an insulating layer 110 (such as a silicon oxide layer or a silicon nitride layer) and a multilayer bit line material layer located on the insulating layer 110 are formed on the substrate 100. Specifically, forming the multilayer bit line material layer may include forming a semiconductor layer 121, a barrier layer 122, a conductive layer 123, and a capping layer 124 sequentially from bottom to top on the substrate 100. For example, the material of the semiconductor layer 121 is polysilicon, the material of the barrier layer 122 is cobalt silicide (CoSi), the material of the conductive layer 123 is tungsten (W), and the material of the capping layer 124 is silicon nitride (SiN). Subsequently, an etching process is used to sequentially etch a multilayer structure of bit line material layers along the Y direction, thereby forming a plurality of mutually spaced bit line structures 120 and a gate structure 220 located on the second region 100B. Adjacent bit line structures 120 are separated by a first spacing SP1, and adjacent gate structures 220 are separated by a second spacing SP2. The width of the second spacing SP2 in the X direction is greater than the width of the first spacing SP1 in the X direction. Then, sidewall structures 130, self-aligned to the sidewalls of the bit line structures 120, are formed on both sides of each bit line structure 120. In one embodiment, the sidewall structure 130 has a multilayer structure, for example, a first sidewall 131 (e.g., silicon oxide) and a second sidewall 132 (e.g., silicon nitride) sequentially stacked along the X direction.

[0055] like Figure 3 As shown, and in combination Figure 6Next, using an etching process, the first region 100A is etched downwards along the Y direction to form a memory node contact trench (not shown) on the outside of the sidewall structure 130 after removing the insulating layer 110 and part of the substrate 100. Then, a contact material layer (not shown) is formed to completely cover the substrate 100 and fill the memory node contact trench. Then, an etching or planarization process is used to remove the contact material layer outside the memory node contact trench until the top surfaces of the bit line structure 120 and the sidewall structure 130 are exposed, thereby obtaining the contact structures 140 located in the memory node contact trench. The contact material layer can be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Next, a metal material layer (not shown) is deposited on the substrate 100, and the metal material layer and the substrate 100 are silicided so that the top of the contact structure 140, which is made of a silicon-containing semiconductor material, such as phosphorus-doped silicon, reacts with the metal material layer to form a silicide layer 150. Furthermore, a first dielectric layer 230, which fills the second spacing SP2 between adjacent gate structures 220 and whose top surface is flush with the top surface of the gate structure 220, and a second dielectric layer 240 located on the first dielectric layer 230 and the gate structure 220 are sequentially formed on the second region 100B using a deposition process.

[0056] like Figures 4-5 As shown, and in combination Figure 6Next, using a deposition process, a first connection pad material layer (such as titanium nitride) and a second connection pad material layer (such as tungsten metal) of the connection pad structure 160 are deposited on the first region 100A and the second region 100B of the substrate 100, and etched to form a first connection pad layer 161 wrapped around the surface of the silicide layer 150 and the bit line structure 120 on the first region 100A, and a second connection pad layer 162 filling the first spacer SP1 between adjacent bit line structures 120 and having a bottom surface higher than the top surface of the bit line structure 120. This forms a connection pad structure 160 including a first connection pad layer 181 and a second connection pad layer 162 arranged sequentially from bottom to top, and a connection pad structure 160 consisting of a first connection pad layer 161 with a groove R located in the second spacer SP2 between adjacent gate structures 220 and a second connection pad layer 162 filling the groove R and covering the first connection pad layer 161 on the second region 100B. Subsequently, a mask layer (not shown) is formed on the connection pad structure 160, wherein the mask layer has an isolation structure pattern. Using this mask layer as a mask, an isolation structure 170 disposed between adjacent connection pad structures 160 is formed on the first region 100A and the second region 100B using etching and filling processes. Specifically, the isolation structure 170 located on the first region 100A passes through the second connection pad layer 162 of the corresponding connection pad structure 160 and the bit line structure 120 and is in direct contact with the first connection pad layer 161 of the corresponding connection pad structure 160. That is, the bottom surface of the isolation structure 170 on the first region 100A is completely covered by the corresponding bit line structure 120 and the first connection pad layer 161. The isolation structure 170 located on the second region 100B passes through the corresponding connection pad structure 160 and the second dielectric layer 240 and is isolated from the gate structure 220 located below it, but this is not a limitation.

[0057] In summary, the present invention provides a semiconductor device comprising: a substrate; a plurality of bit line structures disposed on the substrate at intervals; a sidewall structure located on the sidewall of the bit line structure; a plurality of contact structures located between adjacent bit line structures and covering a portion of the sidewall of the sidewall structure and defining a first interval between adjacent bit line structures; and a plurality of connection pad structures located on the contact structures. Each connection pad structure comprises: a first connection pad layer located between the bit line structures, connected to the contact structure, and filling the first interval; and a second connection pad layer located on the first connection pad layer, wherein the bottom surface of the second connection pad layer is higher than the top surface of the bit line structure. In this invention, utilizing the film uniformity of atomic layer deposition (ALD) technology, a first connection pad layer and corresponding connection pad structures of uniform thickness can be formed within the first interval between adjacent bit line structures. Furthermore, as the size of the semiconductor structure shrinks, a first connection pad layer and corresponding connection pad structures with internal voids and uniform thickness are formed within the first interval between adjacent bit line structures with gradually increasing aspect ratios, thereby improving the reliability and performance of the semiconductor device.

[0058] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes multiple isolation trenches and an active region; Multiple bit line structures are disposed on the substrate, spaced apart from each other; A sidewall structure is located on the sidewall of the bit line structure; Multiple contact structures are located between adjacent bit line structures, directly contacting the end of the active region and covering a portion of the sidewall of the sidewall structure, and defining a first interval between adjacent bit line structures with the sidewall structure. Multiple connecting pad structures are located on the contact structure, and the connecting pad structures include: A first connecting pad layer, partially located in the first interval, is connected to the contact structure; And a second connecting pad layer, located on the first connecting pad layer, wherein the bottom surface of the second connecting pad layer is higher than the top surface of the bit line structure.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Multiple isolation structures are located between adjacent connecting pad structures and pass through the second connecting pad layer and the bit line structure to directly contact the first connecting pad layer.

3. The semiconductor device as described in claim 2, characterized in that, The bottom surface of the isolation structure is completely covered by the bit line structure and the first connecting pad layer.

4. The semiconductor device as described in claim 2, characterized in that, The first connecting pad in the corresponding first interval fills the first interval.

5. The semiconductor device as claimed in claim 2, characterized in that, The first connecting pad layer located in the corresponding first interval has a void.

6. The semiconductor device as claimed in claim 5, characterized in that, The isolation structure is in direct contact with the gap and extends to different depths of the gap.

7. The semiconductor device as claimed in claim 5, characterized in that, The gap is located on the vertical centerline of the first connecting pad layer.

8. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Multiple gate structures are disposed on the substrate, spaced apart from each other, with a second interval between adjacent gate structures; The second connection pad layer includes a first portion located above the first interval and a second portion located within the second interval, wherein the bottom surface of the first portion is higher than the top surface of the bit line structure and the bottom surface of the second portion is lower than the top surface of the gate structure.

9. The semiconductor device as claimed in claim 2, characterized in that, The second connecting pad is recessed on the lower surface of the first connecting pad towards the bottom of the isolation structure.

10. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A silicide layer is located between the contact structure and the first connection pad layer.

11. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, including a first region and a second region, wherein a plurality of isolation trenches and an active region are formed on the first region; Multiple mutually separated position line structures and sidewall structures are formed, wherein the position line structures are located on the first region of the substrate, and the sidewall structures are located on the sidewalls of the position line structures; Multiple contact structures are formed, the contact structures being located between adjacent bit line structures, directly contacting the end of the active region and covering a portion of the sidewall of the sidewall structure, and defining a first interval between adjacent bit line structures with the sidewall structure. Multiple connection pad structures are formed, the connection pad structures are located on the contact structure and include a first connection pad layer partially located in the first interval and a second connection pad layer located on the first connection pad layer, wherein the first connection pad layer is also connected to the contact structure, and the bottom surface of the second connection pad layer is higher than the top surface of the bit line structure.

12. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, Also includes: Multiple isolation structures are formed, which are located between adjacent connection pad structures and pass through the second connection pad layer and the bit line structure to directly contact the first connection pad layer.

13. The method for manufacturing a semiconductor device as described in claim 12, characterized in that, The first connecting pad layer in the corresponding interval fills the first interval.

14. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, Also includes: Multiple gate structures are formed on the second region and are spaced apart from each other, with a second interval between adjacent gate structures; The second connection pad layer includes a first portion located above the first interval and a second portion located within the second interval, wherein the bottom surface of the first portion is higher than the top surface of the bit line structure and the bottom surface of the second portion is lower than the top surface of the gate structure.

15. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, After forming the contact structure and before forming the connecting pad structure, the method further includes: A silicide layer is formed on the contact structure.

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