Thread tracking system, method, apparatus, electronic device, chip, storage medium

Abstract

The present disclosure relates to a thread tracking system, method, device, electronic equipment, chip and storage medium. The thread tracking system comprises a central controller, a plurality of comparison modules and a data bus. Each comparison module is arranged in a corresponding processor core. The comparison module is used to monitor state information of a thread running on each processor core. The data bus is used to connect each comparison module and the central controller, so as to send each state information to the central controller. The central controller is used to receive the state information output from each comparison module, and determine a running path of a target thread between a plurality of processor cores according to the state information in a plurality of clock cycles, so as to realize tracking of the target thread. The thread tracking system determines the running path of the target thread by a hardware mode, so as to realize accurate tracking of the target thread. Therefore, frequent interaction between software and hardware is not required, the load cost of the system is reduced, and the timeliness of the system is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a thread tracking system, method, device, electronic device, chip and storage medium. BACKGROUND

[0002] In order to achieve a good thread load response envelope, improve user performance experience and optimize energy efficiency, the time granularity of frequency adjustment decisions is gradually refined to 1ms or even lower on electronic devices such as mobile terminals (such as smartphones and tablets) and PCs (Personal Computers). Under this trend, how to better track target threads.

[0003] In related technologies, the thread running state is tracked by software and then given to hardware, but this solution causes frequent interaction between software and hardware, increases system load overhead and is not good in timeliness. SUMMARY

[0004] The present disclosure provides a thread tracking system, method and electronic device, which determines the running path of a target thread by a hardware manner, thereby achieving accurate tracking of the target thread. This eliminates the need for frequent interaction between software and hardware, reduces system load overhead and improves system timeliness. The technical solutions of the present disclosure are as follows:

[0005] The first aspect of the present disclosure provides a thread tracking system, comprising a central controller, a plurality of comparison modules and a data bus, wherein

[0006] Each comparison module is arranged in a corresponding processor core and is configured to monitor state information of a thread running on the processor core.

[0007] The data bus is configured to connect each comparison module and the central controller, so as to send the state information output by each comparison module to the central controller.

[0008] The central controller is configured to receive the state information output by each comparison module, and determine a running path of a target thread between a plurality of processor cores according to a plurality of state information, so as to track the target thread.

[0009] In an embodiment of the present disclosure, the comparison module comprises a core thread register, a target thread register, a data bus interface and a comparator, wherein

[0010] The core thread register is configured to store an actual identifier of a thread running on the current processor core.

[0011] The target thread register is configured to receive configuration information sent from the central controller through the data bus interface; wherein the configuration information contains a target identifier of a target thread to be tracked;

[0012] The comparator is configured to output the status information according to the actual identifier and the target identifier.

[0013] In one embodiment of the present disclosure, when the comparator outputs the status information according to the actual identifier and the target identifier, the comparator comprises:

[0014] In response to the actual identifier matching the target identifier, the status information output by the comparator identifies that the target thread is in a running state on the current processor core;

[0015] In response to the actual identifier not matching the target identifier, the status information output by the comparator identifies that the target thread is in a non-running state on the current processor core.

[0016] In one embodiment of the present disclosure, the central controller comprises a configuration unit CFG, a clock reset generation unit CRG, and a processing unit; wherein,

[0017] The configuration unit CFG contains a configuration register, which is configured to interact with an upper-layer software driver interface, receive a control instruction of the upper-layer software driver, and configure the clock reset generation unit CRG and the processing unit according to the control instruction;

[0018] The clock reset generation unit CRG is configured to provide a clock signal and a reset signal to the processing unit after being configured by the configuration unit CFG;

[0019] The processing unit is configured to generate configuration information according to the clock signal and the reset signal provided by the clock reset generation unit CRG after being configured by the configuration unit CFG, and send the configuration information to the corresponding comparator module through a data bus.

[0020] In one embodiment of the present disclosure, the central controller further comprises:

[0021] A plurality of groups of registers, which are configured to store the status information output from each comparator module.

[0022] In one embodiment of the present disclosure, the plurality of groups of registers comprise:

[0023] a current state register CSR, each bit of the current state register CSR being used to store current state information output by each of the comparison modules in a current clock cycle;

[0024] a previous state register PSR, each bit of the previous state register PSR being used to store previous state information output by each of the comparison modules in a previous clock cycle.

[0025] In an embodiment of the present disclosure, the plurality of groups of registers further comprises:

[0026] a current running core register CCR, each bit of the current running core register CCR being used to store a current core number of the processor core in which the target thread is executed in a current clock cycle;

[0027] a previous running core register PCR, each bit of the previous running core register PCR being used to store a previous core number of the processor core in which the target thread is executed in a previous clock cycle.

[0028] In an embodiment of the present disclosure, the processing unit is further configured to:

[0029] determine a processing result according to a running path of the target thread among the plurality of processor cores;

[0030] send the processing result to the configuration unit CFG or a system manager.

[0031] In an embodiment of the present disclosure, the state information comprises a timestamp and a core number, and the central controller is configured to determine the running path of the target thread among the plurality of processor cores according to the plurality of state information, including:

[0032] sort the received state information according to the timestamps in the state information to obtain a state information sequence of a plurality of continuous clock cycles;

[0033] track and record changes of the target thread among different processor cores according to the core number in each state information in the state information sequence;

[0034] generate and output the running path of the target thread according to the tracked sequence of changes of the target thread among the processor cores.

[0035] A second aspect embodiment of the present disclosure provides a thread tracking method, which is applied to the thread tracking system described above, and the method comprises:

[0036] receiving state information output by each of the comparison modules;

[0037] According to the state information, a running path of the target thread among the processor cores is determined to track the target thread.

[0038] In one embodiment of the present disclosure, the method further comprises:

[0039] According to the running path of the target thread among the processor cores, a processing result is determined.

[0040] The processing result is sent to a configuration unit CFG or a system manager.

[0041] In one embodiment of the present disclosure, the state information comprises a timestamp and a core number, and the determining of the running path of the target thread among the processor cores according to the state information comprises:

[0042] According to the timestamp in the state information, the received state information is sorted to obtain a state information sequence of consecutive clock cycles.

[0043] According to the core number in each state information in the state information sequence, a change of the target thread among different processor cores is tracked and recorded.

[0044] According to the tracked change sequence of the target thread among the processor cores, a running path of the target thread is generated and output.

[0045] A third aspect of the present disclosure provides a thread tracking device, which is applied to the thread tracking system and comprises:

[0046] A receiving module is configured to receive state information output from each comparison module.

[0047] A first determining module is configured to determine a running path of a target thread among a plurality of processor cores according to the state information, to track the target thread.

[0048] In one embodiment of the present disclosure, the device further comprises:

[0049] A second determining module is configured to determine a processing result according to the running path of the target thread among the processor cores.

[0050] A sending module is configured to send the processing result to a configuration unit CFG or a system manager.

[0051] In one embodiment of the present disclosure, the state information comprises a timestamp and a core number, and the first determining module comprises:

[0052] a sorting unit configured to sort the received state information according to the time stamp in the state information to obtain a state information sequence of a plurality of continuous clock cycles;

[0053] a tracking unit configured to track and record the change of the target thread between different processor cores according to the core number in each state information in the state information sequence;

[0054] a generating unit configured to generate and output the running path of the target thread according to the tracked change sequence of the target thread between the processor cores.

[0055] The fourth aspect of the present disclosure provides an electronic device, including a processor and a memory connected with the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method as described above.

[0056] The fifth aspect of the present disclosure provides a chip, including a processing circuit, the processing circuit is configured to execute the method as described above.

[0057] The sixth aspect of the present disclosure provides a computer readable storage medium, the computer readable storage medium stores computer execution instructions, the computer execution instructions are executed by the processor to implement the method as described above.

[0058] The embodiments of the present disclosure provide at least the following beneficial effects:

[0059] Through the embodiments of the present disclosure, the thread tracking system of the present disclosure includes a central controller, a plurality of comparison modules and a data bus; wherein each comparison module is arranged in a corresponding processor core and is used to monitor the state information of the running thread in each processor core; the data bus is used to connect each comparison module and the central controller to send the state information output by each comparison module to the central controller; the central controller is used to receive the state information output from each comparison module and determine the running path of the target thread between the plurality of processor cores according to the plurality of state information to realize the tracking of the target thread. Thus, the thread tracking system determines the running path of the target thread by hardware, thereby realizing the accurate tracking of the target thread, which reduces the frequent interaction between software and hardware, reduces the load cost of the system and improves the timeliness of the system.

[0060] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0061] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate implementations of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and, do not limit the present disclosure in any inappropriable way.

[0062] Figure 1 is an application scenario diagram of a thread tracking system according to an embodiment of the present disclosure;

[0063] Figure 2 is a whole block diagram of a thread tracking system according to an embodiment of the present disclosure;

[0064] Figure 3 is a schematic diagram of a central controller according to an embodiment of the present disclosure;

[0065] Figure 4 is a schematic diagram of a state maintenance register according to an embodiment of the present disclosure;

[0066] Figure 5 is a schematic diagram of thread switching in and out on the same core according to an embodiment of the present disclosure;

[0067] Figure 6 is a schematic diagram of thread migration core according to an embodiment of the present disclosure;

[0068] Figure 7 is a whole block diagram of hardware multithreading tracking according to an embodiment of the present disclosure;

[0069] Figure 8 is a schematic diagram of a central controller in hardware multithreading tracking according to an embodiment of the present disclosure;

[0070] Figure 9 is a flow chart of a thread tracking method according to an embodiment of the present disclosure;

[0071] Figure 10 is a block schematic diagram of a thread tracking device according to an embodiment of the present disclosure;

[0072] Figure 11 shows a block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure;

[0073] Figure 12 is a structural schematic diagram of a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings.

[0075] It should be noted that the terms "first", "second", and the like in the description and claims of the present disclosure and above drawings are used to distinguish between similar objects and not necessarily describe a particular sequential or chronological order. It should be understood that the use of such terms in some aspects can be interchanged with respect to one another, such that the embodiments described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following example embodiments are not meant to represent all implementations consistent with the present disclosure. Rather, they are simply examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0076] A thread tracking system and a thread tracking method of an embodiment of the present disclosure are described below with reference to the accompanying drawings.

[0077] Before introducing the thread tracking system of the present disclosure, the application scenario of the thread tracking system of the present disclosure is introduced.

[0078] Figure 1 is an application scenario diagram of the thread tracking system according to an embodiment of the present disclosure. As shown in Figure 1 , the thread tracking system of the present disclosure is applied to electronic devices such as mobile terminal devices or desktop PCs including but not limited to asymmetric multi-cores (such as large cores, medium cores, and small cores).

[0079] As shown in Figure 1 , threads can be scheduled among multiple cores and time-sliced on a single core, and the system manager needs to perform system-level resource management and supply according to the specific thread running path. The thread tracking system of the present disclosure serves the system manager, and the system manager tracks the running path of the thread, instructs the system manager to accurately statistically sample the path, and achieves a fine time granularity requirement of 1 ms and below.

[0080] Figure 2 is a whole block diagram of the thread tracking system according to an embodiment of the present disclosure. As shown in Figure 2 , the thread tracking system of the present disclosure includes a central controller (Hardware Thread Tracking Central Controller), a plurality of comparison modules (HTT Remote), and a data bus (Utility Bus).

[0081] It should be noted that each comparison module (HTT Remote) is arranged in the corresponding processor core (Core), and the number of comparison modules (HTT Remote) is determined by the number of processor cores. For example, the present disclosure is described with 4 processor cores (Core), the processor core Core0 is the processor core of the processor CPU0, the processor core Core1 is the processor core of the processor CPU1, the processor core Core2 is the processor core of the processor CPU2, and the processor core Core3 is the processor core of the processor CPU3.

[0082] The comparison module (HTT Remote) is used to monitor the state information of the thread running on each processor core (Core). The data bus (Utility Bus) is used to connect each comparison module (HTT Remote) and the central controller (Hardware Thread Tracking Central Controller) to send the state information output by each comparison module (HTT Remote) to the central controller (Hardware Thread Tracking Central Controller). The central controller (Hardware Thread Tracking Central Controller) is used to receive the state information sent from each comparison module (HTT Remote), and determine the running path of the target thread between multiple processor cores according to multiple state information, so as to realize the tracking of the target thread.

[0083] As shown in Figure 2 The comparison module (HTT Remote) of the present disclosure includes a core thread register TID Core, a target thread register TID Target, a data bus interface, and a comparator. The core thread register TID Core is used to store the actual identifier of the thread running on the current processor core. For example, the core thread register TID Core is responsible for sampling the system register inside the processor core, which is configured when the thread is cut in or out. The target thread register TID Target is used to receive the configuration information sent from the central controller (Hardware Thread Tracking Central Controller) through the data bus interface; wherein the configuration information contains the target identifier of the target thread to be tracked. The comparator is used to output the state information according to the actual identifier and the target identifier.

[0084] Wherein, the state information output by the comparator identifies that the target thread is in a running state on the current processor core, such as can be represented by 1, in the case that the actual identifier and the target identifier match; the state information output by the comparator identifies that the target thread is in a non-running state on the current processor core, such as can be represented by 0, in the case that the actual identifier and the target identifier do not match.

[0085] As shown in Figure 3 The central controller (Hardware Thread Tracking Central Controller) of the present disclosure comprises a configuration unit CFG, a clock reset generation unit CRG and a processing unit; wherein the configuration unit CFG contains a configuration register, which is used to interact with the upper-layer software driver interface, receive the control instruction of the upper-layer software driver, and configure the clock reset generation unit CRG and the processing unit according to the control instruction; the clock reset generation unit CRG is used to provide a clock signal and a reset signal to the processing unit after being configured by the configuration unit CFG; the processing unit is used to generate configuration information according to the clock signal and the reset signal provided by the clock reset generation unit CRG after being configured by the configuration unit CFG, and send the configuration information to the corresponding comparator module (HTT Remote) through a data bus.

[0086] The working principle of the central controller (Hardware Thread Tracking Central Controller) is as follows: after the processing unit is initialized by the configuration unit CFG and the target thread register TID Target is configured, the processing unit is enabled to work. The target thread register TID Target is configured to each comparison module (HTT Remote) by the processing unit through a data bus (Utility Bus), and after the processing unit initializes each comparison module (HTT Remote), each comparison module (HTT Remote) starts to work normally, and the results of each comparator are returned to the processing unit, which is uniformly processed by the processing unit, such as generating a running path between the target thread and multiple processor cores. After the running path determines the processing result, the processing result processed by the processing unit has two paths, one of which is to return the processing result to the configuration unit CFG, and then the processing result is read by the system software through a system bus; the other path is to send the processing result to the system manager through the module hardware interface, so as to realize the fast supply of on-chip information.

[0087] In one embodiment of the present disclosure, the central controller (Hardware Thread Tracking Central Controller) further comprises a plurality of sets of registers for storing the received state information output from each comparison module (HTT Remote).

[0088] As shown in Figure 4 , the plurality of sets of registers comprises a current status register (CSR) and a previous status register (PSR). Each bit of the current status register (CSR) is used to store the current state information output from each comparison module (HTT Remote) in the current clock cycle. Each bit of the previous status register (PSR) is used to store the previous state information output from each comparison module (HTT Remote) in the previous clock cycle.

[0089] With reference to Figure 4 , the plurality of sets of registers further comprises a current core register (CCR) and a previous core register (PCR). Each bit of the current core register (CCR) is used to store the current core number of the processor core in which the target thread is executed in the current clock cycle. Each bit of the previous core register (PCR) is used to store the previous core number of the processor core in which the target thread is executed in the previous clock cycle.

[0090] In an embodiment of the present disclosure, the state information comprises a timestamp and a core number, and the central controller (Hardware Thread Tracking Central Controller) is configured to determine the running path of the target thread between the plurality of processor cores based on the plurality of state information, comprising: sorting the received state information based on the timestamps in the state information to obtain a state information sequence of a plurality of consecutive clock cycles; tracking and recording the changes of the target thread between different processor cores based on the core number in each state information in the state information sequence; and generating and outputting the running path of the target thread based on the tracked change sequence of the target thread between the processor cores.

[0091] The present disclosure constructs the state event information of the generated thread through these state maintenance registers, tracks the running trajectory of the target thread, and provides a control basis for the system-on-chip manager.

[0092] The following is a description of the specific information output in the hardware thread tracking design:

[0093] Two states: Running and No-Running;

[0094] Two events: thread entry and thread exit;

[0095] Two pieces of information: whether or not the registration will be relocated, and where it will be relocated to.

[0096] Figure 5 This illustrates the situation where, on the same processor core, a thread actively or passively yields its time slice. A change from 0 to 1 or 1 to 0 occurs in the same bit of the previous status register PSR and the current status register CSR. From a hardware perspective, this is a cut-in / cut-out exception event. After these two exception events are triggered, the hardware must perform corresponding processing to ensure that runtime and performance counter statistics are accurate.

[0097] Figure 6 and Figure 5 The difference is that the thread moved from processor core 2 to processor core 1. The exception events triggered and the actions handled in between are the same. In addition, we know which processor core the thread moved from to which core.

[0098] The circuit design disclosed herein allows for the acquisition of two states, two events, and two pieces of information related to the target thread. Using this crucial information, the hardware system manager can perform corresponding management and control without relying on the software system or the thread's execution trajectory and state. This significantly reduces the load on the software system while greatly improving timeliness and accuracy.

[0099] It should be noted that, as Figure 7 and Figure 8 As shown, the thread tracing system disclosed herein is not limited to tracing the execution of a single thread. It can also achieve multi-threaded execution tracing by expanding the processor units in the central controller and increasing the number of comparison modules HTT Remote.

[0100] The thread tracking system of the present disclosure comprises a central controller, a plurality of comparison modules and a data bus. Each comparison module is arranged in a corresponding processor core and is used to monitor the state information of the threads running on the processor core. The data bus is used to connect the comparison modules and the central controller, so as to send the state information output by the comparison modules to the central controller. The central controller is used to receive the state information output by the comparison modules, and determine the running path of the target thread between the plurality of processor cores according to the plurality of state information, so as to track the target thread. Thus, the thread tracking system determines the running path of the target thread by a hardware manner, so as to accurately track the target thread, without frequent interaction between software and hardware, thereby reducing the load overhead of the system and improving the timeliness of the system.

[0101] In summary, by means of the embodiments of the present disclosure, the thread tracking system of the present disclosure comprises a central controller, a plurality of comparison modules and a data bus. Each comparison module is arranged in a corresponding processor core and is used to monitor the state information of the threads running on the processor core. The data bus is used to connect the comparison modules and the central controller, so as to send the state information output by the comparison modules to the central controller. The central controller is used to receive the state information output by the comparison modules, and determine the running path of the target thread between the plurality of processor cores according to the plurality of state information, so as to track the target thread. Thus, the thread tracking system determines the running path of the target thread by a hardware manner, so as to accurately track the target thread, without frequent interaction between software and hardware, thereby reducing the load overhead of the system and improving the timeliness of the system.

[0102] Figure 9 is a flowchart of a thread tracking method according to an embodiment of the present disclosure.

[0103] It should be noted that the thread tracking method of the present disclosure is applied to the thread tracking system described above, and the execution subject is the central controller (Hardware Thread Tracking Central Controller).

[0104] As shown in Figure 9 , the thread tracking method of the present disclosure comprises:

[0105] S1, receiving the state information output by each comparison module.

[0106] S2, determine a running path of the target thread among the plurality of processor cores according to the plurality of state information, so as to realize tracking of the target thread.

[0107] In one embodiment of the present disclosure, the method further comprises:

[0108] determine a processing result according to the running path of the target thread among the plurality of processor cores;

[0109] send the processing result to the configuration unit CFG or the system manager.

[0110] In one embodiment of the present disclosure, before receiving the state information output from each comparison module, the method further comprises:

[0111] In response to receiving a control instruction of an upper-layer software driver, configure the clock reset generation unit CRG and the processing unit according to the control instruction; wherein the clock reset generation unit CRG is configured to provide a clock signal and a reset signal to the processing unit after being configured by the configuration unit CFG; the processing unit is configured to generate configuration information according to the clock signal and the reset signal provided by the clock reset generation unit CRG after being configured by the configuration unit CFG, and send the configuration information to the corresponding comparator module through a data bus.

[0112] In one embodiment of the present disclosure, the state information comprises a timestamp and a core number, and the determination of the running path of the target thread among the plurality of processor cores according to the plurality of state information, so as to realize tracking of the target thread, comprises:

[0113] sort the received state information according to the timestamps in the state information, so as to obtain a state information sequence of a plurality of continuous clock cycles;

[0114] track and record changes of the target thread among different processor cores according to the core number in each state information in the state information sequence;

[0115] generate and output the running path of the target thread according to the tracked change sequence of the target thread among the processor cores.

[0116] It should be noted that details not disclosed in the thread tracking method of the present embodiment are described in detail in the thread tracking system of the present embodiment, and will not be described here.

[0117] The thread tracking method of the present embodiment first receives state information output from each comparison module, and determines a running path of the target thread among the plurality of processor cores according to the plurality of state information, so as to realize tracking of the target thread. The method realizes accurate tracking of the target thread, so that frequent interaction between software and hardware is not required, the load overhead of the system is reduced, and the timeliness of the system is improved.

[0118] Figure 10 is a block schematic diagram of a thread tracking apparatus according to an embodiment of the present disclosure. As shown in the figure, the thread tracking apparatus 100 of the present disclosure comprises: Figure 10

[0119] a receiving module 101 configured to receive state information output from each comparison module.

[0120] a first determining module 102 configured to determine a running path of a target thread among a plurality of processor cores according to the plurality of state information, so as to realize tracking of the target thread.

[0121] In an embodiment of the present disclosure, the apparatus further comprises:

[0122] a second determining module configured to determine a processing result according to the running path of the target thread among the plurality of processor cores.

[0123] a sending module configured to send the processing result to a configuration unit CFG or a system manager.

[0124] In an embodiment of the present disclosure, the state information comprises a timestamp and a core number, and the first determining module comprises:

[0125] a sorting unit configured to sort the received state information according to the timestamp in the state information, so as to obtain a state information sequence of a plurality of continuous clock cycles;

[0126] a tracking unit configured to track and record a change of the target thread among different processor cores according to the core number in each state information in the state information sequence;

[0127] a generating unit configured to generate and output the running path of the target thread according to the tracked change sequence of the target thread among the processor cores.

[0128] It should be noted that details not disclosed in the thread tracking apparatus of the present embodiment are described in the thread tracking system of the present embodiment, and will not be described here in detail.

[0129] The thread tracking apparatus of the present disclosure receives state information output from each comparison module through the receiving module, and determines a running path of a target thread among a plurality of processor cores according to the plurality of state information through the first determining module, so as to realize tracking of the target thread. Thus, the apparatus realizes accurate tracking of the target thread, so that frequent interaction between software and hardware is not required, the load overhead of the system is reduced, and the timeliness of the system is improved.

[0130] ​To achieve the above-mentioned embodiments, the present disclosure further provides an electronic device, comprising: a processor, and a memory connected with the processor in communication; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method provided by the foregoing embodiments.

[0131] Figure 11 A block diagram of an exemplary electronic device suitable for implementing an embodiment of the present disclosure is shown. Figure 11 The electronic device 12 shown is merely one example and should not be taken as limiting the scope of the embodiments of the present disclosure. The electronic device can be, for example, an electronic device or terminal.

[0132] As shown in Figure 11 The electronic device 12 is in the form of a general computing device. Components of the electronic device 12 can include, but are not limited to, one or more processors or processing units 16, a memory 28, a bus 18 that connects different system components, including the memory 28 and the processing unit 16.

[0133] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration bus, a processor or local bus using any of a variety of bus architectures. By way of example, these architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0134] The electronic device 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by the electronic device 12 and includes both volatile and non-volatile media, removable and non-removable media.

[0135] The memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache 32. The electronic device 12 can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 can be used for reading from and writing to non-removable, non-volatile magnetic media (e.g., a "hard drive").Figure 11 Not shown; usually referred to as a "hard drive".

[0136] although Figure 11 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disc drive for reading and writing to a removable non-volatile optical disc (e.g., a compact disc read-only memory (CD-ROM), a digital video disc read-only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this disclosure.

[0137] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of this disclosure.

[0138] Electronic device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable human interaction with electronic device 12, and / or with any device that enables electronic device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via input / output (I / O) interface 22. Furthermore, electronic device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with other modules of electronic device 12 via bus 18. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0139] The processing unit 16 performs various functional applications and data processing by running programs stored in the memory 28, such as implementing the methods mentioned in the foregoing embodiments.

[0140] To achieve the above-mentioned embodiments, the disclosure further provides a chip, comprising: the chip comprises a processing circuit, the processing circuit is configured to execute the method provided by the foregoing embodiments.

[0141] Figure 12 It is a structural schematic diagram of the chip provided by the embodiments of the disclosure. It can be seen from Figure 12 The structural schematic diagram of the chip 1100 is shown, but is not limited thereto.

[0142] The chip 1100 comprises a processing circuit 1101, and the processing circuit 1101 is configured to execute any of the above methods.

[0143] In some embodiments, the chip 1100 further comprises one or more interface circuits 1102. Optionally, the interface circuit 1102 is connected with the memory 1103, and the interface circuit 1102 can be used to receive signals from the memory 1103 or other devices, and the interface circuit 1102 can be used to send signals to the memory 1103 or other devices. For example, the interface circuit 1102 can read instructions stored in the memory 1103 and send the instructions to the processing circuit 1101.

[0144] In some embodiments, the interface circuit 1102 performs at least one of the communication steps such as sending and / or receiving in the above-mentioned methods, and the processing circuit 1101 performs other steps.

[0145] In some embodiments, the terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be replaced with each other.

[0146] In some embodiments, the chip 1100 further comprises one or more memories 1103 for storing instructions. Optionally, all or part of the memory 1103 can be outside the chip 1100.

[0147] To achieve the above-mentioned embodiments, the disclosure further provides a non-transitory computer-readable storage medium, which stores a computer program, and the program is executed by a processor to implement the method provided by the foregoing embodiments of the disclosure.

[0148] To achieve the above-mentioned embodiments, the disclosure further provides a computer program product, when the instructions in the computer program product are executed by a processor, the method provided by the foregoing embodiments of the disclosure is executed.

[0149] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the disclosure comply with the provisions of relevant laws and regulations, and do not violate public order and good customs.

[0150] It is important to note that user’s personal information should be collected for legitimate and reasonable uses of the entity and not shared or sold outside of those legitimate uses. Further, such collection / sharing should occur after receiving the consent of users to the sharing, including but not limited to, through notice and consent processes in the user agreement for users (including use of tick boxes or check boxes) and other consent processes, including through authorization and consent forms that include authorization for the sharing of relevant user information.

[0151] The present disclosure contemplates that user selectively opting in to the permission for use of or access to personal information data can be provided. That is, the present disclosure contemplates that hardware and / or software components can be provided to prevent or detect unauthorized access to such personal information data. Such collection and storage of information may

[0152] In the description of the specification, the description using the terms “one embodiment”, “some embodiments”, “an example”, “a specific example”, or “some examples” etc. means that the particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms in the specification do not necessarily refer to the same embodiment or example. Moreover, the particular features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Furthermore, the skilled person in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples, without contradiction, if necessary.

[0153] In addition, the terms “first”, “second” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second” can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of “a plurality of” is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0154] Any process or method descriptions or descriptions of the flow diagrams in the processes or methods described herein can be understood as representing modules, segments, or portions of code that include one or more executable instructions for implementing specific logical functions or steps in the processes. The scope of preferred embodiments of the present disclosure includes additional implementation in which the functions can be performed in different orders, including substantially simultaneously or in reverse order, and additional functions can be added, in accordance with the described functions. It will be appreciated by those skilled in the art that the scope of the present disclosure is not limited to the specific embodiments described herein, but extends to the embodiments described by the claims, including all equivalents of the embodiments.

[0155] The logic and / or steps represented in flow diagrams or otherwise described herein, for example, can be considered as a sequence of instructions to implement logic functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device, such as a computer-based system, processor- containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this specification, a "computer-readable medium" can be any means that can contain, store, communicate, propagate or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a machine-readable storage device (e.g., magnetic, optical or other storage device), a machine-readable storage substrate, a machine-readable signal, or any combination thereof. Other, specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electrical) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber (optical), and a portable compact disc read-only memory (CDROM). Note that the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example, via optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner into an electronic computer readable medium, then stored in the computer memory.

[0156] It should be understood that aspects of the present disclosure can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. As such, in some embodiments, memory (including computer-readable storage media) can store software or firmware for use by the instruction execution system. In other embodiments, hardware logic (including programmable logic for use with a programmable logic device) can be used to implement at least some of the steps or methods.

[0157] Those of skill in the art would understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0158] In addition, each functional unit in each embodiment of the present disclosure can be integrated in one processing module, or each unit can exist physically separately, or two or more units can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module. When the integrated module is realized in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium.

[0159] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A thread tracing system, characterized in that, include: Central controller, multiple comparison modules, and data bus; among which, Each of the comparison modules is set in the corresponding processor core and is used to monitor the status information of the threads running on each of the processor cores and output the status information of the target thread on each of the processor cores. The data bus is used to connect each of the comparison modules and the central controller, so as to send the status information output by each of the comparison modules to the central controller; The central controller is used to receive the status information output from each of the comparison modules, and to track and record the changes of the target thread between different processor cores according to the core number of the received status information, and to generate and output the running path of the target thread according to the changes, so as to achieve tracking of the target thread.

2. The thread tracing system according to claim 1, characterized in that, The comparison module includes: a core thread register, a target thread register, a data bus interface, and a comparator; wherein, The core thread register is used to store the actual identifier of the thread running on the current processor core; The target thread register is used to receive configuration information sent from the central controller through the data bus interface; wherein, the configuration information contains the target identifier of the target thread that needs to be tracked; The comparator is used to output the state information of the target thread on the current processor core based on the actual identifier and the target identifier.

3. The thread tracing system according to claim 2, characterized in that, When the comparator outputs the state information of the target thread on the current processor core based on the actual identifier and the target identifier, it includes: In response to a match between the actual identifier and the target identifier, the comparator outputs a status information indicating that the target thread is running on the current processor core; In response to a mismatch between the actual identifier and the target identifier, the comparator outputs a status information indicating that the target thread is in a non-running state on the current processor core.

4. The thread tracing system according to claim 1, characterized in that, The central controller includes: a configuration unit (CFG), a clock reset generation unit (CRG), and a processing unit; wherein, The configuration unit CFG includes a configuration register, which is used to interact with the upper-layer software driver interface, receive control instructions from the upper-layer software driver, and configure the clock reset generation unit CRG and the processing unit according to the control instructions. The clock reset generation unit CRG is used to provide clock signals and reset signals to the processing unit after being configured by the configuration unit CFG; The processing unit is configured, after being configured by the configuration unit CFG, to generate configuration information based on the clock signal and the reset signal provided by the clock reset generation unit CRG, and to send the configuration information to the corresponding comparison module via the data bus.

5. The thread tracing system according to claim 4, characterized in that, The central controller also includes: Multiple sets of registers are used to store the status information received from the output of each of the comparison modules.

6. The thread tracing system according to claim 5, characterized in that, The multiple sets of registers include: The current status register (CSR) has bits that store the current status information output by each comparison module in the current clock cycle. The previous status register (PSR) has its bits used to store the previous status information output by each comparison module in the previous clock cycle.

7. The thread tracing system according to claim 6, characterized in that, The multiple sets of registers also include: The current running core register (CCR) contains bits that store the current core number of the processor core in which the target thread is executed during the current clock cycle. The previous running core register (PCR) has its bits used to store the previous core number of the processor core in which the target thread was executed during the previous clock cycle.

8. The thread tracing system according to claim 4, characterized in that, The processing unit is also used for: The processing result is determined based on the running path of the target thread among the multiple processor cores; The processing result is sent to the configuration unit CFG or the system manager.

9. The thread tracing system according to claim 1, characterized in that, The received status information also includes a timestamp. The central controller is used to track and record the changes of the target thread across different processor cores based on the core numbers of the received status information, and to generate and output the execution path of the target thread based on the changes, including: Based on the timestamp, the received multiple state information items are sorted to obtain a state information sequence of multiple consecutive clock cycles; Based on the core number in each state information in the state information sequence, track and record the changes of the target thread across different processor cores; Based on the tracked sequence of changes of the target thread across the processor cores, the execution path of the target thread is generated and output.

10. A thread tracing method, characterized in that, The method is applied to the thread tracing system as described in any one of claims 1-9, comprising: Receive status information output from each comparison module; The target thread is tracked and recorded to track and record the changes of the target thread across different processor cores based on the core numbers of the received status information, and the running path of the target thread is generated and output based on the changes, so as to achieve tracking of the target thread.

11. The thread tracing method according to claim 10, characterized in that, The method further includes: The processing result is determined based on the running path of the target thread among the multiple processor cores; The processing result is sent to the configuration unit CFG or the system manager.

12. The thread tracing method according to claim 10, characterized in that, The received status information also includes a timestamp. The step of tracking and recording the changes of the target thread across different processor cores based on the core IDs of the received status information, and generating and outputting the execution path of the target thread based on these changes, includes: Based on the timestamp, the received multiple state information items are sorted to obtain a state information sequence of multiple consecutive clock cycles; Based on the core number in each state information in the state information sequence, track and record the changes of the target thread across different processor cores; Based on the tracked sequence of changes of the target thread across the processor cores, the execution path of the target thread is generated and output.

13. A thread tracing device, characterized in that, The device is applied to the thread tracing system as described in any one of claims 1-9, comprising: The receiving module is used to receive status information output from each of the comparison modules; The first determining module is used to track and record the changes of the target thread between different processor cores based on the core numbers of the multiple received status information, and generate and output the running path of the target thread based on the changes, so as to achieve tracking of the target thread.

14. The apparatus according to claim 13, characterized in that, The device further includes: The second determining module is used to determine the processing result based on the running path of the target thread among the multiple processor cores; The sending module is used to send the processing result to the configuration unit CFG or the system manager.

15. The apparatus according to claim 13, characterized in that, The received status information also includes a timestamp. The first determining module includes: The sorting unit is used to sort the received multiple state information according to the timestamp to obtain a state information sequence of multiple consecutive clock cycles. The tracking unit is used to track and record the changes of the target thread across different processor cores based on the core number in each state information in the state information sequence; The generation unit is used to generate and output the running path of the target thread based on the tracked sequence of changes of the target thread between the processor cores.

16. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 10-12.

17. A chip, characterized in that, The chip includes processing circuitry configured to perform the method as described in any one of claims 10-12.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 10-12.

Images