Substrate wiring method, substrate and packaging structure of 2.5D packaging structure

Abstract

The present application provides a substrate wiring method, substrate and packaging structure of a 2.5D packaging structure, which relates to the field of semiconductor technology. In the substrate wiring method of the 2.5D packaging structure, the volume of each dielectric layer provided with the wiring metal layer is calculated, the volume of the metal in each dielectric layer is calculated, and the volume proportion of the metal in each dielectric layer is calculated; and it satisfies. Such a setting is conducive to ensuring that the proportion of metal in each layer structure is roughly the same, the thermal expansion coefficient of each layer structure is similar, reducing warping and structural delamination caused by thermal stress, and improving structural reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a substrate wiring method, a substrate and a packaging structure of a 2.5D packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, chiplet technology has emerged, packaging small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input / output density of chips becomes higher and higher, and the number of chips integrated in a single package increases significantly, 2.5D packaging technology, as a multi-chip packaging solution, uses a multi-layer wiring layer process to improve the performance of the packaging structure. Because the 2.5D packaging structure uses a substrate structure with a wiring layer. The substrate adopts a multi-layer wiring layer design, the metal content of the wiring layer in each dielectric layer is inconsistent, and the thermal stress is different, which makes it easy for stratification between each dielectric layer. Summary of the invention

[0003] The purpose of the present invention includes providing a substrate wiring method, substrate and packaging structure of a 2.5D packaging structure, which can ensure that the metal content in each dielectric layer is roughly consistent, so that the thermal expansion coefficient of each layer of the hierarchical structure is similar, thereby reducing warping deformation and structural stratification caused by thermal stress.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a substrate wiring method for a 2.5D packaging structure, wherein the substrate comprises a plurality of stacked dielectric layers, each dielectric layer being provided with a wiring metal layer; the substrate wiring method comprises:

[0006] Calculate the volume of each dielectric layer with the wiring metal layer , i is a natural number between 1 and N; N is the number of dielectric layers provided with the wiring metal layer;

[0007] Calculate the volume of metal in each dielectric layer , i is a natural number between 1 and N; N is the number of dielectric layers provided with the wiring metal layer;

[0008] Calculate the metal volume percentage in each dielectric layer ; ;

[0009] .

[0010] In an optional embodiment, when N is greater than or equal to 5, .

[0011] In an optional embodiment, the wiring metal layer includes a first end portion, a connection portion, and a second end portion connected in sequence; ;in, represents the volume of the first end; Indicates the volume of the connecting line; represents the volume of the second end; m represents the number of wirings in each wiring metal layer.

[0012] In an optional embodiment, the first end includes a connected column section and a transition section; the transition section is connected to the connecting portion; and the volume of the first end is the sum of the volume of the column section and the volume of the transition section.

[0013] In an alternative embodiment, ; is the area of ​​the first top surface of the column segment, is the area of ​​the first bottom surface of the column segment; the first top surface and the first bottom surface are arranged opposite to each other; is the height of the column segment in a direction perpendicular to the first top surface and the first bottom surface; ; is the area of ​​the second top surface of the transition section, is the area of ​​the second bottom surface of the transition section; the second top surface and the second bottom surface are arranged opposite to each other; is the height of the transition section in a direction perpendicular to the second top surface and the second bottom surface; wherein, is the volume of the overlapping portion of the column segment at the first end and the column segment at the first end;

[0014] ;

[0015] ; is the length of the connecting line; is the cross-sectional area of ​​the connecting line;

[0016] ; is the area of ​​the third top surface of the cylinder at the second end, is the area of ​​the third bottom surface of the column at the second end; the third top surface and the third bottom surface are arranged oppositely; is the height of the second end in a direction perpendicular to the third top surface and the third bottom surface; is the volume of the overlapping portion of the column at the second end and the column where the connecting line portion is located.

[0017] In an optional embodiment, if the first top surface of the column segment is circular, then ; b is the radius of the circle where the first top surface is located;

[0018] ; is the central angle corresponding to the overlapping part of the column where the column segment and the transition segment are located; is the height of the overlapping portion of the column where the transition section is located and the column section in a direction perpendicular to the first top surface;

[0019] If the third top surface of the second end is circular, then ; is the radius of the circle where the third top surface is located;

[0020] ; is the central angle corresponding to the overlapping portion of the cylinder at the second end and the cylinder where the connecting line portion is located; It is the height of the overlapping portion of the column at the second end and the column where the connecting portion is located in the direction perpendicular to the third top surface.

[0021] In an alternative embodiment, ; is the bottom area of ​​each dielectric layer; is the thickness of each dielectric layer.

[0022] In an optional embodiment, if , then use at least one of the following methods:

[0023] 1. In and A dummy wiring layer is added to the smaller layer of the two layers, the dummy wiring layer is made of metal material, and the dummy wiring layer is not electrically connected to the wiring metal layer;

[0024] 2. and In the larger layer of the two, reducing the cross section of at least one of the connection portion, the first end portion, and the second end portion; or reducing the number of wirings in each wiring metal layer;

[0025] 3. and In the smaller layer of the two, the cross section of at least one of the connection portion, the first end portion and the second end portion is increased; or the number of wirings in each wiring metal layer is increased;

[0026] 4. and The thickness of the dielectric layer is increased in the larger of the two.

[0027] In an optional embodiment, if , then in and The dummy wiring layer is added to the smaller layer of the two.

[0028] In an optional embodiment, in The pseudo wiring layer is increased and the first The number of wiring in the layer; in the ( ) layer and / or the ( Layer increase Reduced amount of routing in the layer.

[0029] In an optional implementation, a dummy wiring mark portion is arranged on the cutting path of the substrate, and the dummy wiring mark portion is located on the outermost dielectric layer.

[0030] In an optional implementation, a stress release portion is provided on the pseudo wiring mark portion on the cutting path.

[0031] In an optional embodiment, there are multiple stress release portions, and the multiple stress release portions are centrally symmetrically distributed; each of the stress release portions includes a first side and a second side that are oppositely arranged, and the first side and the second side are symmetrically arranged.

[0032] In an optional embodiment, the method comprises:

[0033] forming an initial metal layer;

[0034] Forming a first dielectric layer covering the initial metal layer; wherein the first dielectric layer has a second graphic layer opening exposing the initial metal layer;

[0035] Filling metal in the opening of the second graphic layer to form a first wiring metal layer;

[0036] Forming a second dielectric layer covering the first wiring metal layer; wherein the second dielectric layer is provided with a third graphic layer opening;

[0037] forming a second wiring metal layer in the opening of the third graphic layer;

[0038] And so on, until the N+1th dielectric layer covering the Nth wiring metal layer is formed;

[0039] Wherein, a window is provided on the N+1th dielectric layer;

[0040] Filling metal in the window to form a bump;

[0041] Among them, a stress balancing groove is opened on at least any one dielectric layer; metal is filled in the stress balancing groove; after the dielectric layer is baked and solidified, the metal in the stress balancing groove is removed.

[0042] The stress balancing groove is arranged in a non-mounting area of ​​the substrate, wherein the non-mounting area includes a cutting path and an edge area.

[0043] In a second aspect, the present invention provides a substrate prepared by a substrate wiring method for a 2.5D packaging structure as described in any one of the aforementioned embodiments.

[0044] In a third aspect, the present invention provides a packaging structure, comprising components and a substrate as described in any one of the aforementioned embodiments, wherein the components are mounted on the substrate and electrically connected to the substrate.

[0045] The substrate wiring method, substrate and packaging structure of the 2.5D packaging structure provided by the embodiments of the present invention have the following beneficial effects:

[0046] The substrate wiring method, substrate and packaging structure of the 2.5D packaging structure provided by the present application adopt a hierarchical structure in which multiple dielectric layers are stacked. A wiring metal layer is provided in each dielectric layer. By controlling the metal volume proportion in each dielectric layer, the metal volume proportion in the adjacent two layers does not exceed 8%. In this way, it can be ensured that the metal content in each dielectric layer is roughly the same, so that the thermal expansion coefficient of each layer of the hierarchical structure is similar, reducing the warping deformation and structural delamination caused by thermal stress, and improving the structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A schematic diagram of a 2.5D packaging structure provided in this embodiment;

[0049] Figure 2 A schematic diagram of the distribution of the wiring structure in the dielectric layer in the substrate of the 2.5D packaging structure provided in this embodiment;

[0050] Figure 3 A schematic diagram of the distribution of multiple wiring structures in a certain dielectric layer in the substrate of the 2.5D packaging structure provided in this embodiment;

[0051] Figure 4 A schematic diagram of a wiring structure in a substrate of a 2.5D packaging structure provided in this embodiment;

[0052] Figure 5 A schematic diagram of parameter annotation of a wiring structure in a substrate provided in this embodiment;

[0053] Figure 6 A schematic structural diagram of a substrate of a 2.5D packaging structure provided in this embodiment;

[0054] Figure 7 for Figure 6 A partial enlarged schematic diagram of point F in the middle;

[0055] Figure 8 A schematic diagram of a structure in which multiple wiring structures in the same dielectric layer of a substrate of a 2.5D packaging structure provided in this embodiment use different line widths;

[0056] Fig. 9 A schematic diagram of the distribution of a wiring structure and a dummy wiring layer in a certain dielectric layer in a substrate of a 2.5D packaging structure provided in this embodiment from a cross-sectional perspective;

[0057] Fig.10 A schematic diagram of the distribution of the wiring structure in the substrate and the dummy wiring layer in the dielectric layer of the 2.5D packaging structure provided in this embodiment;

[0058] Fig.11 Another structural schematic diagram of a substrate of a 2.5D packaging structure provided in this embodiment;

[0059] Fig.12 A schematic diagram of a first structure of forming a pseudo wiring identification portion on a cutting path in a substrate of a 2.5D packaging structure provided in this embodiment;

[0060] Fig.13 A schematic diagram of a second structure of forming a pseudo wiring identification portion on a cutting path in a substrate of a 2.5D packaging structure provided in this embodiment;

[0061] Fig.14 A schematic diagram of a third structure of forming a pseudo wiring identification portion on a cutting path in a substrate of a 2.5D packaging structure provided in this embodiment;

[0062] Fig.15 A schematic diagram of a distribution structure of pseudo wiring identification parts on a cutting path in a substrate of a 2.5D packaging structure provided in this embodiment;

[0063] Figures 16 to 19 A schematic diagram of the manufacturing process of a substrate of a 2.5D packaging structure provided in this embodiment;

[0064] Fig. 20 A schematic structural diagram of the 2.5D packaging structure provided in this embodiment from another perspective.

[0065] Icons: 10-packaging structure; 100-substrate; 200-chip; 300-plastic package; 400-base plate; 110-dielectric layer; 120-wiring metal layer; 1201-wiring structure; 121-first end; 122-column section; 123-transition section; 124-connection section; 125-second end; 140-pseudo wiring layer; 141-pseudo wiring layer pattern opening; 143-pseudo wiring identification section; 150-stress release section; 160-bump; 171-carrier; 172-film layer; 173-photoresist layer; 17 4-first graphic layer opening; 175-initial metal layer; 111-first dielectric layer; 1111-second graphic layer opening; 131-first wiring metal layer; 112-second dielectric layer; 1121-third graphic layer opening; 132-second wiring metal layer; 113-third dielectric layer; 133-third wiring metal layer; 114-Nth dielectric layer; 134-Nth wiring metal layer; 115-bottom dielectric layer; 116-solder ball; 117-top dielectric layer; 180-cutting path; 181-edge area. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0069] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0070] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0071] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0072] Combination Figure 1 The 2.5D packaging structure 10 provided in an embodiment of the present invention includes components and a substrate 100. The components are mounted on the substrate 100 and electrically connected to the substrate 100. The components include, but are not limited to, chips 200, capacitors, inductors, resistors and other elements. Optionally, the packaging structure 10 includes a substrate 400, a substrate 100, a chip 200 and a plastic package 300. The chip 200 is mounted on the substrate 100 and electrically connected to the substrate 100. The plastic package 300 covers the chip 200 to protect it. In some embodiments, the plastic package 300 can also be omitted. Among them, the substrate 100 includes a plurality of stacked dielectric layers 110, and each dielectric layer 110 is provided with a wiring metal layer 120. The substrate 100 is arranged on the substrate 400, and the substrate 100 and the substrate 400 are electrically connected.

[0073] In the substrate wiring method of the 2.5D package structure 10 provided in the embodiment of the present invention, the volume of each dielectric layer 110 provided with the wiring metal layer 120 is calculated. , calculate the volume of metal in each dielectric layer 110 , calculate the metal volume proportion in each dielectric layer 110 ; ; and meet This arrangement helps ensure that the metal proportions in each layer structure are roughly the same, the thermal expansion coefficients of each layer structure are similar, and the warping and structural delamination caused by thermal stress are reduced, thereby improving structural reliability.

[0074] Understandably, . That is The dielectric layer 110 structure and the The difference in the volume percentage of metal in the dielectric layer 110 structure does not exceed 8%, that is, the volume percentage of metal in the two adjacent dielectric layer 110 structures in the substrate 100 does not exceed 8%. This is conducive to making the thermal expansion coefficients of the two adjacent layers in the substrate 100 closer, so that the thermal stresses they are subjected to are roughly the same. This can alleviate the warping deformation and structural delamination caused by the difference in thermal stress in the process.

[0075] It should be noted that the dielectric layer 110 for controlling the metal volume ratio in this embodiment refers to the dielectric layer 110 provided with the wiring metal layer 120. The dielectric layer for forming bumps on the upper and lower surface layers is not within the control design range of the above accuracy.

[0076] Optional, when N is greater than or equal to 5, That is, in the entire substrate 100 structure, the difference in metal volume percentage between the first dielectric layer 111 and the Nth dielectric layer 114 is no more than 8%. Assuming that the dielectric layer 110 with the wiring metal layer 120 has 6 layers in total, the difference in metal proportion between the first layer and the sixth layer structure does not exceed 40%. Assuming that the dielectric layer 110 with the wiring metal layer 120 has 10 layers in total, the difference in metal proportion between the first layer and the tenth layer structure does not exceed 72%. This is conducive to achieving similar thermal expansion coefficients of materials in all layers of the hierarchical structure, and is conducive to controlling the warping deformation of the entire substrate 100 structure in the process technology and reducing the risk of structural delamination.

[0077] It can be understood that as the N value increases, that is, the number of dielectric layers 110 increases, the cumulative error becomes larger. By reducing the metal volume percentage difference of one layer and spreading it to the multi-layer structure, the metal percentage error between the first layer and the Nth layer is controlled within In this way, the difference in thermal expansion coefficient of each layer structure is smaller and the control accuracy is higher, which can effectively alleviate the warping deformation and reduce the risk of structural delamination.

[0078] Combination Figures 2 to 4 Optionally, the wiring metal layer 120 includes a first end portion 121, a connection portion 124, and a second end portion 125 connected in sequence; ;in, represents the volume of the first end portion 121; represents the volume of the connecting portion 124; represents the volume of the second end 125; m represents the number of wirings in each wiring metal layer 120. In other words, the wiring metal layer 120 in each dielectric layer 110 includes a plurality of wiring structures 1201, each wiring structure 1201 includes a first end 121, a wiring portion 124, and a second end 125. The volume of each wiring structure 1201 is the sum of the volumes of the first end 121, the wiring portion 124, and the second end 125, expressed as The volume of the entire wiring metal layer 120 in the dielectric layer 110 is the sum of the volumes of all wiring structures 1201 .

[0079] It should be noted that the shape and size of each wiring structure 1201 may be the same or different, and can be flexibly designed according to actual needs. For example, the first end 121 can be any shape such as a truncated cone, a cylinder, a prism or a prism, a cone or a pyramid. The second end 125 can also be any shape such as a truncated cone, a cylinder, a prism or a prism, a cone or a pyramid. The connecting portion 124 can be any shape such as a cylinder, an elliptical cylinder, a cuboid or a semi-cylinder. Each part can be a regular shape or an irregular shape.

[0080] It should be understood that in some wiring structures 1201, the number of connection parts 124 may be more than one, for example, a first end 121 or a second end 125 may extend from multiple connection parts 124. Or a connection part 124 may extend from one or more end structures. Regardless of how the shape of the wiring structure 1201 changes, the calculation principle is the same as above, and it is only necessary to calculate and sum the volumes of each segment of each wiring structure 1201 in turn, and finally add up the volumes of multiple wiring structures 1201 in each layer to obtain the metal volume in the layer structure.

[0081] Combination Figure 3 , Figure 3 It is a distribution diagram of the wiring metal layer 120 in a certain dielectric layer 110. It can be seen that some wiring structures 1201 do not have end structures. For example, it can be used to connect two or more wiring structures 1201 in the same layer. Or some wiring structures 1201 have only one end, which is not specifically limited here. Exemplarily, in each wiring structure 1201, the first end 121 includes a connected column segment 122 and a transition segment 123; the transition segment 123 is connected to the connecting portion 124. The volume of the first end 121 is the sum of the volume of the column segment 122 and the volume of the transition segment 123.

[0082] Combination Figures 5 to 7 , the volume of the wiring structure 1201 is calculated as follows:

[0083] Volume of column segment 122: ; is the area of ​​the first top surface of the column segment 122, is the area of ​​the first bottom surface of the column segment 122; the first top surface and the first bottom surface are arranged opposite to each other; is the height of the column segment 122 in a direction perpendicular to the first top surface and the first bottom surface.

[0084] The volume of the transition section 123: ; is the area of ​​the second top surface of the transition section 123, is the area of ​​the second bottom surface of the transition section 123; the second top surface and the second bottom surface are arranged oppositely; is the height of the transition section 123 in a direction perpendicular to the second top surface and the second bottom surface; wherein, It is the volume of the overlapping portion of the column where the column segment 122 of the first end 121 and the transition segment 123 of the first end 121 are located.

[0085] The volume of the first end 121: .

[0086] The volume of the second end 125: ; is the length of the connecting portion 124; is the cross-sectional area of ​​the connecting portion 124;

[0087] Volume of the third end: . is the area of ​​the third top surface of the cylinder at the second end 125, is the area of ​​the third bottom surface of the cylinder of the second end 125; the third top surface and the third bottom surface are arranged oppositely; is the height of the second end portion 125 in a direction perpendicular to the third top surface and the third bottom surface; is the volume of the overlapping portion of the column at the second end 125 and the column where the connecting portion 124 is located.

[0088] Volume of each wiring structure 1201: .

[0089] Optionally, the column section 122 is a truncated cone structure, the transition section 123 is approximately a truncated cone structure; the connecting portion 124 is a cylinder, and the second end portion 125 is a truncated cone structure. If the first top surface of the column section 122 is circular, then ; b is the radius of the circle where the first top surface is located; Figure 5 Where a is the circular radius of the first bottom surface, .

[0090] ; is the central angle corresponding to the overlapping portion of the cylinder where the cylinder section 122 and the transition section 123 are located; is the height of the overlapping portion of the column where the transition section 123 is located and the column section 122 in a direction perpendicular to the first top surface;

[0091] If the third top surface of the second end portion 125 is circular, then ; is the radius of the circle where the third top surface is located; Figure 5 Where c is the circular radius of the third base, .

[0092] ; is the central angle corresponding to the overlapping portion of the cylinder of the second end portion 125 and the cylinder where the connecting portion 124 is located; It is the height of the overlapping portion of the column at the second end 125 and the column where the connecting portion 124 is located in the direction perpendicular to the third top surface.

[0093] Combination Figure 5 As shown, it can be understood that in the above calculation method, the volume of the column section 122 of the first end 121 and the volume of the column where the transition section 123 of the first end 121 is located have a partial overlapping area K. represents the volume of the overlapping area. And, ; is the central angle of the circle corresponding to the overlapping area of ​​the prism and the frustum; is the height of the overlapping area between the prism and the frustum. The calculation idea is: the radius is , the central angle is The cross-sectional area of ​​the overlapping area is the area of ​​the fan-shaped area minus the area of ​​the triangle OCB, that is, Figure 5 The product of the cross-sectional area of ​​the overlapping area and the corresponding height is the volume of the area. It should be understood that according to different actual shapes, It may be a variable or a fixed value. If it is a variable, the calculus method can be used to calculate the volume of the overlapping area, and the calculation formula is not shown here.

[0094] Therefore, the volume of the first end 121 is: Substituting the above calculation formulas into this formula, we get:

[0095]

[0096] ; is the length of the connecting portion 124. In this embodiment, the connecting portion 124 is taken as an example of a uniform cross section. The area of ​​the second top surface of the truncated cone in the transition section 123 is Consistent. Among them, .

[0097] ; is the central angle corresponding to the overlapping area of ​​the truncated cone of the connecting portion 124 and the second end portion 125; is the height corresponding to the overlapping area of ​​the truncated cone of the connecting portion 124 and the second end portion 125; is the volume of the overlapping area between the truncated cone of the second end portion 125 and the connecting line portion 124 . The calculation ideas and methods are similar to The calculation ideas and methods are consistent with each other and will not be described in detail here.

[0098] If the second end 125 is a truncated cone, that is, the third top surface and the third bottom surface are designed to be circular, then: ; is the radius of the third top circular surface of the truncated cone of the second end portion 125, is the radius of the third bottom circle of the truncated cone of the second end 125. . is the height of the truncated cone of the second end portion 125 in a direction perpendicular to the third top surface and the third bottom surface.

[0099] It should be understood that if one wants to reduce the metal proportion in a certain layer structure, the volume of at least one of the first end 121, the second end 125 and the connecting portion 124 can be reduced. , , , , , and On the contrary, if you want to increase the metal proportion in a certain layer structure, you can increase the volume of at least one of the first end 121, the second end 125 and the connecting portion 124. , , , , , and at least one of .

[0100] In this embodiment, the column section 122 and transition section 123 of the first end 121, and the second end 125 are respectively designed as truncated cone structures, and the connecting portion 124 is designed as a cylinder. In some other embodiments, the column section 122 and transition section 123 of the first end 121, the second end 125, and the connecting portion 124 may also be other shapes, which are not specifically limited here.

[0101] It should be noted that is the sum of the volumes of all metals in each dielectric layer 110. If there is only a wiring metal layer 120 in the dielectric layer 110, then is the sum of the volumes of all wiring metal layers 120 in the layer. If the dielectric layer 110 has other metal components in addition to the wiring metal layer 120, then It is the sum of the volume of all wiring metal layers 120 in this layer and the volume of other metal components.

[0102] Optional, ; is the bottom area of ​​each dielectric layer 110; is the thickness of each dielectric layer 110 .

[0103] It is easy to understand that the metal volume ratio is consistent with the metal content ratio. That is, if the difference in the metal content ratio between two adjacent dielectric layers 110 exceeds a preset value, at least one of the following methods is used to adjust the difference in the metal content ratio between adjacent dielectric layers 110 in the final substrate 100 structure to not more than 8%. The optional adjustment methods are as follows:

[0104] 1. In and A pseudo wiring layer 140 is added to the smaller layer of the two. The pseudo wiring layer 140 is made of metal material. The pseudo wiring layer 140 is not electrically connected to the wiring metal layer 120. The pseudo wiring layer 140 is used to increase the metal content in the layer structure to adjust the thermal expansion coefficient of the layer, ensure that the metal content in each layer structure is roughly consistent, and the thermal stress is uniform. It is beneficial to reduce warping deformation and prevent structural delamination. In addition, the pseudo wiring layer 140 also has the function of improving structural strength and heat dissipation performance.

[0105] 2. and In the larger layer, at least one of the cross-section of the connection portion 124, the first end portion 121 and the second end portion 125 is reduced; or the number of wirings in each wiring metal layer 120 is reduced. In this way, the metal content of the layer can be reduced, so that the metal content in the layer is roughly the same as the metal content in the adjacent layer. That is, the metal content ratio of each layer is roughly the same.

[0106] 3. and In the smaller layer, at least one of the connection portion 124, the first end portion 121 and the second end portion 125 is enlarged in cross section; or the number of wirings in each wiring metal layer 120 is increased. In this way, the metal content of the layer can be increased, so that the metal content in the layer is substantially the same as the metal content in the adjacent layer.

[0107] 4. and The thickness of the dielectric layer 110 is increased in the larger layer of the two layers, so that the proportion of metal content in the layer can also be reduced.

[0108] It should be noted that the preset value in this embodiment is 8%. In some other implementations, the preset value can be flexibly set, for example, the preset value can be any value between 0.1% and 8%. Among the above-mentioned multiple adjustment methods, one or more of them can be selected for adjustment. Only the layer with a smaller metal content can be adjusted, or only the layer with a larger metal content can be adjusted. Alternatively, the metal content in the two-layer structure can be adjusted at the same time, the metal content of the layer with a lower metal content can be increased, and the metal content of the layer with a higher metal content can be reduced, so that the metal content ratio in the two-layer structure is roughly the same. No specific limitation is made here.

[0109] It can be understood that in this embodiment, combined with the above-mentioned volume calculation method of the wiring structure 1201, the volume of each wiring metal layer 120 before and after adjustment can be accurately calculated, so the adjustment amount of the metal content can be accurately controlled by calculation, which can greatly improve the wiring accuracy and accurately control the metal content in each dielectric layer 110.

[0110] Optional, if , that is, the metal content ratio of two adjacent layers is quite different, the difference is between 20% and 40%, then and A dummy wiring layer 140 is added to the smaller layer of the two layers. Adding the dummy wiring layer 140 can quickly and conveniently increase the metal content in the layer structure.

[0111] If the metal content ratio difference between two adjacent layers is small, for example, between 8.01% and 19.99%, it can be adjusted by increasing or decreasing the line width of the wiring layer, increasing or decreasing the number of wiring structures 1201, etc. Of course, it is not limited to this, and the above-mentioned metal content adjustment methods are applicable.

[0112] Optional, in The pseudo wiring layer 140 is added to the first layer, and the The number of wiring in the layer; in the ( ) layer and / or the ( Layer increase The number of wiring structures 1201 in the layer is reduced. It can be understood that the volume of each dielectric layer 110 structure is roughly equal, that is, the space for setting the wiring metal layer 120 is limited. If a pseudo wiring layer 140 is added to a certain layer, the pseudo wiring layer 140 occupies a certain wiring space, and the number of wiring structures 1201 of the wiring metal layer 120 in the layer structure needs to be sacrificed. In order to ensure that the number of overall wiring structures 1201 is not reduced, the wiring structures 1201 can be compensated in the adjacent dielectric layer 110, that is, a corresponding number of wiring structures 1201 are added to the structure of the adjacent dielectric layer 110.

[0113] Exemplarily, it is assumed that a pseudo wiring layer 140 is added to the structure of the fifth dielectric layer 110. Accordingly, the number of wiring structures 1201 in the structure of the fifth dielectric layer 110 is reduced by 10. A total of about 10 wiring structures 1201 are added to the structure of the fourth and / or sixth dielectric layer 110 for compensation. This arrangement increases the structural strength of the fifth dielectric layer 110 and improves the heat dissipation performance. In addition, since the number of wiring structures 1201 is reduced in the structure of the fifth dielectric layer 110, the distance between the wiring structures 1201 of the fourth and sixth layers is increased, which is beneficial to reducing the capacitance effect.

[0114] The calculation formula according to the capacitance value is C=εS / d, where C is the capacitance value, ε is the dielectric constant, S is the overlapping area of ​​the wiring metal layer 120 after projection in the thickness direction, and d is the vertical distance of the wiring metal layer 120 in the thickness direction. It can be seen that reducing the projected overlapping area S of the wiring metal layer 120, or increasing the vertical distance between the wiring metal layers 120, is conducive to reducing the capacitance value, thereby reducing the capacitance effect. In this embodiment, since a pseudo wiring layer 140 is provided, it is possible to increase the vertical distance between the wiring metal layers 120 and reduce the overlapping area of ​​the wiring metal layers 120 after projection in the thickness direction. Therefore, it is conducive to reducing the capacitance effect, thereby increasing the transmission speed of the signal and reducing crosstalk.

[0115] Combination Figure 6 In this embodiment, in the third dielectric layer 113, the number of wiring structures 1201 is reduced, and a dummy wiring layer 140 is provided. In the second dielectric layer 112, the number of wiring structures 1201 is correspondingly increased as compensation. In addition, the spacing between the fourth wiring metal layer 120 and the second wiring metal layer 132 in the thickness direction is increased, which is beneficial to reduce the capacitance effect.

[0116] It is worth noting that in Figure 6 In the cross-sectional perspective shown, due to the perspective, some dummy wiring layers 140 and the wiring metal layers 120 appear to be connected, but in fact they are designed to be misaligned in the thickness direction, that is, there is actually no electrical connection.

[0117] Combination Figure 8 Optionally, in the same dielectric layer 110, the wiring metal layer 120 has multiple wiring structures 1201. The line width, line diameter, etc. of each wiring structure 1201 may be different. For example, some line widths are thick, as shown by W2 in the figure; some line widths are relatively thin, as shown by W1 in the figure. With this arrangement, where the line diameter is thinner, the projected overlapping area with the wiring metal layer 120 of the adjacent layer in the thickness direction is smaller, which is beneficial to reduce the capacitance effect, thereby increasing the signal transmission speed and reducing crosstalk. In high-frequency applications, a smaller line width can improve the resolution of the signal, thereby improving the performance of the circuit. In addition, some thinner line widths can increase the spacing between the wiring structures 1201 in the same layer structure, thereby reducing the crosstalk between the wiring structures 1201 in the same layer.

[0118] Combination Fig. 9 and Fig.10, shows a schematic diagram of the distribution of the wiring structure 1201 and the pseudo wiring layer 140 in the dielectric layer 110 in a certain layer structure. It is easy to understand that the shape, quantity, distribution position, etc. of the pseudo wiring layer 140 are not specifically limited. Since the pseudo wiring layer 140 has no electrical connection function, the end structure is omitted in the structure. The pseudo wiring layer 140 can be one or more pseudo wiring units, and the shape, size and distribution position of each pseudo wiring unit can be flexibly set, and can be a regular shape or an irregular shape. Its parameters such as wire diameter, wire width and length can be flexibly designed according to actual conditions. No specific limitation is made here.

[0119] Combination Fig.11 In some embodiments, if the number of wiring structures 1201 in a layer is reduced due to the provision of a dummy wiring layer 140, it is not necessary to compensate for the sacrificed wiring structures 1201 in the remaining layers without affecting the overall performance of the substrate 100. It is sufficient to ensure that the metal content in each layer structure is approximately the same.

[0120] Optionally, a pseudo wiring mark 143 is arranged on the cutting road 180 of the substrate 100. The pseudo wiring mark 143 is located on the outermost dielectric layer 110. The pseudo wiring mark 143 can improve the structural strength of the substrate 100 and reduce the warping deformation in the process technology. At the same time, it is beneficial to improve the heat dissipation performance.

[0121] Combination Figure 12 to Figure 14 Optionally, a stress release portion 150 is provided on the pseudo wiring identification portion 143 on the cutting path 180. The stress release portion 150 is a groove provided on the pseudo wiring identification portion 143. The stress release portion 150 can be designed to be circular, rectangular, rhombus, triangular, elliptical, crescent or other arbitrary shapes. In the present embodiment, the cross-section of the stress release portion 150 shown is N-shaped or Z-shaped. Of course, it can also be Y-shaped, H-shaped, L-shaped, U-shaped, S-shaped, T-shaped, cross-shaped or W-shaped. By providing the stress release portion 150, it is beneficial to the stress release of the substrate 100 structure, and improves heat dissipation and air permeability. In addition, the stress release portion 150 can also enhance the bonding force between the substrate 100 and the plastic package 300 or the colloid, and enhance the bonding force between the pseudo wiring identification portion 143 and the dielectric layer 110, so that the structure is more reliable and prevents delamination.

[0122] Optionally, there are multiple stress release parts 150, and the multiple stress release parts 150 are centrally symmetrically distributed. The symmetrical distribution method is conducive to balancing stress and alleviating structural warping. It should be understood that in some embodiments, the multiple stress release parts 150 can also be symmetrically distributed in an axisymmetric manner, which is not specifically limited here.

[0123] Optionally, each stress release portion 150 includes a first side and a second side that are arranged opposite to each other, and the first side and the second side are arranged symmetrically. In this embodiment, if the thickness direction of the substrate 100 is taken as the up-down direction, a Z-shaped stress groove is provided on the pseudo wiring identification portion 143 to balance the stress in the front-to-back direction. An N-shaped stress groove is provided on the pseudo wiring identification portion 143 to balance the stress in the left-to-right direction.

[0124] Combination Fig.15 Optionally, each pseudo wiring identification portion 143 is in a cross shape. The cross-shaped intersection is located at the intersection of the horizontal and vertical cutting paths 180. The pseudo wiring identification portion 143 is only distributed in a part of the cutting path 180, and does not completely cover the cutting path 180. The pseudo wiring identification portion 143 can not only improve the strength, improve the supporting performance, reduce the warping deformation, and improve the heat dissipation performance, but also play a role in identification and positioning. For example, it can be used to position and identify when mounting the chip 200 on the substrate 100, and serve as a positioning reference.

[0125] Optionally, a bump 160 is formed in the uppermost dielectric layer 110, and the bump 160 is used to electrically connect to an external device. In this embodiment, the bump 160 is welded to a pad on the chip 200 to achieve electrical connection.

[0126] Combination Figures 16 to 19 The embodiment of the present invention further provides a substrate 100, which is prepared by the substrate 100 wiring method of the 2.5D package structure 10 in any of the above embodiments. Exemplarily, the preparation method is as follows:

[0127] A carrier 171 is provided. The carrier 171 may be made of glass, silicon oxide, metal or other materials.

[0128] The adhesive film layer 172 is spin-coated on the carrier 171. The adhesive film layer 172 is made of thermoplastic material, such as epoxy resin, polyimide, benzocyclobutene and other polymer composite materials. The adhesive film layer 172 can be separated by irradiating UV light.

[0129] Step S1: Spin-coat a photoresist layer 173 on the film layer 172. Cover the photoresist layer 173 with a photomask, and form a first pattern layer opening 174 on the photoresist layer 173 by an exposure and development process. Electroplating, sputtering, or chemical plating is used again to electroplate metal in the first pattern layer opening 174 to form an initial metal layer 175. Remove the excess photoresist layer 173.

[0130] Step S2: Spin-coat the first dielectric layer 111 on the initial metal layer 175. The first dielectric layer 111 covers the initial metal layer 175, and the thickness of the first dielectric layer 111 is greater than the thickness of the initial metal layer 175. Optionally, the dielectric layer 110 can be formed by any process of spin coating, spray coating, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD). The material of the dielectric layer 110 can be at least one of silicon nitride, silicon oxynitride, polyimide and benzocyclobutene.

[0131] Step S3: Cover the first dielectric layer 111 with the photomask again, and form a second pattern layer opening 1111 on the first dielectric layer 111 by exposure and development process. Electroplating metal is formed in the second pattern layer opening 1111 by any one of sputtering, chemical plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) to form a first wiring metal layer 131.

[0132] In this embodiment, since the initial metal layer 175 and the first wiring metal layer 131 are both located in the first dielectric layer 111, the initial metal layer 175 can be regarded as a part of the first wiring metal layer 131. When calculating the metal proportion in the first layer structure, the metal volume is the sum of the volumes of the initial metal layer 175 and the first wiring metal layer 131. Of course, in some embodiments, the initial metal layer 175 can also be omitted, which is not specifically limited here.

[0133] Repeat the above steps S2 and S3 to form a second dielectric layer 112 covering the first wiring metal layer 131. The second dielectric layer 112 is provided with a third graphic layer opening 1121. The second wiring metal layer 132 is formed in the third graphic layer opening 1121. This is repeated until the N+1 dielectric layer covering the N wiring metal layer 134 is formed. The N+1 dielectric layer is used as the top dielectric layer 117, and a window is provided thereon. Metal is filled in the window to form a bump 160.

[0134] It can be understood that the above steps S2 and S3 are repeated to sequentially form a second dielectric layer 112, open a third graphic layer opening 1121, form a second wiring metal layer 132, a third dielectric layer 113, a third wiring metal layer 133, ..., an Nth dielectric layer 114 and an Nth wiring metal layer 134.

[0135] Optionally, according to the pre-calculated metal content in each dielectric layer 110, if a dummy wiring layer 140 is to be formed, a dummy wiring layer pattern opening 141 is formed by using a mask when a graphic layer opening is formed in each dielectric layer 110. When metal is electroplated in the graphic layer opening to form the wiring metal layer 120, metal is electroplated in the dummy wiring layer pattern opening 141 to form the dummy wiring layer 140.

[0136] After the Nth wiring metal layer 134 is made, a top dielectric layer 117, i.e., the N+1th dielectric layer, is spin-coated. A window is opened on the top dielectric layer 117, and metal is electroplated in the window to form a bump 160. Optionally, a cross-shaped pseudo wiring identification portion 143 is formed on the top dielectric layer 117. A hollow stress release portion 150, such as an N-shaped groove or a Z-shaped groove, is etched on the pseudo wiring identification portion 143. It plays a role in stress release and identification.

[0137] Optionally, in the above-mentioned method for preparing the substrate 100, a stress balancing groove is opened on any one or any multiple layers or each layer of the dielectric layer 110. Metal is filled in the stress balancing groove. After the dielectric layer 110 is baked and solidified, the metal in the stress balancing groove is removed. The metal in the stress balancing groove is not electrically connected to the wiring metal layer 120. One or more stress balancing grooves can be spaced from the wiring metal layer 120 in the dielectric layer 110 and can be arranged at any position of the dielectric layer 110. Optionally, one or more stress balancing grooves are distributed as much as possible in the dielectric layer 110 at the position corresponding to the cutting path 180 or the edge area 181 and other non-mounting areas, so that no etching interface or traces will be left in the wiring area of ​​the substrate 100, which is conducive to improving the wiring accuracy. At the same time, it can also effectively resist the baking thermal stress, thereby reducing the structural warping and deformation caused by the baking thermal stress, so that the surface of the substrate 100 structure is smoother and the structure is more reliable.

[0138] Optionally, a micro-etching process is used to remove the metal in the stress balancing groove, so that a micro-etching groove can be formed on the surface of the dielectric layer 110, which is beneficial to improving the bonding force between the multi-layer structure and improving the structural reliability when another dielectric layer 110 is coated thereon.

[0139] Because in each layer of the structure, after each baking is completed, the metal in the stress balance groove will be removed through a micro-etching process, which can offset the baking stress without affecting the metal content in the overall structure.

[0140] The chip 200 is mounted on the bump 160. The solder joints of the chip 200 are welded to the bumps 160 on the substrate 100. After the chip 200 is mounted, the bottom filling glue is filled under the chip 200. The number and type of the mounted chips 200 can be flexibly set according to actual conditions. The chip 200 is plastic-encapsulated, and a plastic encapsulation body 300 covering the chip 200 is formed on one side of the substrate 100. After the plastic encapsulation body 300 is cured, the carrier 171 is removed.

[0141] The dielectric layer 110 is spin-coated on the side of the substrate 100 where the carrier 171 is removed, to form the bottom dielectric layer 115. An opening is formed on the bottom dielectric layer 115, and a metal is arranged in the opening to form a bump 160 on the other side of the substrate 100. The bump 160 on this side is implanted to form a solder ball 116. Finally, the single product is cut and separated.

[0142] Combination Fig. 20 In this embodiment, the chip 200 mounted on the substrate 100 is not limited to one type, but may be multiple types, for example, the chip 200 includes a first chip and a second chip of different types. The first chip and the second chip are mounted on the substrate 100 respectively.

[0143] In summary, the substrate wiring method of the 2.5D package structure 10, the substrate 100 and the package structure 10 provided in the embodiment of the present invention have the following beneficial effects, including:

[0144] The substrate wiring method, substrate 100 and packaging structure 10 of the 2.5D packaging structure 10 provided in the present application, the substrate 100 adopts a hierarchical structure in which multiple dielectric layers 110 are stacked. A wiring metal layer 120 is provided in each dielectric layer 110. By controlling the metal volume proportion in each dielectric layer 110, the metal volume proportion in the adjacent two layers does not exceed 8%. In this way, it can be ensured that the metal content in each dielectric layer 110 is roughly consistent, so that the thermal expansion coefficient of each layer of the hierarchical structure is similar, reducing the warping deformation and structural stratification caused by thermal stress, and improving the structural reliability. In addition, the design of the pseudo wiring layer 140 is conducive to controlling the metal content in each layer structure, which is conducive to improving the structural strength and alleviating the warping deformation. It is conducive to improving the heat dissipation performance. It also helps to balance the thermal stress in the process and maintain the flatness of the substrate 100 structure.

[0145] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A substrate wiring method for a 2.5D packaging structure, characterized in that: The substrate comprises a plurality of stacked dielectric layers, each dielectric layer is provided with a wiring metal layer; the substrate wiring method comprises: Calculate the volume of each dielectric layer with the wiring metal layer ; Calculate the volume of metal in each dielectric layer , i is a natural number between 1 and N; N is the number of dielectric layers provided with the wiring metal layer; Calculate the metal volume percentage in each dielectric layer ; ; ； like , at least one of the following methods is used for adjustment:

1. In and A dummy wiring layer is added to the smaller layer of the two layers, the dummy wiring layer is made of metal material, and the dummy wiring layer is not electrically connected to the wiring metal layer; 2. The wiring metal layer includes a first end portion, a connection portion, and a second end portion connected in sequence; and In the larger layer of the two, reducing the cross section of at least one of the connection portion, the first end portion, and the second end portion; or reducing the number of wirings in each wiring metal layer; 3. and In the smaller layer of the two, the cross section of at least one of the connection portion, the first end portion and the second end portion is increased; or the number of wirings in each wiring metal layer is increased; 4. and The thickness of the dielectric layer is increased in the larger of the two.

2. The substrate wiring method of the 2.5D packaging structure according to claim 1, characterized in that: When N is greater than or equal to 5, .

3. The substrate wiring method of the 2.5D packaging structure according to claim 1, characterized in that: The wiring metal layer includes a first end portion, a connection portion, and a second end portion connected in sequence; ;in, represents the volume of the first end; Indicates the volume of the connecting line; represents the volume of the second end; m represents the number of wirings in each wiring metal layer.

4. The substrate wiring method of the 2.5D packaging structure according to claim 3, characterized in that: The first end portion includes a connected column section and a transition section; the transition section is connected to the connecting portion; and the volume of the first end portion is the sum of the volume of the column section and the volume of the transition section.

5. The substrate wiring method of the 2.5D package structure according to claim 4, characterized in that: ; is the area of ​​the first top surface of the column segment, is the area of ​​the first bottom surface of the column segment; the first top surface and the first bottom surface are arranged opposite to each other; is the height of the column segment in a direction perpendicular to the first top surface and the first bottom surface; ; is the area of ​​the second top surface of the transition section, is the area of ​​the second bottom surface of the transition section; the second top surface and the second bottom surface are arranged opposite to each other; is the height of the transition section in a direction perpendicular to the second top surface and the second bottom surface; wherein, is the volume of the overlapping portion of the column segment at the first end and the column segment at the first end; ； ; is the length of the connecting line; is the cross-sectional area of ​​the connecting line; ; is the area of ​​the third top surface of the cylinder at the second end, is the area of ​​the third bottom surface of the column at the second end; the third top surface and the third bottom surface are arranged oppositely; is the height of the second end in a direction perpendicular to the third top surface and the third bottom surface; is the volume of the overlapping portion of the column at the second end and the column where the connecting line portion is located.

6. The substrate wiring method of the 2.5D packaging structure according to claim 5, characterized in that: If the first top surface of the column segment is circular, then ; b is the radius of the circle where the first top surface is located; ; is the central angle corresponding to the overlapping part of the column where the column segment and the transition segment are located; is the height of the overlapping portion of the column where the transition section is located and the column section in a direction perpendicular to the first top surface; If the third top surface of the second end portion is circular, then ; is the radius of the circle where the third top surface is located; ; is the central angle corresponding to the overlapping portion of the cylinder at the second end and the cylinder where the connecting line portion is located; It is the height of the overlapping portion of the column at the second end and the column where the connecting portion is located in the direction perpendicular to the third top surface.

7. The substrate wiring method of the 2.5D packaging structure according to claim 1, characterized in that: ; is the bottom area of ​​each dielectric layer; is the thickness of each dielectric layer.

8. The substrate wiring method of the 2.5D packaging structure according to claim 1, characterized in that: like , then in and The dummy wiring layer is added to the smaller layer of the two.

9. The substrate wiring method of the 2.5D packaging structure according to claim 1, characterized in that: In the The pseudo wiring layer is increased and the first The number of wiring in the layer; in the first ( ) layer and / or the ( ) layer increases Reduced amount of routing in the layer.

10. The substrate wiring method of the 2.5D packaging structure according to claim 1, characterized in that: A pseudo wiring mark portion is arranged on the cutting path of the substrate, and the pseudo wiring mark portion is located on the outermost dielectric layer.

11. The substrate wiring method of the 2.5D packaging structure according to claim 10, characterized in that: A stress release portion is provided on the pseudo wiring mark portion on the cutting path.

12. The substrate wiring method of the 2.5D packaging structure according to claim 11, characterized in that: There are multiple stress release parts, and the multiple stress release parts are distributed symmetrically around the center; Each of the stress release portions includes a first side and a second side that are oppositely disposed, and the first side and the second side are symmetrically disposed.

13. The substrate wiring method of the 2.5D package structure according to any one of claims 1 to 12, characterized in that: include: forming an initial metal layer; Forming a first dielectric layer covering the initial metal layer; wherein the first dielectric layer has a second graphic layer opening exposing the initial metal layer; Filling metal in the opening of the second graphic layer to form a first wiring metal layer; Forming a second dielectric layer covering the first wiring metal layer; wherein the second dielectric layer is provided with a third graphic layer opening; forming a second wiring metal layer in the opening of the third graphic layer; And so on, until the N+1th dielectric layer covering the Nth wiring metal layer is formed; A window is provided on the N+1th dielectric layer; a metal is filled in the window to form a bump; Among them, a stress balancing groove is opened on at least any one dielectric layer; metal is filled in the stress balancing groove; after the dielectric layer is baked and solidified, the metal in the stress balancing groove is removed.

14. The substrate wiring method of the 2.5D packaging structure according to claim 13, characterized in that: The stress balancing groove is arranged in a non-mounting area of ​​the substrate, wherein the non-mounting area includes a cutting path and an edge area.

15. A substrate, characterized in that The 2.5D packaging structure is prepared by the substrate wiring method according to any one of claims 1 to 14.

16. A packaging structure, characterized in that: The invention comprises a component and the substrate as claimed in claim 15, wherein the component is mounted on the substrate and is electrically connected to the substrate.

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