A method for detecting the thickness of a PI passivation layer in a process of a multi-layer RDL and PI passivation layer encapsulation structure

Abstract

The application discloses a kind of in the process of containing multilayer RDL and PI passivation layer package structure PI passivation layer thickness detection method, comprising the following steps: first, respectively set measurement pattern in each chip corner and design opening, ensure that each layer PI passivation layer thickness measurement area is placed in different chip corner respectively, prevent multilayer PI passivation layer thickness measurement area stacking in same chip corner;Subsequently, the height difference in the opening of measurement pattern inside and outside is measured as the current PI passivation layer thickness.The application realizes the measurement of PI passivation layer thickness by designing opening in the flat place of chip corner, can realize the accurate measurement of the thickness of PI passivation layer, and then can accurately reflect and monitor the ability and stability of real process and process, while the inaccuracy of measuring thickness in the fluctuation area on RDL can be avoided, to provide a new idea for the measurement of PI passivation layer thickness.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to a method for detecting the thickness of the PI passivation layer in a packaging structure containing a multilayer RDL and a PI passivation layer. Background Technology

[0002] With the development of semiconductor chip packaging technology, multilayer RDL (Redirect Line Layer) and PI passivation layer stacked structures have become essential and widely used. To achieve high yield standards after multilayer stacking, precise and efficient testing and control of each process step in the stacking process are required. Among these, the testing of the thickness of the PI passivation layer after each hard bake is an important process indicator.

[0003] The existing method for measuring the thickness of PI passivation layer is to directly measure the height difference between the top and bottom openings of the effective pattern within the die (chip). Since most of the PI passivation layer in the effective pattern area within the die (chip) covers the RDL (Redirect Line Layer) with height, the application of the PI passivation layer on the RDL (Redirect Line Layer) will produce undulations. These undulating areas cannot accurately reflect the thickness of the applied PI passivation layer, and cannot achieve the purpose of accurately monitoring the thickness of each PI passivation layer. Summary of the Invention

[0004] To address the technical problems existing in the prior art, the present invention aims to provide a method for detecting the thickness of the PI passivation layer in a process containing a multilayer RDL and PI passivation layer packaging structure.

[0005] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows:

[0006] A method for detecting the thickness of the PI passivation layer in a packaging structure containing a multilayer RDL and a PI passivation layer includes the following steps:

[0007] First, set up measurement patterns and design openings at each chip corner to ensure that the measurement area for the thickness of each PI passivation layer is placed in a different chip corner, preventing the measurement areas for the thickness of multiple PI passivation layers from being stacked in the same chip corner.

[0008] The height difference between the inside and outside of the opening in the measurement pattern is then measured and used as the current PI passivation layer thickness.

[0009] Furthermore, measurement patterns and openings are designed on the flat areas at the corners of each chip.

[0010] Furthermore, there are four chip corners, and measurement patterns are sequentially set on the flat areas of the four chip corners to ensure that the measurement area for the thickness of each PI passivation layer is placed in a different chip corner.

[0011] Furthermore, the measurement pattern is obtained by adding the measurement pattern to the chip corner area of ​​the pattern inside the photomask used for the original PI photoresist exposure and then preparing it through a semiconductor photolithography process.

[0012] Furthermore, the measurement pattern is a pattern with a large opening area that is convenient for measurement, including square, circle, ellipse, regular polygon, and cross shape.

[0013] Furthermore, the steps for measuring the height difference between the inside and outside of the opening in the measurement graphic include:

[0014] The measurement pattern area at the corner of the chip is automatically located by an automatic measurement machine, so that the measurement path passes through the measurement pattern, thereby obtaining the height difference between the inside and outside of the opening of the measurement pattern, which is the thickness of the current PI passivation layer. To reduce errors, the value is taken multiple times to obtain the maximum, minimum, average and uniformity of the PI passivation layer thickness.

[0015] Furthermore, 13 points were selected in the measurement pattern area at each corner of the chip to measure the height difference, thereby obtaining the maximum, minimum, average, and uniformity of the PI passivation layer thickness.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] This invention discloses a method for measuring the thickness of a PI passivation layer in a packaging structure containing a multilayer RDL and a PI passivation layer. An opening is designed at a flat area at the corner of the chip to measure the thickness of the PI passivation layer, which can accurately measure the thickness of the PI passivation layer. This allows for accurate reflection and monitoring of the actual process and stability of the manufacturing process. At the same time, it can avoid the inaccuracy of measuring the thickness in the undulating area of ​​the RDL, providing a new approach to the measurement of PI passivation layer thickness. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the present invention;

[0019] Figure 2 A corner image of the chip showing the pattern inside the photomask used for the original PI adhesive exposure.

[0020] Figure 3 This is a schematic diagram of the measurement pattern of the present invention;

[0021] Figure 4-5 This is a schematic diagram of PI passivation layer thickness measurement;

[0022] Figure 6 This is a schematic diagram showing the locations of the 13 points selected in this invention. Detailed Implementation

[0023] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0024] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0025] like Figure 1-6 As shown, a method for detecting the thickness of the PI passivation layer in a packaging structure containing a multilayer RDL and a PI passivation layer includes the following steps:

[0026] Multilayer RDL (Redirect Line Layer) and PI passivation layer stacking are completed using conventional packaging technology. First, measurement patterns 2 are set on the flat areas of each die corner 1, and corresponding openings 3 are designed. The opening size is 50-100 micrometers. Specifically, measurement patterns 2 and openings 3 are set sequentially on the flat areas of the four die corners 1 to ensure that the measurement area of ​​each PI passivation layer thickness is placed in a different die corner 1, preventing the measurement areas of multiple PI passivation layer thicknesses from being stacked in the same die corner 1, which would cause inaccurate measurement.

[0027] The height difference between the inside and outside of the opening in the measurement pattern is then measured and used as the current PI passivation layer thickness. This allows for the effective utilization of the chip corner area and accurate measurement of the thickness of multiple PI passivation layers.

[0028] This invention avoids the inaccuracy caused by measuring the thickness of the PI passivation layer in undulating areas of the RDL by measuring the thickness on a flat surface. This enables accurate measurement of the PI passivation layer thickness, thereby accurately reflecting and monitoring the actual process and stability of the manufacturing process.

[0029] The fabrication of the measurement pattern 2 for chip corner 1 only requires the existing... Figure 2 The measurement pattern is added to the die corner area of ​​the photomask used for PI photoresist exposure, and then semiconductor photolithography processes such as coating, exposure, development, and hard baking are performed. Compared with the original process, no additional steps are added to the manufacturing process. Only the measurement pattern needs to be added during the photomask design. This reflects the convenience of the present invention in achieving accurate measurement of PI passivation layer thickness.

[0030] like Figure 3 As shown, in terms of graphic design, the measurement graphic 2 can be designed into various patterns, but it should be designed as a pattern with a large opening area that is easy to measure, such as square, circle, ellipse, regular polygon, cross, etc. Avoid designing it into a complex pattern with many sharp corners and a small opening area, as this is not conducive to measurement and will affect the accuracy of the measurement.

[0031] The steps for measuring the height difference between the inside and outside of the opening in a measurement graphic include:

[0032] The measurement pattern area of ​​the chip corner is automatically located by the automatic measurement machine. The measurement area of ​​each PI passivation layer thickness is placed in a different chip corner 1 to prevent multiple PI passivation layer thickness measurement areas from being stacked in the same chip corner 1. This ensures that the measurement path passes through the measurement pattern, thereby obtaining the height difference between the inside and outside of the opening of the measurement pattern, which is the thickness of the current PI passivation layer. To reduce errors, 13 points or other numbers of points are selected in the measurement pattern area of ​​each chip corner to measure the height difference. The values ​​are taken multiple times to obtain the maximum, minimum, average and uniformity of the PI passivation layer thickness, and the data are recorded and plotted in Table 1.

[0033] Table 1

[0034] thickness

[0035] Where Min represents the minimum value;

[0036] Max represents the maximum value;

[0037] Avg represents the average value;

[0038] U% represents uniformity, U% = (Max - Min) / (2 * Avg) * %.

[0039] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0040] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for detecting the thickness of a PI passivation layer in a manufacturing process containing a multilayer RDL and PI passivation layer packaging structure, characterized in that, Includes the following steps: First, set up measurement patterns and design openings on the flat areas of each chip corner. The opening size is 50-100 micrometers. Ensure that the measurement areas for the thickness of each PI passivation layer are placed in different chip corners to prevent multiple PI passivation layer thickness measurement areas from being stacked in the same chip corner. The height difference between the inside and outside of the opening in the measurement pattern is then measured and used as the current PI passivation layer thickness. There are four chip corners. Measurement patterns are set sequentially on the flat areas of the four chip corners to ensure that the measurement area for the thickness of each PI passivation layer is placed in a different chip corner. The measurement pattern is obtained by adding the measurement pattern to the corner area of ​​the chip in the photomask pattern used for the original PI photoresist exposure and then preparing it through a semiconductor photolithography process. The steps for measuring the height difference between the inside and outside of the opening in a measurement graphic include: The measurement pattern area at the corner of the chip is automatically located by the automatic measurement machine, so that the measurement path passes through the measurement pattern, thereby obtaining the height difference between the inside and outside of the opening of the measurement pattern, which is the thickness of the current PI passivation layer. In order to reduce the error, the value is taken multiple times and the maximum, minimum, average and uniformity of the PI passivation layer thickness are obtained. Thirteen points were selected in the measurement pattern area at each corner of the chip to measure the height difference, and the maximum, minimum, average and uniformity of the PI passivation layer thickness were obtained.

2. The method for detecting the thickness of the PI passivation layer in a packaging structure containing a multilayer RDL and a PI passivation layer according to claim 1, characterized in that, The measurement pattern is a pattern with a large opening area that is convenient for measurement, including square, circle, ellipse, regular polygon, and cross shape.

Images