A gallium nitride vertical JFET device with channel threshold modulation layer and N-I-P voltage withstanding region

Abstract

The application discloses a gallium nitride vertical JFET device with a channel threshold modulation layer and an N-I-P voltage resistance region and a preparation method thereof. The device comprises, from bottom to top, an N++ GaN substrate, an N-GaN drift region, a first I-type insulating region, a second I-type insulating region and an N-GaN drift region located on the surface of the N-GaN drift region, a first heavily doped P-type region, a channel region and a second heavily doped P-type region located on the surface of the first I-type insulating region, the N-GaN drift region and the second I-type insulating region respectively, a first gate, a source and a second gate located on the surface of the first heavily doped P-type region, the channel region and the second heavily doped P-type region respectively, a passivation layer located between the first gate and the source and between the second gate and the source, and a drain located on the other surface of the N++ GaN substrate. Since the heavily doped P-type region, the I-type insulating region, the N-GaN drift region and the N++ GaN substrate form the N-I-P voltage resistance region, the breakdown voltage of the device is improved, the N-type ultra-low-doped channel threshold modulation layer is introduced into the channel region, and the threshold voltage is also improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region and its fabrication method. Background Technology

[0002] Currently, lateral GaN HEMT devices are rapidly developing and maturing in RF and low-voltage power devices. Enhancement GaN HEMTs based on p-GaN cap layers and enhancement GaN HEMTs based on cascaded structures are gradually being applied. At present, the voltage rating of commercially available GaN HEMTs is usually below 650V, which has the advantage of switching speed in medium and low voltage applications. However, if it is necessary to further improve the voltage rating, vertical GaN will become the new focus, especially GaN vertical power devices based on homoepitaxial GaN substrates, which will become the future development direction for high voltage and high current.

[0003] Compared with lateral GaN HEMTs, vertical GaN devices have the following advantages: (1) for a given chip area, they have higher breakdown voltage and current capabilities; (2) the electric field peak of vertical GaN devices can be transferred from the surface to the drift region, which can suppress the occurrence of surface breakdown; (3) by using GaN homoepitaxial layer, the thermal mismatch ratio between the substrate and the drift region is reduced, which is beneficial to power dissipation; (4) due to less reliance on surface passivation, the dynamic on-resistance is more stable; (5) the defect density in the homoepitaxial layer is reduced. These advantages make vertical GaN devices particularly suitable for medium voltage (600-10kV) and high power scenarios.

[0004] To date, several 1.2kV-level vertical GaN transistors have been fabricated on GaN substrates, such as current aperture vertical electron transistors (CAVFETs), junction field-effect transistors (JFETs), trench MOSFETs, and fin-channel MOSFETs. In the conventional structure of a JFET, both the threshold voltage and forward current are related to the n-type impurity concentration in the channel. When the n-type impurity concentration is high, the threshold voltage is low and the forward current is high; conversely, when the n-type impurity concentration is low, the threshold voltage is high and the forward current is low. In other words, traditional vertical GaN transistors cannot simultaneously achieve high threshold voltage and large forward current. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region, and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region, comprising:

[0007] N++GaN substrate;

[0008] The N-GaN drift region is located on one side surface of the N++GaN substrate;

[0009] A first type I insulating region, a second type I insulating region, and an N GaN drift region are located on the surface of the N-GaN drift region away from the N++GaN substrate, with the first type I insulating region and the second type I insulating region located on opposite sides of the N-GaN drift region, respectively.

[0010] The first heavily doped P-type region, the channel region, and the second heavily doped P-type region are respectively located on the surface of the first type I insulating region, the N GaN drift region, and the side of the second type I insulating region away from the N++GaN substrate; the channel region includes an N-type ultra-low doped channel threshold modulation layer, and the channel threshold is in contact with the NGaN;

[0011] The first gate, source, and second gate are respectively located on the surface of the first heavily doped P-type region, the channel region, and the second heavily doped P-type region away from the N++GaN substrate;

[0012] A passivation layer located between the first gate and the source, and between the second gate and the source;

[0013] The drain electrode is located on the surface of the N++GaN substrate on the side away from the N-GaN drift region.

[0014] In one embodiment of the present invention, the doping concentration of the channel region gradually increases from bottom to top.

[0015] In one embodiment of the present invention, the channel region further includes an N GaN channel layer and an N++ GaN channel layer, wherein the N++ GaN channel layer is located on the side of the channel threshold modulation layer away from the N++ GaN substrate, and the N GaN channel layer is located between the channel threshold modulation layer and the N++ GaN channel layer.

[0016] In one embodiment of the present invention, the doping concentration of the channel threshold modulation layer is 0.5 × 10⁻⁶. 15 ~1×10 17 cm -3 .

[0017] In one embodiment of the present invention, the doping concentration of the N GaN channel layer is 5 × 10⁻⁶. 16 ~7×10 18 cm -3 .

[0018] In one embodiment of the present invention, the doping concentration of the N++GaN channel layer is 1×10⁻⁶. 18 ~5×10 19 cm -3 .

[0019] In one embodiment of the present invention, the doping concentration of the first heavily doped P-type region and the second heavily doped P-type region is 3 × 10⁻⁶. 17 ~5×10 19 cm -3 .

[0020] In one embodiment of the present invention, the doping concentration of the N-GaN drift region is 1×10⁻⁶. 15 ~5×10 18 cm -3 .

[0021] In a second aspect, the present invention provides a method for fabricating a gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region, comprising:

[0022] Provide an N++ GaN substrate;

[0023] An N-GaN drift layer and an N GaN drift region are sequentially deposited on one side surface of the N++GaN substrate;

[0024] After etching the first preset regions at both ends of the N GaN drift region, a first type I insulating region and a second type I insulating region are grown in the first preset regions at both ends, respectively.

[0025] A channel region is grown on the surface of the first type I insulating region, the N GaN drift region and the second type I insulating region, and the doping concentration of the channel region gradually increases from bottom to top.

[0026] After growing an AlN masking layer on the surface of the channel region, the AlN masking layer located in the second preset region at both ends of the channel region is etched away, and Mg ions are implanted to form a first heavily doped P-type region and a second heavily doped P-type region.

[0027] Thin the N++GaN substrate and fabricate a drain on its surface away from the N-GaN drift layer;

[0028] A source electrode is fabricated on the side surface of the channel region away from the N++GaN substrate, and a first gate electrode and a second gate electrode are fabricated on the side surfaces of the first heavily doped P-type region and the second heavily doped P-type region away from the N++GaN substrate, respectively.

[0029] After depositing passivation layers on the first heavily doped P-type region, the second heavily doped P-type region, the first gate, the second gate, and the source surface, holes are made in the passivation layers on the source, the first gate, and the second gate surfaces to bring out electrodes.

[0030] In one embodiment of the present invention, the step of growing a channel region on the surface of the first type I insulating region, the N GaN drift region, and the second type I insulating region includes:

[0031] Using metal-organic chemical vapor deposition (MOCVD), an N-type ultra-low doped channel threshold modulation layer, an N-GaN channel layer, and an N++GaN channel layer are sequentially grown on the surfaces of the first type I insulating region, the N GaN drift region, and the second type I insulating region.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] (1) This invention provides a gallium nitride vertical JFET device with a channel threshold modulation layer and an NIP breakdown voltage region, and its fabrication method. In this vertical JFET device, the first heavily doped P-type region, the first I-type insulating region, the N-GaN drift region, and the N++GaN substrate constitute the first NIP breakdown voltage region, and the second heavily doped P-type region, the second I-type insulating region, the N-GaN drift region, and the N++GaN substrate constitute the second NIP breakdown voltage region. This can improve the breakdown voltage of the device, and the electric field region with a high electric field value in the drift region of the device becomes larger, thereby reducing the electric field strength in the contact area between the P-type region and the N-type drift region. In addition, this invention introduces a channel threshold modulation layer in the channel region. The ultra-low doping method of the N-type layer can not only significantly improve the threshold voltage of the device, but also improve the electron mobility, thereby improving the operating frequency of the JFET device. At the same time, by increasing the doping concentration of the upper part of the channel threshold modulation layer, the forward current can be increased.

[0034] (2) The present invention adds a first type I insulating layer and a second type I insulating layer with high thermal conductivity to the pn junction, which is beneficial to improve the heat dissipation capability of the JFET device, reduce the junction temperature, prevent the JFET device from being damaged due to excessive junction temperature, and significantly improve the reliability.

[0035] (3) The present invention employs a multilayer doping method in the channel region, which can reduce the on-resistance and improve the quality factor of the JFET device.

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0037] Figure 1This is a schematic diagram of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP withstand voltage region provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic flowchart of a method for fabricating a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP withstand voltage region, provided in an embodiment of the present invention.

[0039] Figures 3a-3j This is a schematic diagram of the fabrication process of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region provided in an embodiment of the present invention;

[0040] Figure 4a The graph shows the transfer curves of conventional devices and gallium nitride vertical JFET devices with channel threshold modulation layers and NIP breakdown voltage regions.

[0041] Figure 4b This is a semi-logarithmic coordinate graph showing the transition curves of conventional devices and gallium nitride vertical JFET devices with a channel threshold modulation layer and a NIP breakdown voltage region.

[0042] Figure 5a This is a schematic diagram of the electric field distribution of a conventional device;

[0043] Figure 5b This is a schematic diagram of the electric field distribution of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region.

[0044] Figure 6 This is a comparison chart of the breakdown voltages of conventional devices and gallium nitride vertical JFET devices with a channel threshold modulation layer and a NIP breakdown voltage region. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0046] Figure 1 This is a schematic diagram of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region provided in an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region, characterized in that it includes:

[0047] N++GaN substrate;

[0048] The N-GaN drift region located on one side surface of the N++GaN substrate;

[0049] A first type I insulating region, a second type I insulating region, and an NGaN drift region are located on the surface of the N-GaN drift region away from the N++GaN substrate. The first type I insulating region and the second type I insulating region are located on both sides of the N-GaN drift region, respectively.

[0050] The first heavily doped P-type region, the channel region, and the second heavily doped P-type region are respectively located on the surface of the first type I insulating region, the N GaN drift region, and the second type I insulating region on the side away from the N++GaN substrate; the channel region includes an N-type ultra-low doped channel threshold modulation layer, and the channel threshold is in contact with the N GaN.

[0051] The first gate, source, and second gate are respectively located on the surface of the first heavily doped P-type region, the channel region, and the second heavily doped P-type region on the side away from the N++GaN substrate;

[0052] A passivation layer located between the first gate and the source, and between the second gate and the source;

[0053] The drain electrode is located on the surface of the N++GaN substrate on the side away from the N-GaN drift region.

[0054] Specifically, in this embodiment, the gallium nitride JFET device includes: an N++GaN substrate, an N-GaN drift region on the surface of the N++GaN substrate, a first type I insulating region, a second type I insulating region and an N GaN drift region on the surface of the N-GaN drift region, a first heavily doped P-type region on the surface of the first type I insulating region, a channel region on the surface of the N GaN drift region, and a second heavily doped P-type region on the surface of the second type I insulating region. The N GaN drift region is located between the first type I insulating region and the second type I insulating region. Thus, two NIP breakdown voltage regions can be formed in the device, namely: a first NIP breakdown voltage region composed of the first heavily doped P-type region, the first type I insulating region, the N-GaN drift region and the N++GaN substrate, and a second NIP breakdown voltage region composed of the second heavily doped P-type region, the second type I insulating region, the N-GaN drift region and the N++GaN substrate. In this embodiment, the two NIP withstand voltage regions help improve the breakdown voltage of the device. The electric field region with high electric field value in the drift region of the device becomes larger, thereby reducing the electric field strength in the contact area between the P-type region and the N-type drift region.

[0055] Optionally, the doping concentration of the N-GaN drift region is 1×10⁻⁶. 15 ~5×10 18 cm -3 The doping concentration of the first-doped P-type region and the second-doped P-type region is 3 × 10⁻⁶. 17 ~5×10 19 cm -3 .

[0056] Furthermore, the channel region of the aforementioned gallium nitride vertical JFET device includes an N-type ultra-low doped (N--) channel threshold modulation layer, which is located on the surface of the N GaN drift region away from the N++ GaN substrate, i.e., in... Figure 1 From this perspective, the channel threshold modulation layer is located on the upper surface of the N GaN drift region.

[0057] It should be understood that for GaN vertical JFET devices, when the gate voltage is zero volt, because the electrons in the N-type region of the channel are an order of magnitude lower than the holes in the P-type region, the electrons in the N-type region are depleted by the holes in the P-type region, generating a space charge region. Furthermore, the space charge region in the N-type region is large, and the two P-type regions can deplete the entire N-type channel, preventing the drain current from flowing to the source. When the gate voltage of the GaN vertical JFET device is greater than the threshold voltage, the space charge region in the N-type region decreases, and the drain current flows to the source. Since both the threshold voltage and the forward current are related to the N-type doping concentration in the channel, in conventional JFET devices, when the N-type impurity concentration is high, the forward current is large, but the threshold voltage is low; similarly, when the N-type impurity concentration is low, the threshold voltage is high, but the forward current is small. This embodiment, by introducing a channel threshold modulation layer in the channel region, can significantly improve the threshold voltage of the device through its ultra-low N-type doping method.

[0058] Optionally, the doping concentration in the channel region gradually increases from bottom to top. By increasing the doping concentration in the upper part of the channel threshold modulation layer, the forward current is increased. The electric field is concentrated within the insulating region by the breakdown voltage of the first type I insulating region and the second type I insulating region. After changing the high electric field region, the electric field strength in the contact region between the P-type and N-type drift regions can be reduced, thereby obtaining a GaN vertical JFET that simultaneously satisfies high threshold voltage, large forward current, and high breakdown voltage. For example, the channel region also includes an N GaN channel layer and an N++ GaN channel layer, wherein the N++ GaN channel layer is located on the side of the channel threshold modulation layer away from the N++ GaN substrate, and the NGaN channel layer is located between the channel threshold modulation layer and the N++ GaN channel layer. The doping concentration of the channel threshold modulation layer is 0.5 × 10⁻⁶. 15 ~1×10 17 cm -3 The doping concentration of the N GaN channel layer is 5 × 10⁻⁶. 16 ~7×10 18 cm -3 The doping concentration of the N++GaN channel layer is 1×10⁻⁶. 18 ~5×10 19 cm -3 .

[0059] Figure 2This is a schematic flowchart of a method for fabricating a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region, provided in an embodiment of the present invention. Figures 3a-3j This is a schematic diagram illustrating the fabrication process of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region, as provided in an embodiment of the present invention. Please refer to... Figure 2 , 3a ~3j, this embodiment of the invention also provides a method for fabricating a gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region, comprising:

[0060] S1. Provide an N++ GaN substrate;

[0061] S2. An N-GaN drift layer and an N GaN drift region are sequentially deposited on one side surface of an N++GaN substrate.

[0062] S3. After etching the first preset regions at both ends of the N GaN drift region, a first type I insulating region and a second type I insulating region are grown in the first preset regions at both ends, respectively.

[0063] S4. A channel region is grown on the surface of the first type I insulating region, the N GaN drift region and the second type I insulating region, and the doping concentration of the channel region gradually increases from bottom to top.

[0064] S5. After growing an AlN masking layer on the surface of the channel region, the AlN masking layer located in the second preset region at both ends of the channel region is etched away, and Mg ions are implanted to form a first heavily doped P-type region and a second heavily doped P-type region.

[0065] S6. Thin the N++GaN substrate and fabricate a drain on the surface of the substrate away from the N-GaN drift layer;

[0066] S7. A source electrode is fabricated on the side surface of the channel region away from the N++GaN substrate, and a first gate electrode and a second gate electrode are fabricated on the side surfaces of the first heavily doped P-type region and the second heavily doped P-type region away from the N++GaN substrate, respectively.

[0067] S8. After depositing passivation layers on the surfaces of the first heavily doped P-type region, the second heavily doped P-type region, the first gate, the second gate, and the source, holes are made in the passivation layers on the surfaces of the source, the first gate, and the second gate to bring out electrodes.

[0068] Specifically, please see Figures 3a-3bIn steps S1 and S2, the N++GaN substrate is first ultrasonically cleaned to eliminate dangling bonds on the surface, followed by drying and heat treatment. Then, metal-organic chemical vapor deposition (MOCVD) is used to sequentially deposit and grow an N-GaN drift layer with a thickness of 1μm to 3μm and an N-GaN drift region with a thickness of 5μm to 7μm on the surface of the N++GaN substrate to obtain an epitaxial wafer. The obtained epitaxial wafer is ultrasonically cleaned in acetone for 2 minutes to remove residual organic matter on the surface, followed by ultrasonic cleaning in ethanol for 3 minutes. Finally, it is rinsed with deionized water to remove residual acetone and ethanol, and dried with N2.

[0069] In step S3, such as Figures 3c-3d As shown, after coating, the first preset regions at both ends of the N GaN drift region are etched, and AlN is grown in the first preset regions at both ends using MOCVD process to form the first type I insulating region and the second type I insulating region on both sides of the N GaN drift region.

[0070] Further, please see Figure 3e In step S4, a channel region with a thickness of 1 μm to 3 μm is grown on the surface of the N GaN drift region, the first type I insulating region, and the second type I insulating region using MOCVD technology, including:

[0071] Using metal-organic chemical vapor deposition (MOCVD), an N-type ultra-low doped channel threshold modulation layer, an NGaN channel layer, and an N++GaN channel layer are sequentially grown on the surfaces of the first type I insulating region, the NGaN drift region, and the second type I insulating region.

[0072] In fact, the materials for the first type I insulation region and the second type I insulation region may also include silicon nitride, silicon oxide, etc., and this application does not limit them.

[0073] In step S5, a growth is performed on the surface of the channel region as follows: Figure 3f After removing the AlN masking layer shown and etching away the AlN masking layer in the second preset region, Mg ions are implanted into the second preset regions at both ends of the channel region (i.e., the regions not covered by the AlN masking layer on both sides). The concentration can be 1×10⁻⁶. 20 ~5×10 21 cm -3 After being annealed under high temperature and high pressure, it forms Figure 3g The first and second doped P-type regions are shown.

[0074] Please continue reading Figures 3h-3jIn steps S6-S7, the N++GaN substrate is first thinned, and then Ti / Al / Ni / Au metal is deposited on the surface of the N++GaN substrate away from the N-GaN drift layer using electron beam evaporation. Then, high-temperature annealing is performed in a rapid annealing furnace to form a good ohmic contact with the substrate, thus forming the drain. Similarly, Ti / Al / Ni / Au metal is deposited on the surface of the channel region away from the N++GaN substrate using electron beam evaporation, and Ni / Au metal is deposited on the surfaces of the first and second heavily doped P-type regions away from the N++GaN substrate. After high-temperature annealing, the source, first gate, and second gate are formed.

[0075] Finally, a passivation layer of approximately 50 nm thick SiNX or SiO2 is deposited above the source, first gate, second gate, first heavily doped P-type region, and second heavily doped P-type region using plasma chemical vapor deposition (PECVD). The nitrogen (N) source is provided by ammonia (NH3), and the silicon (Si) source is provided by silane (SiH4), thus avoiding direct contact between the first / second gate and the source. Through-holes are made in the passivation layer above the source, first gate, and second gate to bring out electrodes, thus obtaining... Figure 1 The image shows a gallium nitride vertical JFET transistor with a channel threshold modulation layer and a NIP region.

[0076] Figure 4a The graphs show the transfer curves of conventional devices and gallium nitride vertical JFET devices with a channel threshold modulation layer and a NIP breakdown voltage region. Figure 4b This is a semi-logarithmic coordinate graph showing the transfer curves of a conventional JFET device and a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region. It should be noted that a conventional JFET device, from bottom to top, includes: a drain, a substrate on the drain surface, an N-GaN drift region on the substrate surface, a channel region on the surface of the N-GaN drift region, a first P+GaN region and a second P+GaN region on both sides of the channel, a first gate on the surface of the first P+GaN region, a second gate on the surface of the second P+GaN region, and a source on the surface of the channel region. Figure 4a As shown, when the threshold voltage of both the conventional device and the gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region is 2.8V, the electron concentration in the channel region of the conventional device is 0.6 × 10⁻⁶. 16 cm -3 The forward current is less than that of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region. For example... Figure 4b As shown, when the forward current of both the conventional device and the gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region is 0.6A, the electron concentration in the channel region of the conventional device is 2.5 × 10⁻⁶. 16cm -3 The threshold voltage is less than that of devices with a channel threshold modulation layer.

[0077] Figure 5a This is a schematic diagram of the electric field distribution of a conventional device. Figure 5b This is a schematic diagram of the electric field distribution of a gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region. Please refer to... Figures 5a-5b At a voltage of 1800V, the type I insulation region makes the electric field distribution in the device drift region more uniform and reduces the electric field intensity in the contact area between the P-type region and the N-type drift region.

[0078] Figure 6 This is a comparison chart of the breakdown voltages of conventional devices and gallium nitride vertical JFET devices with a channel threshold modulation layer and a NIP breakdown region. (Example:) Figure 6 As shown, the breakdown voltage of conventional devices is around 1200V, while the breakdown voltage of gallium nitride vertical JFET devices with a channel threshold modulation layer and NIP withstand voltage region is around 1800V, which significantly improves the breakdown voltage.

[0079] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0080] (1) This invention provides a gallium nitride vertical JFET device with a channel threshold modulation layer and an NIP breakdown voltage region, and its fabrication method. In this vertical JFET device, the first heavily doped P-type region, the first I-type insulating region, the N-GaN drift region, and the N++GaN substrate constitute the first NIP breakdown voltage region, and the second heavily doped P-type region, the second I-type insulating region, the N-GaN drift region, and the N++GaN substrate constitute the second NIP breakdown voltage region. This can improve the breakdown voltage of the device, and the electric field region with a high electric field value in the drift region of the device becomes larger, thereby reducing the electric field strength in the contact area between the P-type region and the N-type drift region. In addition, this invention introduces a channel threshold modulation layer in the channel region. The ultra-low doping method of the N-type layer can not only significantly improve the threshold voltage of the device, but also improve the electron mobility, thereby improving the operating frequency of the JFET device. At the same time, by increasing the doping concentration of the upper part of the channel threshold modulation layer, the forward current can be increased.

[0081] (2) The present invention adds a first type I insulating layer and a second type I insulating layer with high thermal conductivity to the pn junction, which is beneficial to improve the heat dissipation capability of the JFET device, reduce the junction temperature, prevent the JFET device from being damaged due to excessive junction temperature, and significantly improve the reliability.

[0082] (3) The present invention employs a multilayer doping method in the channel region, which can reduce the on-resistance and improve the quality factor of the JFET device.

[0083] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0084] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine different embodiments or examples described in this specification.

[0085] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region, characterized in that, include: N++ GaN substrate; The N-GaN drift region is located on one side surface of the N++ GaN substrate; A first type I insulating region, a second type I insulating region, and an N GaN drift region are located on the surface of the N-GaN drift region away from the N++ GaN substrate, with the first type I insulating region and the second type I insulating region located on opposite sides of the N-GaN drift region, respectively. The first heavily doped P-type region, the channel region, and the second heavily doped P-type region are respectively located on the surface of the first type I insulating region, the N GaN drift region, and the side of the second type I insulating region away from the N++ GaN substrate; the channel region includes an N-type ultra-low doped channel threshold modulation layer, and the channel threshold modulation layer is in contact with the N GaN drift region; The first gate, source, and second gate are respectively located on the surface of the first heavily doped P-type region, the channel region, and the second heavily doped P-type region away from the N++ GaN substrate. A passivation layer located between the first gate and the source, and between the second gate and the source; The drain electrode is located on the surface of the N++ GaN substrate on the side away from the N-GaN drift region.

2. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 1, characterized in that, The doping concentration in the channel region gradually increases from bottom to top.

3. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 2, characterized in that, The channel region further includes an N GaN channel layer and an N++ GaN channel layer, wherein the N++ GaN channel layer is located on the side of the channel threshold modulation layer away from the N++ GaN substrate, and the N GaN channel layer is located between the channel threshold modulation layer and the N++ GaN channel layer.

4. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 3, characterized in that, The doping concentration of the channel threshold modulation layer is 0.5 × 10⁻⁶. 15 ~1×10 17 cm -3 .

5. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 3, characterized in that, The doping concentration of the N GaN channel layer is 5 × 10⁻⁶. 16 ~7×10 18 cm -3 .

6. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 3, characterized in that, The doping concentration of the N++ GaN channel layer is 1×10⁻⁶. 18 ~5×10 19 cm -3 .

7. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 1, characterized in that, The doping concentrations of the first heavily doped P-type region and the second heavily doped P-type region are 3 × 10⁻⁶. 17 ~5×10 19 cm -3 .

8. The gallium nitride vertical JFET device with a channel threshold modulation layer and a NIP breakdown voltage region according to claim 1, characterized in that, The doping concentration of the N-GaN drift region is 1×10⁻⁶. 15 ~5×10 18 cm -3 .

9. A method for fabricating a gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region, characterized in that, include: Provide an N++ GaN substrate; An N-GaN drift layer and an N GaN drift region are sequentially deposited on one side surface of the N++ GaN substrate; After etching the first preset regions at both ends of the N GaN drift region, a first type I insulating region and a second type I insulating region are grown in the first preset regions at both ends, respectively. A channel region is grown on the surface of the first type I insulating region, the N GaN drift region and the second type I insulating region, and the doping concentration of the channel region gradually increases from bottom to top. After growing an AlN masking layer on the surface of the channel region, the AlN masking layer located in the second preset region at both ends of the channel region is etched away, and Mg ions are implanted to form a first heavily doped P-type region and a second heavily doped P-type region. Thin the N++ GaN substrate and fabricate a drain on its surface away from the N-GaN drift layer; A source electrode is fabricated on the side surface of the channel region away from the N++ GaN substrate, and a first gate electrode and a second gate electrode are fabricated on the side surfaces of the first heavily doped P-type region and the second heavily doped P-type region away from the N++ GaN substrate, respectively. After depositing passivation layers on the first heavily doped P-type region, the second heavily doped P-type region, the first gate, the second gate, and the source surface, holes are made in the passivation layers on the source, the first gate, and the second gate surfaces to bring out electrodes.

10. The method for fabricating a gallium nitride vertical JFET device having a channel threshold modulation layer and a NIP breakdown voltage region according to claim 9, characterized in that, The step of growing channel regions on the surfaces of the first type I insulating region, the N GaN drift region, and the second type I insulating region includes: Using metal-organic chemical vapor deposition (MOCVD), an N-type ultra-low doped channel threshold modulation layer, an N-GaN channel layer, and an N++GaN channel layer are sequentially grown on the surfaces of the first type I insulating region, the N GaN drift region, and the second type I insulating region.

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